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Merge "Merge tag 'android14-6.1.68_r00' into branch 'android14-6.1'" into android14-6.1

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This commit is contained in:
Todd Kjos 2024-01-24 17:34:59 +00:00
commit f27fc6ba23
1419 changed files with 18494 additions and 9512 deletions
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9
Documentation/ABI/testing/sysfs-bus-optee-devices
View File

@ -6,3 +6,12 @@ Description:
OP-TEE bus provides reference to registered drivers under this directory. The <uuid>
matches Trusted Application (TA) driver and corresponding TA in secure OS. Drivers
are free to create needed API under optee-ta-<uuid> directory.
What: /sys/bus/tee/devices/optee-ta-<uuid>/need_supplicant
Date: November 2023
KernelVersion: 6.7
Contact: op-tee@lists.trustedfirmware.org
Description:
Allows to distinguish whether an OP-TEE based TA/device requires user-space
tee-supplicant to function properly or not. This attribute will be present for
devices which depend on tee-supplicant to be running.

7
Documentation/admin-guide/kernel-parameters.txt
View File

@ -5728,6 +5728,13 @@
This feature may be more efficiently disabled
using the csdlock_debug- kernel parameter.
smp.panic_on_ipistall= [KNL]
If a csd_lock_timeout extends for more than
the specified number of milliseconds, panic the
system. By default, let CSD-lock acquisition
take as long as they take. Specifying 300,000
for this value provides a 5-minute timeout.
smsc-ircc2.nopnp [HW] Don't use PNP to discover SMC devices
smsc-ircc2.ircc_cfg= [HW] Device configuration I/O port
smsc-ircc2.ircc_sir= [HW] SIR base I/O port

4
Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
View File

@ -62,6 +62,9 @@ properties:
- description: MPM pin number
- description: GIC SPI number for the MPM pin
'#power-domain-cells':
const: 0
required:
- compatible
- reg
@ -93,4 +96,5 @@ examples:
<86 183>,
<90 260>,
<91 260>;
#power-domain-cells = <0>;
};

5
Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
View File

@ -31,8 +31,9 @@ properties:
- const: renesas,rzg2l-irqc
'#interrupt-cells':
description: The first cell should contain external interrupt number (IRQ0-7) and the
second cell is used to specify the flag.
description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
cell is used to specify the flag.
const: 2
'#address-cells':

5
Documentation/devicetree/bindings/mfd/mt6397.txt
View File

@ -21,8 +21,10 @@ Required properties:
compatible:
"mediatek,mt6323" for PMIC MT6323
"mediatek,mt6331" for PMIC MT6331 and MT6332
"mediatek,mt6358" for PMIC MT6358 and MT6366
"mediatek,mt6357" for PMIC MT6357
"mediatek,mt6358" for PMIC MT6358
"mediatek,mt6359" for PMIC MT6359
"mediatek,mt6366", "mediatek,mt6358" for PMIC MT6366
"mediatek,mt6397" for PMIC MT6397
Optional subnodes:
@ -39,6 +41,7 @@ Optional subnodes:
- compatible: "mediatek,mt6323-regulator"
see ../regulator/mt6323-regulator.txt
- compatible: "mediatek,mt6358-regulator"
- compatible: "mediatek,mt6366-regulator", "mediatek-mt6358-regulator"
see ../regulator/mt6358-regulator.txt
- compatible: "mediatek,mt6397-regulator"
see ../regulator/mt6397-regulator.txt

2
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
View File

@ -59,7 +59,7 @@ properties:
maxItems: 4
clocks:
minItems: 3
minItems: 2
items:
- description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
- description: SDC MMC clock, MCLK

20
Documentation/virt/coco/sev-guest.rst
View File

@ -37,11 +37,11 @@ along with a description:
the return value. General error numbers (-ENOMEM, -EINVAL)
are not detailed, but errors with specific meanings are.
The guest ioctl should be issued on a file descriptor of the /dev/sev-guest device.
The ioctl accepts struct snp_user_guest_request. The input and output structure is
specified through the req_data and resp_data field respectively. If the ioctl fails
to execute due to a firmware error, then fw_err code will be set otherwise the
fw_err will be set to 0x00000000000000ff.
The guest ioctl should be issued on a file descriptor of the /dev/sev-guest
device. The ioctl accepts struct snp_user_guest_request. The input and
output structure is specified through the req_data and resp_data field
respectively. If the ioctl fails to execute due to a firmware error, then
the fw_error code will be set, otherwise fw_error will be set to -1.
The firmware checks that the message sequence counter is one greater than
the guests message sequence counter. If guest driver fails to increment message
@ -57,8 +57,14 @@ counter (e.g. counter overflow), then -EIO will be returned.
__u64 req_data;
__u64 resp_data;
/* firmware error code on failure (see psp-sev.h) */
__u64 fw_err;
/* bits[63:32]: VMM error code, bits[31:0] firmware error code (see psp-sev.h) */
union {
__u64 exitinfo2;
struct {
__u32 fw_error;
__u32 vmm_error;
};
};
};
2.1 SNP_GET_REPORT

2
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 1
SUBLEVEL = 57
SUBLEVEL = 68
EXTRAVERSION =
NAME = Curry Ramen

1
android/abi_gki_aarch64_db845c
View File

@ -773,6 +773,7 @@
sysfs_emit
sysfs_remove_link
system_power_efficient_wq
system_unbound_wq
system_wq
tasklet_init
tasklet_kill

1
android/abi_gki_aarch64_virtual_device
View File

@ -440,6 +440,7 @@
sysfs_remove_group
sysfs_remove_link
system_freezable_wq
system_unbound_wq
system_wq
__tasklet_schedule
tasklet_setup

16
arch/arm/boot/dts/am3517-evm.dts
View File

@ -271,13 +271,6 @@ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */
OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
@ -355,3 +348,12 @@ OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
>;
};
};
&omap3_pmx_wkup {
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */
OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */
>;
};
};

1
arch/arm/boot/dts/imx28-xea.dts
View File

@ -8,6 +8,7 @@
#include "imx28-lwe.dtsi"
/ {
model = "Liebherr XEA board";
compatible = "lwn,imx28-xea", "fsl,imx28";
};

2
arch/arm/boot/dts/imx6ul-pico.dtsi
View File

@ -121,6 +121,8 @@ ethphy1: ethernet-phy@1 {
max-speed = <100>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};

8
arch/arm/boot/dts/imx7s.dtsi
View File

@ -454,7 +454,7 @@ iomuxc_lpsr: pinctrl@302c0000 {
};
gpt1: timer@302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
@ -463,7 +463,7 @@ gpt1: timer@302d0000 {
};
gpt2: timer@302e0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
@ -473,7 +473,7 @@ gpt2: timer@302e0000 {
};
gpt3: timer@302f0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
@ -483,7 +483,7 @@ gpt3: timer@302f0000 {
};
gpt4: timer@30300000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_GPT4_ROOT_CLK>,

1
arch/arm/boot/dts/motorola-mapphone-common.dtsi
View File

@ -640,6 +640,7 @@ &uart1 {
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core 0x17c>;
overrun-throttle-ms = <500>;
};
&uart4 {

6
arch/arm/boot/dts/omap4-l4-abe.dtsi
View File

@ -109,6 +109,8 @@ mcbsp1: mcbsp@0 {
reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
@ -142,6 +144,8 @@ mcbsp2: mcbsp@0 {
reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
@ -175,6 +179,8 @@ mcbsp3: mcbsp@0 {
reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;

2
arch/arm/boot/dts/omap4-l4.dtsi
View File

@ -2043,6 +2043,8 @@ mcbsp4: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>; /* L4 Interconnect */
reg-names = "mpu";
clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;

6
arch/arm/boot/dts/omap5-l4-abe.dtsi
View File

@ -109,6 +109,8 @@ mcbsp1: mcbsp@0 {
reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
@ -142,6 +144,8 @@ mcbsp2: mcbsp@0 {
reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
@ -175,6 +179,8 @@ mcbsp3: mcbsp@0 {
reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;

14
arch/arm/boot/dts/qcom-mdm9615.dtsi
View File

@ -82,14 +82,12 @@ cxo_board {
};
};
regulators {
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-always-on;
};
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-always-on;
};
soc: soc {

2
arch/arm/boot/dts/r8a7792-blanche.dts
View File

@ -239,7 +239,7 @@ du1_pins: du1 {
};
keyboard_pins: keyboard {
pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02";
pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_2";
bias-pull-up;
};

4
arch/arm/include/asm/exception.h
View File

@ -10,10 +10,6 @@
#include <linux/interrupt.h>
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
#define __exception_irq_entry __irq_entry
#else
#define __exception_irq_entry
#endif
#endif /* __ASM_ARM_EXCEPTION_H */

1
arch/arm/lib/memset.S
View File

@ -17,6 +17,7 @@ ENTRY(__memset)
ENTRY(mmioset)
WEAK(memset)
UNWIND( .fnstart )
and r1, r1, #255 @ cast to unsigned char
ands r3, r0, #3 @ 1 unaligned?
mov ip, r0 @ preserve r0 as return value
bne 6f @ 1

7
arch/arm/mach-imx/mmdc.c
View File

@ -502,6 +502,10 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", ret);
if (!name) {
ret = -ENOMEM;
goto pmu_release_id;
}
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
@ -524,9 +528,10 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
pmu_register_err:
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
hrtimer_cancel(&pmu_mmdc->hrtimer);
pmu_release_id:
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
pmu_free:
kfree(pmu_mmdc);
return ret;

14
arch/arm/mach-omap1/timer32k.c
View File

@ -176,17 +176,18 @@ static u64 notrace omap_32k_read_sched_clock(void)
return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
}
static struct timespec64 persistent_ts;
static cycles_t cycles;
static unsigned int persistent_mult, persistent_shift;
/**
* omap_read_persistent_clock64 - Return time from a persistent clock.
* @ts: &struct timespec64 for the returned time
*
* Reads the time from a source which isn't disabled during PM, the
* 32k sync timer. Convert the cycles elapsed since last read into
* nsecs and adds to a monotonically increasing timespec64.
*/
static struct timespec64 persistent_ts;
static cycles_t cycles;
static unsigned int persistent_mult, persistent_shift;
static void omap_read_persistent_clock64(struct timespec64 *ts)
{
unsigned long long nsecs;
@ -206,10 +207,9 @@ static void omap_read_persistent_clock64(struct timespec64 *ts)
/**
* omap_init_clocksource_32k - setup and register counter 32k as a
* kernel clocksource
* @pbase: base addr of counter_32k module
* @size: size of counter_32k to map
* @vbase: base addr of counter_32k module
*
* Returns 0 upon success or negative error code upon failure.
* Returns: %0 upon success or negative error code upon failure.
*
*/
static int __init omap_init_clocksource_32k(void __iomem *vbase)

5
arch/arm/xen/enlighten.c
View File

@ -207,7 +207,7 @@ static void xen_power_off(void)
static irqreturn_t xen_arm_callback(int irq, void *arg)
{
xen_hvm_evtchn_do_upcall();
xen_evtchn_do_upcall();
return IRQ_HANDLED;
}
@ -487,7 +487,8 @@ static int __init xen_guest_init(void)
* for secondary CPUs as they are brought up.
* For uniformity we use VCPUOP_register_vcpu_info even on cpu0.
*/
xen_vcpu_info = alloc_percpu(struct vcpu_info);
xen_vcpu_info = __alloc_percpu(sizeof(struct vcpu_info),
1 << fls(sizeof(struct vcpu_info) - 1));
if (xen_vcpu_info == NULL)
return -ENOMEM;

2
arch/arm64/Kconfig
View File

@ -1295,6 +1295,8 @@ choice
config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
depends on !LD_IS_LLD || LLD_VERSION >= 130000
# https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
depends on AS_IS_GNU || AS_VERSION >= 150000
help
Say Y if you plan on running a kernel with a big-endian userspace.

46
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -1186,26 +1186,34 @@ sata1: sata@3210000 {
dma-coherent;
};
usb0: usb@3100000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
bus: bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
usb1: usb@3110000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
usb1: usb@3110000 {
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
};
ccn@4000000 {

1
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -398,6 +398,7 @@ micfil: audio-controller@30080000 {
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};

1
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
View File

@ -27,6 +27,7 @@ reg_eth_phy: regulator-eth-phy {
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

1
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -370,6 +370,7 @@ micfil: audio-controller@30080000 {
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
#sound-dai-cells = <0>;
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -1301,6 +1301,7 @@ usb_dwc3_0: usb@38100000 {
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
};
};
@ -1343,6 +1344,7 @@ usb_dwc3_1: usb@38200000 {
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
};
};

4
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1431,7 +1431,7 @@ usb_dwc3_0: usb@38100000 {
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg1>;
usb3-resume-missing-cas;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
@ -1463,7 +1463,7 @@ usb_dwc3_1: usb@38200000 {
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
power-domains = <&pgc_otg2>;
usb3-resume-missing-cas;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
View File

@ -8,5 +8,5 @@ &jpegdec {
};
&jpegenc {
compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
};

4
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
View File

@ -120,7 +120,7 @@ cp0_sdhci_pins: cp0-sdhi-pins-0 {
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
cp0_spi0_pins: cp0-spi-pins-0 {
cp0_spi1_pins: cp0-spi-pins-1 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
@ -170,7 +170,7 @@ &cp0_sdhci0 {
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
pinctrl-0 = <&cp0_spi1_pins>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>; /* CS0 */
status = "okay";

4
arch/arm64/boot/dts/marvell/cn9130-db.dtsi
View File

@ -307,7 +307,7 @@ &cp0_sdhci0 {
&cp0_spi1 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
pinctrl-0 = <&cp0_spi1_pins>;
reg = <0x700680 0x50>;
flash@0 {
@ -371,7 +371,7 @@ cp0_sdhci_pins: cp0-sdhi-pins-0 {
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
cp0_spi0_pins: cp0-spi-pins-0 {
cp0_spi1_pins: cp0-spi-pins-1 {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};

2
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View File

@ -72,7 +72,7 @@ led-1 {
};
};
memory {
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
};

2
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@ -54,7 +54,7 @@ key-wps {
};
};
memory {
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
};

4
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View File

@ -43,7 +43,7 @@ extcon_usb: extcon_iddig {
id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
};
usb_p1_vbus: regulator@0 {
usb_p1_vbus: regulator-usb-p1 {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
@ -52,7 +52,7 @@ usb_p1_vbus: regulator@0 {
enable-active-high;
};
usb_p0_vbus: regulator@1 {
usb_p0_vbus: regulator-usb-p0 {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;

52
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
View File

@ -30,14 +30,14 @@ reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
ntc@0 {
thermal-sensor {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <390000>;
@ -139,8 +139,8 @@ &mmc1 {
};
&pio {
i2c_pins_0: i2c0{
pins_i2c{
i2c_pins_0: i2c0 {
pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
@ -148,8 +148,8 @@ pins_i2c{
};
};
i2c_pins_1: i2c1{
pins_i2c{
i2c_pins_1: i2c1 {
pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
@ -157,8 +157,8 @@ pins_i2c{
};
};
i2c_pins_2: i2c2{
pins_i2c{
i2c_pins_2: i2c2 {
pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
@ -166,8 +166,8 @@ pins_i2c{
};
};
i2c_pins_3: i2c3{
pins_i2c{
i2c_pins_3: i2c3 {
pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
@ -175,8 +175,8 @@ pins_i2c{
};
};
i2c_pins_4: i2c4{
pins_i2c{
i2c_pins_4: i2c4 {
pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
@ -184,8 +184,8 @@ pins_i2c{
};
};
i2c_pins_5: i2c5{
pins_i2c{
i2c_pins_5: i2c5 {
pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
@ -193,8 +193,8 @@ pins_i2c{
};
};
spi_pins_0: spi0{
pins_spi{
spi_pins_0: spi0 {
pins_spi {
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
<PINMUX_GPIO86__FUNC_SPI0_CSB>,
<PINMUX_GPIO87__FUNC_SPI0_MO>,
@ -308,8 +308,8 @@ pins_clk {
};
};
spi_pins_1: spi1{
pins_spi{
spi_pins_1: spi1 {
pins_spi {
pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
<PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO163__FUNC_SPI1_A_MO>,
@ -318,8 +318,8 @@ pins_spi{
};
};
spi_pins_2: spi2{
pins_spi{
spi_pins_2: spi2 {
pins_spi {
pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
<PINMUX_GPIO1__FUNC_SPI2_MO>,
<PINMUX_GPIO2__FUNC_SPI2_CLK>,
@ -328,8 +328,8 @@ pins_spi{
};
};
spi_pins_3: spi3{
pins_spi{
spi_pins_3: spi3 {
pins_spi {
pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
<PINMUX_GPIO22__FUNC_SPI3_CSB>,
<PINMUX_GPIO23__FUNC_SPI3_MO>,
@ -338,8 +338,8 @@ pins_spi{
};
};
spi_pins_4: spi4{
pins_spi{
spi_pins_4: spi4 {
pins_spi {
pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
<PINMUX_GPIO18__FUNC_SPI4_CSB>,
<PINMUX_GPIO19__FUNC_SPI4_MO>,
@ -348,8 +348,8 @@ pins_spi{
};
};
spi_pins_5: spi5{
pins_spi{
spi_pins_5: spi5 {
pins_spi {
pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
<PINMUX_GPIO14__FUNC_SPI5_CSB>,
<PINMUX_GPIO15__FUNC_SPI5_MO>,

8
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@ -101,6 +101,8 @@ cros_ec_pwm: pwm {
&dsi0 {
status = "okay";
/delete-property/#size-cells;
/delete-property/#address-cells;
/delete-node/panel@0;
ports {
port {
@ -437,20 +439,20 @@ pins2 {
};
touchscreen_pins: touchscreen-pins {
touch_int_odl {
touch-int-odl {
pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
input-enable;
bias-pull-up;
};
touch_rst_l {
touch-rst-l {
pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
output-high;
};
};
trackpad_pins: trackpad-pins {
trackpad_int {
trackpad-int {
pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
input-enable;
bias-disable; /* pulled externally */

96
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -108,7 +108,7 @@ reserved_memory: reserved-memory {
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
@ -423,7 +423,7 @@ &mt6358_vsim2_reg {
&pio {
aud_pins_default: audiopins {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
<PINMUX_GPIO98__FUNC_I2S2_BCK>,
<PINMUX_GPIO101__FUNC_I2S2_LRCK>,
@ -445,7 +445,7 @@ pins_bus {
};
aud_pins_tdm_out_on: audiotdmouton {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
<PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
<PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
@ -457,7 +457,7 @@ pins_bus {
};
aud_pins_tdm_out_off: audiotdmoutoff {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
<PINMUX_GPIO170__FUNC_GPIO170>,
<PINMUX_GPIO171__FUNC_GPIO171>,
@ -471,13 +471,13 @@ pins_bus {
};
bt_pins: bt-pins {
pins_bt_en {
pins-bt-en {
pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
output-low;
};
};
ec_ap_int_odl: ec_ap_int_odl {
ec_ap_int_odl: ec-ap-int-odl {
pins1 {
pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
input-enable;
@ -485,7 +485,7 @@ pins1 {
};
};
h1_int_od_l: h1_int_od_l {
h1_int_od_l: h1-int-od-l {
pins1 {
pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
input-enable;
@ -493,7 +493,7 @@ pins1 {
};
i2c0_pins: i2c0 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
@ -502,7 +502,7 @@ pins_bus {
};
i2c1_pins: i2c1 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
@ -511,7 +511,7 @@ pins_bus {
};
i2c2_pins: i2c2 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
bias-disable;
@ -520,7 +520,7 @@ pins_bus {
};
i2c3_pins: i2c3 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
@ -529,7 +529,7 @@ pins_bus {
};
i2c4_pins: i2c4 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
bias-disable;
@ -538,7 +538,7 @@ pins_bus {
};
i2c5_pins: i2c5 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
@ -547,7 +547,7 @@ pins_bus {
};
i2c6_pins: i2c6 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
<PINMUX_GPIO12__FUNC_SDA6>;
bias-disable;
@ -555,7 +555,7 @@ pins_bus {
};
mmc0_pins_default: mmc0-pins-default {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
@ -570,13 +570,13 @@ pins_cmd_dat {
mediatek,pull-up-adv = <01>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_rst {
pins-rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <01>;
@ -584,7 +584,7 @@ pins_rst {
};
mmc0_pins_uhs: mmc0-pins-uhs {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
@ -599,19 +599,19 @@ pins_cmd_dat {
mediatek,pull-up-adv = <01>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_ds {
pins-ds {
pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_rst {
pins-rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-up-adv = <01>;
@ -619,7 +619,7 @@ pins_rst {
};
mmc1_pins_default: mmc1-pins-default {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
@ -629,7 +629,7 @@ pins_cmd_dat {
mediatek,pull-up-adv = <10>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
input-enable;
mediatek,pull-down-adv = <10>;
@ -637,7 +637,7 @@ pins_clk {
};
mmc1_pins_uhs: mmc1-pins-uhs {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
@ -648,7 +648,7 @@ pins_cmd_dat {
mediatek,pull-up-adv = <10>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
mediatek,pull-down-adv = <10>;
@ -656,15 +656,15 @@ pins_clk {
};
};
panel_pins_default: panel_pins_default {
panel_reset {
panel_pins_default: panel-pins-default {
panel-reset {
pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
output-low;
bias-pull-up;
};
};
pwm0_pin_default: pwm0_pin_default {
pwm0_pin_default: pwm0-pin-default {
pins1 {
pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
output-high;
@ -676,14 +676,14 @@ pins2 {
};
scp_pins: scp {
pins_scp_uart {
pins-scp-uart {
pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
<PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
};
};
spi0_pins: spi0 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
<PINMUX_GPIO86__FUNC_GPIO86>,
<PINMUX_GPIO87__FUNC_SPI0_MO>,
@ -693,7 +693,7 @@ pins_spi{
};
spi1_pins: spi1 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
<PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO163__FUNC_SPI1_A_MO>,
@ -703,20 +703,20 @@ pins_spi{
};
spi2_pins: spi2 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
<PINMUX_GPIO1__FUNC_SPI2_MO>,
<PINMUX_GPIO2__FUNC_SPI2_CLK>;
bias-disable;
};
pins_spi_mi {
pins-spi-mi {
pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
mediatek,pull-down-adv = <00>;
};
};
spi3_pins: spi3 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
<PINMUX_GPIO22__FUNC_SPI3_CSB>,
<PINMUX_GPIO23__FUNC_SPI3_MO>,
@ -726,7 +726,7 @@ pins_spi{
};
spi4_pins: spi4 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
<PINMUX_GPIO18__FUNC_SPI4_CSB>,
<PINMUX_GPIO19__FUNC_SPI4_MO>,
@ -736,7 +736,7 @@ pins_spi{
};
spi5_pins: spi5 {
pins_spi{
pins-spi {
pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
<PINMUX_GPIO14__FUNC_SPI5_CSB>,
<PINMUX_GPIO15__FUNC_SPI5_MO>,
@ -746,63 +746,63 @@ pins_spi{
};
uart0_pins_default: uart0-pins-default {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
};
};
uart1_pins_default: uart1-pins-default {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
};
pins_rts {
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins_cts {
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
input-enable;
};
};
uart1_pins_sleep: uart1-pins-sleep {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
};
pins_rts {
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins_cts {
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
input-enable;
};
};
wifi_pins_pwrseq: wifi-pins-pwrseq {
pins_wifi_enable {
pins-wifi-enable {
pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
output-low;
};
};
wifi_pins_wakeup: wifi-pins-wakeup {
pins_wifi_wakeup {
pins-wifi-wakeup {
pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
input-enable;
};

12
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View File

@ -178,7 +178,7 @@ &mmc1 {
&pio {
i2c_pins_0: i2c0 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
@ -187,7 +187,7 @@ pins_i2c{
};
i2c_pins_1: i2c1 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
@ -196,7 +196,7 @@ pins_i2c{
};
i2c_pins_2: i2c2 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
@ -205,7 +205,7 @@ pins_i2c{
};
i2c_pins_3: i2c3 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
@ -214,7 +214,7 @@ pins_i2c{
};
i2c_pins_4: i2c4 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
@ -223,7 +223,7 @@ pins_i2c{
};
i2c_pins_5: i2c5 {
pins_i2c{
pins_i2c {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;

242
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -1136,127 +1136,6 @@ thermal: thermal@1100b000 {
nvmem-cell-names = "calibration-data";
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
sustainable-power = <5000>;
trips {
threshold: trip-point0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
};
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@ -2031,4 +1910,125 @@ larb3: larb@1a002000 {
power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
};
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
sustainable-power = <5000>;
trips {
threshold: trip-point0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
};
};

2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@ -207,7 +207,7 @@ &i2c7 {
pinctrl-0 = <&i2c7_pins>;
pmic@34 {
#interrupt-cells = <1>;
#interrupt-cells = <2>;
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupt-controller;

39
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
View File

@ -48,7 +48,7 @@ key-0 {
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
reg = <0 0x40000000 0x2 0x00000000>;
};
reserved-memory {
@ -56,13 +56,8 @@ reserved-memory {
#size-cells = <2>;
ranges;
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@54600000 {
no-map;
reg = <0 0x54600000 0x0 0x200000>;
};
/* 12 MiB reserved for OP-TEE (BL32)
/*
* 12 MiB reserved for OP-TEE (BL32)
* +-----------------------+ 0x43e0_0000
* | SHMEM 2MiB |
* +-----------------------+ 0x43c0_0000
@ -75,6 +70,34 @@ optee_reserved: optee@43200000 {
no-map;
reg = <0 0x43200000 0 0x00c00000>;
};
scp_mem: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
vpu_mem: memory@53000000 {
compatible = "shared-dma-pool";
reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
};
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_mem: memory@54600000 {
no-map;
reg = <0 0x54600000 0x0 0x200000>;
};
snd_dma_mem: memory@60000000 {
compatible = "shared-dma-pool";
reg = <0 0x60000000 0 0x1100000>;
no-map;
};
apu_mem: memory@62000000 {
compatible = "shared-dma-pool";
reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
};
};
};

7
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -229,6 +229,7 @@ dsu-pmu {
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
status = "fail";
};
dmic_codec: dmic-codec {
@ -470,6 +471,8 @@ power-domain@MT8195_POWER_DOMAIN_VDEC1 {
power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
clock-names = "venc1-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -532,6 +535,8 @@ power-domain@MT8195_POWER_DOMAIN_VDEC2 {
power-domain@MT8195_POWER_DOMAIN_VENC {
reg = <MT8195_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_LARB>;
clock-names = "venc0-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -1984,7 +1989,7 @@ larb20: larb@1b010000 {
reg = <0 0x1b010000 0 0x1000>;
mediatek,larb-id = <20>;
mediatek,smi = <&smi_common_vpp>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
<&vencsys_core1 CLK_VENC_CORE1_GALS>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
clock-names = "apb", "smi", "gals";

12
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View File

@ -532,12 +532,12 @@ timer@2080000 {
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};

3
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
View File

@ -200,6 +200,9 @@ adv_bridge: bridge@39 {
pd-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>;
avdd-supply = <&pm8916_l6>;
a2vdd-supply = <&pm8916_l6>;
dvdd-supply = <&pm8916_l6>;
pvdd-supply = <&pm8916_l6>;
v1p2-supply = <&pm8916_l6>;
v3p3-supply = <&pm8916_l17>;

4
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -169,7 +169,7 @@ q6_region: memory@4ab00000 {
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
hwlocks = <&tcsr_mutex 0>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc {
@ -248,7 +248,7 @@ gcc: gcc@1800000 {
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
reg = <0x0 0x01905000 0x0 0x1000>;
reg = <0x0 0x01905000 0x0 0x20000>;
#hwlock-cells = <1>;
};

2
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -90,7 +90,7 @@ smem@4ab00000 {
reg = <0x0 0x4ab00000 0x0 0x00100000>;
no-map;
hwlocks = <&tcsr_mutex 0>;
hwlocks = <&tcsr_mutex 3>;
};
memory@4ac00000 {

2
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -1257,7 +1257,7 @@ apps_iommu: iommu@1ef0000 {
#size-cells = <1>;
#iommu-cells = <1>;
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x01e20000 0x40000>;
ranges = <0 0x01e20000 0x20000>;
reg = <0x01ef0000 0x3000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>;

5
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
View File

@ -109,11 +109,6 @@ rmtfs_mem: rmtfs@ca100000 {
qcom,client-id = <1>;
};
audio_mem: audio@cb400000 {
reg = <0 0xcb000000 0 0x400000>;
no-mem;
};
qseecom_mem: qseecom@cb400000 {
reg = <0 0xcb400000 0 0x1c00000>;
no-mem;

11
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -820,7 +820,8 @@ gcc: clock-controller@100000 {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<0>, <&pcie1_lane>,
<0>, <0>, <0>, <0>;
<0>, <0>, <0>,
<&usb_1_ssphy>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
@ -5337,6 +5338,14 @@ cpufreq_hw: cpufreq@18591000 {
reg = <0 0x18591000 0 0x1000>,
<0 0x18592000 0 0x1000>,
<0 0x18593000 0 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0",
"dcvsh-irq-1",
"dcvsh-irq-2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;

12
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View File

@ -145,6 +145,10 @@ panel_in_edp: endpoint {
};
};
&cpufreq_hw {
/delete-property/ interrupts-extended; /* reference to lmh_cluster[01] */
};
&psci {
/delete-node/ cpu0;
/delete-node/ cpu1;
@ -277,6 +281,14 @@ &BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
};
&lmh_cluster0 {
status = "disabled";
};
&lmh_cluster1 {
status = "disabled";
};
/*
* Reserved memory changes
*

2
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View File

@ -714,6 +714,8 @@ &wifi {
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
};
/* PINCTRL - additions to nodes defined in sdm845.dtsi */

14
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -1839,8 +1839,12 @@ pcie0_phy: phy@1c06000 {
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "refgen";
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@ -1938,8 +1942,12 @@ pcie1_phy: phy@1c0e000 {
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_CLK>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "refgen";
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@ -3701,7 +3709,7 @@ camnoc_virt: interconnect@ac00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8150-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x400>;
reg = <0 0x0b220000 0 0x30000>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>;
#interrupt-cells = <2>;

2
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -1778,7 +1778,7 @@ qup_uart6_default: qup-uart6-default-state {
};
qup_uart18_default: qup-uart18-default-state {
pins = "gpio58", "gpio59";
pins = "gpio68", "gpio69";
function = "qup18";
drive-strength = <2>;
bias-disable;

2
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -666,7 +666,7 @@ vpu_mmu: iommu@ff350800 {
vdec: video-codec@ff360000 {
compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
reg = <0x0 0xff360000 0x0 0x400>;
reg = <0x0 0xff360000 0x0 0x480>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;

1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
View File

@ -493,6 +493,7 @@ &i2c4 {
&i2s0 {
pinctrl-0 = <&i2s0_2ch_bus>;
pinctrl-1 = <&i2s0_2ch_bus_bclk_off>;
rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>;
status = "okay";

16
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -1062,7 +1062,9 @@ power-domain@RK3399_PD_VCODEC {
power-domain@RK3399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
<&cru HCLK_VDU>;
<&cru HCLK_VDU>,
<&cru SCLK_VDU_CA>,
<&cru SCLK_VDU_CORE>;
pm_qos = <&qos_video_m1_r>,
<&qos_video_m1_w>;
#power-domain-cells = <0>;
@ -1338,7 +1340,7 @@ vpu_mmu: iommu@ff650800 {
vdec: video-codec@ff660000 {
compatible = "rockchip,rk3399-vdec";
reg = <0x0 0xff660000 0x0 0x400>;
reg = <0x0 0xff660000 0x0 0x480>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
<&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
@ -2396,6 +2398,16 @@ i2s0_2ch_bus: i2s0-2ch-bus {
<4 RK_PA0 1 &pcfg_pull_none>;
};
i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
rockchip,pins =
<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PD1 1 &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none>,
<4 RK_PA0 1 &pcfg_pull_none>;
};
i2s0_8ch_bus: i2s0-8ch-bus {
rockchip,pins =
<3 RK_PD0 1 &pcfg_pull_none>,

2
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
View File

@ -172,7 +172,7 @@ &main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
clock-frequency = <100000>;
exp1: gpio@22 {
compatible = "ti,tca6424";

1
arch/arm64/configs/gki_defconfig
View File

@ -735,7 +735,6 @@ CONFIG_PANIC_TIMEOUT=-1
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_WQ_WATCHDOG=y
CONFIG_SCHEDSTATS=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_HIST_TRIGGERS=y
CONFIG_PID_IN_CONTEXTIDR=y

3
arch/arm64/include/asm/cputype.h
View File

@ -85,7 +85,8 @@
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
#define APM_CPU_PART_POTENZA 0x000
#define APM_CPU_PART_XGENE 0x000
#define APM_CPU_VAR_POTENZA 0x00
#define CAVIUM_CPU_PART_THUNDERX 0x0A1
#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2

17
arch/arm64/include/asm/setup.h
View File

@ -21,9 +21,22 @@ static inline bool arch_parse_debug_rodata(char *arg)
extern bool rodata_enabled;
extern bool rodata_full;
if (arg && !strcmp(arg, "full")) {
if (!arg)
return false;
if (!strcmp(arg, "full")) {
rodata_enabled = rodata_full = true;
return true;
}
if (!strcmp(arg, "off")) {
rodata_enabled = rodata_full = false;
return true;
}
if (!strcmp(arg, "on")) {
rodata_enabled = true;
rodata_full = true;
rodata_full = false;
return true;
}

2
arch/arm64/kvm/guest.c
View File

@ -865,7 +865,7 @@ u32 __attribute_const__ kvm_target_cpu(void)
break;
case ARM_CPU_IMP_APM:
switch (part_number) {
case APM_CPU_PART_POTENZA:
case APM_CPU_PART_XGENE:
return KVM_ARM_TARGET_XGENE_POTENZA;
}
break;

7
arch/arm64/mm/pageattr.c
View File

@ -29,8 +29,8 @@ bool can_set_direct_map(void)
*
* KFENCE pool requires page-granular mapping if initialized late.
*/
return (rodata_enabled && rodata_full) || debug_pagealloc_enabled() ||
arm64_kfence_can_set_direct_map();
return rodata_full || debug_pagealloc_enabled() ||
arm64_kfence_can_set_direct_map();
}
static int change_page_range(pte_t *ptep, unsigned long addr, void *data)
@ -105,8 +105,7 @@ static int change_memory_common(unsigned long addr, int numpages,
* If we are manipulating read-only permissions, apply the same
* change to the linear mapping of the pages that back this VM area.
*/
if (rodata_enabled &&
rodata_full && (pgprot_val(set_mask) == PTE_RDONLY ||
if (rodata_full && (pgprot_val(set_mask) == PTE_RDONLY ||
pgprot_val(clear_mask) == PTE_RDONLY)) {
for (i = 0; i < area->nr_pages; i++) {
__change_memory_common((u64)page_address(area->pages[i]),

10
arch/loongarch/include/asm/percpu.h
View File

@ -28,7 +28,7 @@ static inline void set_my_cpu_offset(unsigned long off)
#define __my_cpu_offset __my_cpu_offset
#define PERCPU_OP(op, asm_op, c_op) \
static inline unsigned long __percpu_##op(void *ptr, \
static __always_inline unsigned long __percpu_##op(void *ptr, \
unsigned long val, int size) \
{ \
unsigned long ret; \
@ -59,7 +59,7 @@ PERCPU_OP(and, and, &)
PERCPU_OP(or, or, |)
#undef PERCPU_OP
static inline unsigned long __percpu_read(void *ptr, int size)
static __always_inline unsigned long __percpu_read(void *ptr, int size)
{
unsigned long ret;
@ -96,7 +96,7 @@ static inline unsigned long __percpu_read(void *ptr, int size)
return ret;
}
static inline void __percpu_write(void *ptr, unsigned long val, int size)
static __always_inline void __percpu_write(void *ptr, unsigned long val, int size)
{
switch (size) {
case 1:
@ -128,8 +128,8 @@ static inline void __percpu_write(void *ptr, unsigned long val, int size)
}
}
static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
int size)
static __always_inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
int size)
{
switch (size) {
case 1:

9
arch/loongarch/mm/init.c
View File

@ -68,11 +68,11 @@ void copy_user_highpage(struct page *to, struct page *from,
{
void *vfrom, *vto;
vto = kmap_atomic(to);
vfrom = kmap_atomic(from);
vfrom = kmap_local_page(from);
vto = kmap_local_page(to);
copy_page(vto, vfrom);
kunmap_atomic(vfrom);
kunmap_atomic(vto);
kunmap_local(vfrom);
kunmap_local(vto);
/* Make sure this page is cleared on other CPU's too before using it */
smp_wmb();
}
@ -228,6 +228,7 @@ pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(".bss..swapper_pg_dir");
pgd_t invalid_pg_dir[_PTRS_PER_PGD] __page_aligned_bss;
#ifndef __PAGETABLE_PUD_FOLDED
pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss;
EXPORT_SYMBOL(invalid_pud_table);
#endif
#ifndef __PAGETABLE_PMD_FOLDED
pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;

12
arch/loongarch/net/bpf_jit.c
View File

@ -796,8 +796,6 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
/* function return */
case BPF_JMP | BPF_EXIT:
emit_sext_32(ctx, regmap[BPF_REG_0], true);
if (i == ctx->prog->len - 1)
break;
@ -844,14 +842,8 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
}
break;
case BPF_DW:
if (is_signed_imm12(off)) {
emit_insn(ctx, ldd, dst, src, off);
} else if (is_signed_imm14(off)) {
emit_insn(ctx, ldptrd, dst, src, off);
} else {
move_imm(ctx, t1, off, is32);
emit_insn(ctx, ldxd, dst, src, t1);
}
move_imm(ctx, t1, off, is32);
emit_insn(ctx, ldxd, dst, src, t1);
break;
}
break;

2
arch/mips/Kconfig
View File

@ -483,6 +483,7 @@ config MACH_LOONGSON2EF
config MACH_LOONGSON64
bool "Loongson 64-bit family of machines"
select ARCH_DMA_DEFAULT_COHERENT
select ARCH_SPARSEMEM_ENABLE
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_MIGHT_HAVE_PC_SERIO
@ -1304,6 +1305,7 @@ config CPU_LOONGSON64
select CPU_SUPPORTS_MSA
select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
select CPU_MIPSR2_IRQ_VI
select DMA_NONCOHERENT
select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC
select MIPS_ASID_BITS_VARIABLE

9
arch/mips/include/asm/mach-loongson64/boot_param.h
View File

@ -14,7 +14,11 @@
#define ADAPTER_ROM 8
#define ACPI_TABLE 9
#define SMBIOS_TABLE 10
#define MAX_MEMORY_TYPE 11
#define UMA_VIDEO_RAM 11
#define VUMA_VIDEO_RAM 12
#define MAX_MEMORY_TYPE 13
#define MEM_SIZE_IS_IN_BYTES (1 << 31)
#define LOONGSON3_BOOT_MEM_MAP_MAX 128
struct efi_memory_map_loongson {
@ -117,7 +121,8 @@ struct irq_source_routing_table {
u64 pci_io_start_addr;
u64 pci_io_end_addr;
u64 pci_config_addr;
u32 dma_mask_bits;
u16 dma_mask_bits;
u16 dma_noncoherent;
} __packed;
struct interface_info {

25
arch/mips/kernel/process.c
View File

@ -121,6 +121,19 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
/* Put the stack after the struct pt_regs. */
childksp = (unsigned long) childregs;
p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK;
/*
* New tasks lose permission to use the fpu. This accelerates context
* switching for most programs since they don't use the fpu.
*/
clear_tsk_thread_flag(p, TIF_USEDFPU);
clear_tsk_thread_flag(p, TIF_USEDMSA);
clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
#ifdef CONFIG_MIPS_MT_FPAFF
clear_tsk_thread_flag(p, TIF_FPUBOUND);
#endif /* CONFIG_MIPS_MT_FPAFF */
if (unlikely(args->fn)) {
/* kernel thread */
unsigned long status = p->thread.cp0_status;
@ -149,20 +162,8 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
p->thread.reg29 = (unsigned long) childregs;
p->thread.reg31 = (unsigned long) ret_from_fork;
/*
* New tasks lose permission to use the fpu. This accelerates context
* switching for most programs since they don't use the fpu.
*/
childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
clear_tsk_thread_flag(p, TIF_USEDFPU);
clear_tsk_thread_flag(p, TIF_USEDMSA);
clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
#ifdef CONFIG_MIPS_MT_FPAFF
clear_tsk_thread_flag(p, TIF_FPUBOUND);
#endif /* CONFIG_MIPS_MT_FPAFF */
#ifdef CONFIG_MIPS_FP_SUPPORT
atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
#endif

3
arch/mips/kvm/mmu.c
View File

@ -593,7 +593,7 @@ static int kvm_mips_map_page(struct kvm_vcpu *vcpu, unsigned long gpa,
gfn_t gfn = gpa >> PAGE_SHIFT;
int srcu_idx, err;
kvm_pfn_t pfn;
pte_t *ptep, entry, old_pte;
pte_t *ptep, entry;
bool writeable;
unsigned long prot_bits;
unsigned long mmu_seq;
@ -665,7 +665,6 @@ static int kvm_mips_map_page(struct kvm_vcpu *vcpu, unsigned long gpa,
entry = pfn_pte(pfn, __pgprot(prot_bits));
/* Write the PTE */
old_pte = *ptep;
set_pte(ptep, entry);
err = 0;

10
arch/mips/loongson64/env.c
View File

@ -13,6 +13,8 @@
* Copyright (C) 2009 Lemote Inc.
* Author: Wu Zhangjin, wuzhangjin@gmail.com
*/
#include <linux/dma-map-ops.h>
#include <linux/export.h>
#include <linux/pci_ids.h>
#include <asm/bootinfo.h>
@ -147,8 +149,14 @@ void __init prom_lefi_init_env(void)
loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
if (loongson_sysconf.dma_mask_bits < 32 ||
loongson_sysconf.dma_mask_bits > 64)
loongson_sysconf.dma_mask_bits > 64) {
loongson_sysconf.dma_mask_bits = 32;
dma_default_coherent = true;
} else {
dma_default_coherent = !eirq_source->dma_noncoherent;
}
pr_info("Firmware: Coherent DMA: %s\n", dma_default_coherent ? "on" : "off");
loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;

47
arch/mips/loongson64/init.c
View File

@ -49,8 +49,7 @@ void virtual_early_config(void)
void __init szmem(unsigned int node)
{
u32 i, mem_type;
static unsigned long num_physpages;
u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size;
phys_addr_t node_id, mem_start, mem_size;
/* Otherwise come from DTB */
if (loongson_sysconf.fw_interface != LOONGSON_LEFI)
@ -64,30 +63,46 @@ void __init szmem(unsigned int node)
mem_type = loongson_memmap->map[i].mem_type;
mem_size = loongson_memmap->map[i].mem_size;
mem_start = loongson_memmap->map[i].mem_start;
/* Memory size comes in MB if MEM_SIZE_IS_IN_BYTES not set */
if (mem_size & MEM_SIZE_IS_IN_BYTES)
mem_size &= ~MEM_SIZE_IS_IN_BYTES;
else
mem_size = mem_size << 20;
mem_start = (node_id << 44) | loongson_memmap->map[i].mem_start;
switch (mem_type) {
case SYSTEM_RAM_LOW:
case SYSTEM_RAM_HIGH:
start_pfn = ((node_id << 44) + mem_start) >> PAGE_SHIFT;
node_psize = (mem_size << 20) >> PAGE_SHIFT;
end_pfn = start_pfn + node_psize;
num_physpages += node_psize;
pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n",
(u32)node_id, mem_type, mem_start, mem_size);
pr_info(" start_pfn:0x%llx, end_pfn:0x%llx, num_physpages:0x%lx\n",
start_pfn, end_pfn, num_physpages);
memblock_add_node(PFN_PHYS(start_pfn),
PFN_PHYS(node_psize), node,
case UMA_VIDEO_RAM:
pr_info("Node %d, mem_type:%d\t[%pa], %pa bytes usable\n",
(u32)node_id, mem_type, &mem_start, &mem_size);
memblock_add_node(mem_start, mem_size, node,
MEMBLOCK_NONE);
break;
case SYSTEM_RAM_RESERVED:
pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n",
(u32)node_id, mem_type, mem_start, mem_size);
memblock_reserve(((node_id << 44) + mem_start), mem_size << 20);
case VIDEO_ROM:
case ADAPTER_ROM:
case ACPI_TABLE:
case SMBIOS_TABLE:
pr_info("Node %d, mem_type:%d\t[%pa], %pa bytes reserved\n",
(u32)node_id, mem_type, &mem_start, &mem_size);
memblock_reserve(mem_start, mem_size);
break;
/* We should not reserve VUMA_VIDEO_RAM as it overlaps with MMIO */
case VUMA_VIDEO_RAM:
default:
pr_info("Node %d, mem_type:%d\t[%pa], %pa bytes unhandled\n",
(u32)node_id, mem_type, &mem_start, &mem_size);
break;
}
}
/* Reserve vgabios if it comes from firmware */
if (loongson_sysconf.vgabios_addr)
memblock_reserve(virt_to_phys((void *)loongson_sysconf.vgabios_addr),
SZ_256K);
}
#ifndef CONFIG_NUMA

7
arch/parisc/Kconfig
View File

@ -105,9 +105,12 @@ config ARCH_HAS_ILOG2_U64
default n
config GENERIC_BUG
bool
default y
def_bool y
depends on BUG
select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
config GENERIC_BUG_RELATIVE_POINTERS
bool
config GENERIC_HWEIGHT
bool

9
arch/parisc/include/asm/alternative.h
View File

@ -34,7 +34,8 @@ void apply_alternatives(struct alt_instr *start, struct alt_instr *end,
/* Alternative SMP implementation. */
#define ALTERNATIVE(cond, replacement) "!0:" \
".section .altinstructions, \"aw\" !" \
".section .altinstructions, \"a\" !" \
".align 4 !" \
".word (0b-4-.) !" \
".hword 1, " __stringify(cond) " !" \
".word " __stringify(replacement) " !" \
@ -44,7 +45,8 @@ void apply_alternatives(struct alt_instr *start, struct alt_instr *end,
/* to replace one single instructions by a new instruction */
#define ALTERNATIVE(from, to, cond, replacement)\
.section .altinstructions, "aw" ! \
.section .altinstructions, "a" ! \
.align 4 ! \
.word (from - .) ! \
.hword (to - from)/4, cond ! \
.word replacement ! \
@ -52,7 +54,8 @@ void apply_alternatives(struct alt_instr *start, struct alt_instr *end,
/* to replace multiple instructions by new code */
#define ALTERNATIVE_CODE(from, num_instructions, cond, new_instr_ptr)\
.section .altinstructions, "aw" ! \
.section .altinstructions, "a" ! \
.align 4 ! \
.word (from - .) ! \
.hword -num_instructions, cond ! \
.word (new_instr_ptr - .) ! \

1
arch/parisc/include/asm/assembly.h
View File

@ -574,6 +574,7 @@
*/
#define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \
.section __ex_table,"aw" ! \
.align 4 ! \
.word (fault_addr - .), (except_addr - .) ! \
.previous

38
arch/parisc/include/asm/bug.h
View File

@ -17,24 +17,27 @@
#define PARISC_BUG_BREAK_ASM "break 0x1f, 0x1fff"
#define PARISC_BUG_BREAK_INSN 0x03ffe01f /* PARISC_BUG_BREAK_ASM */
#if defined(CONFIG_64BIT)
#define ASM_WORD_INSN ".dword\t"
#ifdef CONFIG_GENERIC_BUG_RELATIVE_POINTERS
# define __BUG_REL(val) ".word " __stringify(val) " - ."
#else
#define ASM_WORD_INSN ".word\t"
# define __BUG_REL(val) ".word " __stringify(val)
#endif
#ifdef CONFIG_DEBUG_BUGVERBOSE
#define BUG() \
do { \
asm volatile("\n" \
"1:\t" PARISC_BUG_BREAK_ASM "\n" \
"\t.pushsection __bug_table,\"aw\"\n" \
"2:\t" ASM_WORD_INSN "1b, %c0\n" \
"\t.short %c1, %c2\n" \
"\t.org 2b+%c3\n" \
"\t.pushsection __bug_table,\"a\"\n" \
"\t.align 4\n" \
"2:\t" __BUG_REL(1b) "\n" \
"\t" __BUG_REL(%c0) "\n" \
"\t.short %1, %2\n" \
"\t.blockz %3-2*4-2*2\n" \
"\t.popsection" \
: : "i" (__FILE__), "i" (__LINE__), \
"i" (0), "i" (sizeof(struct bug_entry)) ); \
"i" (0), "i" (sizeof(struct bug_entry)) ); \
unreachable(); \
} while(0)
@ -51,10 +54,12 @@
do { \
asm volatile("\n" \
"1:\t" PARISC_BUG_BREAK_ASM "\n" \
"\t.pushsection __bug_table,\"aw\"\n" \
"2:\t" ASM_WORD_INSN "1b, %c0\n" \
"\t.short %c1, %c2\n" \
"\t.org 2b+%c3\n" \
"\t.pushsection __bug_table,\"a\"\n" \
"\t.align 4\n" \
"2:\t" __BUG_REL(1b) "\n" \
"\t" __BUG_REL(%c0) "\n" \
"\t.short %1, %2\n" \
"\t.blockz %3-2*4-2*2\n" \
"\t.popsection" \
: : "i" (__FILE__), "i" (__LINE__), \
"i" (BUGFLAG_WARNING|(flags)), \
@ -65,10 +70,11 @@
do { \
asm volatile("\n" \
"1:\t" PARISC_BUG_BREAK_ASM "\n" \
"\t.pushsection __bug_table,\"aw\"\n" \
"2:\t" ASM_WORD_INSN "1b\n" \
"\t.short %c0\n" \
"\t.org 2b+%c1\n" \
"\t.pushsection __bug_table,\"a\"\n" \
"\t.align 4\n" \
"2:\t" __BUG_REL(1b) "\n" \
"\t.short %0\n" \
"\t.blockz %1-4-2\n" \
"\t.popsection" \
: : "i" (BUGFLAG_WARNING|(flags)), \
"i" (sizeof(struct bug_entry)) ); \

8
arch/parisc/include/asm/jump_label.h
View File

@ -15,10 +15,12 @@ static __always_inline bool arch_static_branch(struct static_key *key, bool bran
asm_volatile_goto("1:\n\t"
"nop\n\t"
".pushsection __jump_table, \"aw\"\n\t"
".align %1\n\t"
".word 1b - ., %l[l_yes] - .\n\t"
__stringify(ASM_ULONG_INSN) " %c0 - .\n\t"
".popsection\n\t"
: : "i" (&((char *)key)[branch]) : : l_yes);
: : "i" (&((char *)key)[branch]), "i" (sizeof(long))
: : l_yes);
return false;
l_yes:
@ -30,10 +32,12 @@ static __always_inline bool arch_static_branch_jump(struct static_key *key, bool
asm_volatile_goto("1:\n\t"
"b,n %l[l_yes]\n\t"
".pushsection __jump_table, \"aw\"\n\t"
".align %1\n\t"
".word 1b - ., %l[l_yes] - .\n\t"
__stringify(ASM_ULONG_INSN) " %c0 - .\n\t"
".popsection\n\t"
: : "i" (&((char *)key)[branch]) : : l_yes);
: : "i" (&((char *)key)[branch]), "i" (sizeof(long))
: : l_yes);
return false;
l_yes:

2
arch/parisc/include/asm/ldcw.h
View File

@ -56,7 +56,7 @@
})
#ifdef CONFIG_SMP
# define __lock_aligned __section(".data..lock_aligned")
# define __lock_aligned __section(".data..lock_aligned") __aligned(16)
#endif
#endif /* __PARISC_LDCW_H */

1
arch/parisc/include/asm/uaccess.h
View File

@ -41,6 +41,7 @@ struct exception_table_entry {
#define ASM_EXCEPTIONTABLE_ENTRY( fault_addr, except_addr )\
".section __ex_table,\"aw\"\n" \
".align 4\n" \
".word (" #fault_addr " - .), (" #except_addr " - .)\n\t" \
".previous\n"

2
arch/parisc/include/uapi/asm/errno.h
View File

@ -75,7 +75,6 @@
/* We now return you to your regularly scheduled HPUX. */
#define ENOSYM 215 /* symbol does not exist in executable */
#define ENOTSOCK 216 /* Socket operation on non-socket */
#define EDESTADDRREQ 217 /* Destination address required */
#define EMSGSIZE 218 /* Message too long */
@ -101,7 +100,6 @@
#define ETIMEDOUT 238 /* Connection timed out */
#define ECONNREFUSED 239 /* Connection refused */
#define EREFUSED ECONNREFUSED /* for HP's NFS apparently */
#define EREMOTERELEASE 240 /* Remote peer released connection */
#define EHOSTDOWN 241 /* Host is down */
#define EHOSTUNREACH 242 /* No route to host */

1
arch/parisc/include/uapi/asm/pdc.h
View File

@ -472,6 +472,7 @@ struct pdc_model { /* for PDC_MODEL */
unsigned long arch_rev;
unsigned long pot_key;
unsigned long curr_key;
unsigned long width; /* default of PSW_W bit (1=enabled) */
};
struct pdc_cache_cf { /* for PDC_CACHE (I/D-caches) */

7
arch/parisc/kernel/entry.S
View File

@ -462,13 +462,13 @@
* to a CPU TLB 4k PFN (4k => 12 bits to shift) */
#define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
#define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12)
#define PFN_START_BIT (63-ASM_PFN_PTE_SHIFT+(63-58)-PAGE_ADD_SHIFT)
/* Drop prot bits and convert to page addr for iitlbt and idtlbt */
.macro convert_for_tlb_insert20 pte,tmp
#ifdef CONFIG_HUGETLB_PAGE
copy \pte,\tmp
extrd,u \tmp,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
extrd,u \tmp,PFN_START_BIT,PFN_START_BIT+1,\pte
depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
(63-58)+PAGE_ADD_SHIFT,\pte
@ -476,8 +476,7 @@
depdi _HUGE_PAGE_SIZE_ENCODING_DEFAULT,63,\
(63-58)+PAGE_ADD_HUGE_SHIFT,\pte
#else /* Huge pages disabled */
extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
extrd,u \pte,PFN_START_BIT,PFN_START_BIT+1,\pte
depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
(63-58)+PAGE_ADD_SHIFT,\pte
#endif

5
arch/parisc/kernel/head.S
View File

@ -70,9 +70,8 @@ $bss_loop:
stw,ma %arg2,4(%r1)
stw,ma %arg3,4(%r1)
#if !defined(CONFIG_64BIT) && defined(CONFIG_PA20)
/* This 32-bit kernel was compiled for PA2.0 CPUs. Check current CPU
* and halt kernel if we detect a PA1.x CPU. */
#if defined(CONFIG_PA20)
/* check for 64-bit capable CPU as required by current kernel */
ldi 32,%r10
mtctl %r10,%cr11
.level 2.0

1
arch/parisc/kernel/vmlinux.lds.S
View File

@ -131,6 +131,7 @@ SECTIONS
RO_DATA(8)
/* unwind info */
. = ALIGN(4);
.PARISC.unwind : {
__start___unwind = .;
*(.PARISC.unwind)

3
arch/powerpc/include/asm/nohash/32/pte-40x.h
View File

@ -69,9 +69,6 @@
#define _PTE_NONE_MASK 0
/* Until my rework is finished, 40x still needs atomic PTE updates */
#define PTE_ATOMIC_UPDATES 1
#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
#define _PAGE_BASE (_PAGE_BASE_NC)

7
arch/powerpc/include/asm/nohash/32/pte-8xx.h
View File

@ -94,6 +94,13 @@ static inline pte_t pte_wrprotect(pte_t pte)
#define pte_wrprotect pte_wrprotect
static inline int pte_read(pte_t pte)
{
return (pte_val(pte) & _PAGE_RO) != _PAGE_NA;
}
#define pte_read pte_read
static inline int pte_write(pte_t pte)
{
return !(pte_val(pte) & _PAGE_RO);

2
arch/powerpc/include/asm/nohash/64/pgtable.h
View File

@ -197,7 +197,7 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
{
unsigned long old;
if (pte_young(*ptep))
if (!pte_young(*ptep))
return 0;
old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
return (old & _PAGE_ACCESSED) != 0;

2
arch/powerpc/include/asm/nohash/pgtable.h
View File

@ -25,7 +25,9 @@ static inline int pte_write(pte_t pte)
return pte_val(pte) & _PAGE_RW;
}
#endif
#ifndef pte_read
static inline int pte_read(pte_t pte) { return 1; }
#endif
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }

8
arch/powerpc/kernel/entry_32.S
View File

@ -135,8 +135,9 @@ ret_from_syscall:
lis r4,icache_44x_need_flush@ha
lwz r5,icache_44x_need_flush@l(r4)
cmplwi cr0,r5,0
bne- 2f
bne- .L44x_icache_flush
#endif /* CONFIG_PPC_47x */
.L44x_icache_flush_return:
kuep_unlock
lwz r4,_LINK(r1)
lwz r5,_CCR(r1)
@ -170,10 +171,11 @@ syscall_exit_finish:
b 1b
#ifdef CONFIG_44x
2: li r7,0
.L44x_icache_flush:
li r7,0
iccci r0,r0
stw r7,icache_44x_need_flush@l(r4)
b 1b
b .L44x_icache_flush_return
#endif /* CONFIG_44x */
.globl ret_from_fork

13
arch/powerpc/kernel/fpu.S
View File

@ -23,6 +23,15 @@
#include <asm/feature-fixups.h>
#ifdef CONFIG_VSX
#define __REST_1FPVSR(n,c,base) \
BEGIN_FTR_SECTION \
b 2f; \
END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
REST_FPR(n,base); \
b 3f; \
2: REST_VSR(n,c,base); \
3:
#define __REST_32FPVSRS(n,c,base) \
BEGIN_FTR_SECTION \
b 2f; \
@ -41,9 +50,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
2: SAVE_32VSRS(n,c,base); \
3:
#else
#define __REST_1FPVSR(n,b,base) REST_FPR(n, base)
#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
#endif
#define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base)
#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
@ -67,6 +78,7 @@ _GLOBAL(store_fp_state)
SAVE_32FPVSRS(0, R4, R3)
mffs fr0
stfd fr0,FPSTATE_FPSCR(r3)
REST_1FPVSR(0, R4, R3)
blr
EXPORT_SYMBOL(store_fp_state)
@ -138,4 +150,5 @@ _GLOBAL(save_fpu)
2: SAVE_32FPVSRS(0, R4, R6)
mffs fr0
stfd fr0,FPSTATE_FPSCR(r6)
REST_1FPVSR(0, R4, R6)
blr

2
arch/powerpc/kernel/head_85xx.S
View File

@ -394,7 +394,7 @@ interrupt_base:
#ifdef CONFIG_PPC_FPU
FP_UNAVAILABLE_EXCEPTION
#else
EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, unknown_exception)
EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, emulation_assist_interrupt)
#endif
/* System Call Interrupt */

6
arch/powerpc/kernel/process.c
View File

@ -1163,11 +1163,11 @@ void kvmppc_save_user_regs(void)
usermsr = current->thread.regs->msr;
/* Caller has enabled FP/VEC/VSX/TM in MSR */
if (usermsr & MSR_FP)
save_fpu(current);
__giveup_fpu(current);
if (usermsr & MSR_VEC)
save_altivec(current);
__giveup_altivec(current);
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
if (usermsr & MSR_TM) {

2
arch/powerpc/kernel/setup-common.c
View File

@ -946,6 +946,8 @@ void __init setup_arch(char **cmdline_p)
/* Parse memory topology */
mem_topology_setup();
/* Set max_mapnr before paging_init() */
set_max_mapnr(max_pfn);
/*
* Release secondary cpus out of their spinloops at 0x60 now that

2
arch/powerpc/kernel/traps.c
View File

@ -1164,6 +1164,7 @@ static void emulate_single_step(struct pt_regs *regs)
__single_step_exception(regs);
}
#ifdef CONFIG_PPC_FPU_REGS
static inline int __parse_fpscr(unsigned long fpscr)
{
int ret = FPE_FLTUNK;
@ -1190,6 +1191,7 @@ static inline int __parse_fpscr(unsigned long fpscr)
return ret;
}
#endif
static void parse_fpe(struct pt_regs *regs)
{

2
arch/powerpc/kernel/vector.S
View File

@ -32,6 +32,7 @@ _GLOBAL(store_vr_state)
mfvscr v0
li r4, VRSTATE_VSCR
stvx v0, r4, r3
lvx v0, 0, r3
blr
EXPORT_SYMBOL(store_vr_state)
@ -108,6 +109,7 @@ _GLOBAL(save_altivec)
mfvscr v0
li r4,VRSTATE_VSCR
stvx v0,r4,r7
lvx v0,0,r7
blr
#ifdef CONFIG_VSX

1
arch/powerpc/mm/mem.c
View File

@ -288,7 +288,6 @@ void __init mem_init(void)
#endif
high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
set_max_mapnr(max_pfn);
kasan_late_init();

5
arch/powerpc/perf/core-book3s.c
View File

@ -1371,8 +1371,7 @@ static void power_pmu_disable(struct pmu *pmu)
/*
* Disable instruction sampling if it was enabled
*/
if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE)
val &= ~MMCRA_SAMPLE_ENABLE;
val &= ~MMCRA_SAMPLE_ENABLE;
/* Disable BHRB via mmcra (BHRBRD) for p10 */
if (ppmu->flags & PPMU_ARCH_31)
@ -1383,7 +1382,7 @@ static void power_pmu_disable(struct pmu *pmu)
* instruction sampling or BHRB.
*/
if (val != mmcra) {
mtspr(SPRN_MMCRA, mmcra);
mtspr(SPRN_MMCRA, val);
mb();
isync();
}

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