drm/amd/display: Disable phantom OTG after enable for plane disable
commit dc55b106ad477c67f969f3432d9070c6846fb557 upstream [Description] - Need to disable phantom OTG after it's enabled in order to restore it to it's original state. - If it's enabled and then an MCLK switch comes in we may not prefetch the correct data since the phantom OTG could already be in the middle of the frame. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1079,6 +1079,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
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struct dc_state *dangling_context = dc_create_state(dc);
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struct dc_state *current_ctx;
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struct pipe_ctx *pipe;
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struct timing_generator *tg;
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if (dangling_context == NULL)
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return;
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@ -1122,6 +1123,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
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if (should_disable && old_stream) {
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pipe = &dc->current_state->res_ctx.pipe_ctx[i];
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tg = pipe->stream_res.tg;
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/* When disabling plane for a phantom pipe, we must turn on the
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* phantom OTG so the disable programming gets the double buffer
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* update. Otherwise the pipe will be left in a partially disabled
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@ -1129,7 +1131,8 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
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* again for different use.
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*/
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if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
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pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
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if (tg->funcs->enable_crtc)
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tg->funcs->enable_crtc(tg);
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}
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dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
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disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
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@ -1146,6 +1149,15 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
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dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
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dc->hwss.post_unlock_program_front_end(dc, dangling_context);
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}
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/* We need to put the phantom OTG back into it's default (disabled) state or we
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* can get corruption when transition from one SubVP config to a different one.
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* The OTG is set to disable on falling edge of VUPDATE so the plane disable
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* will still get it's double buffer update.
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*/
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if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
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if (tg->funcs->disable_phantom_crtc)
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tg->funcs->disable_phantom_crtc(tg);
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}
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}
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}
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@ -167,6 +167,13 @@ static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
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REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
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}
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static void optc32_disable_phantom_otg(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
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}
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static void optc32_set_odm_bypass(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing)
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{
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@ -260,6 +267,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
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.enable_crtc = optc32_enable_crtc,
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.disable_crtc = optc32_disable_crtc,
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.phantom_crtc_post_enable = optc32_phantom_crtc_post_enable,
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.disable_phantom_crtc = optc32_disable_phantom_otg,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.is_counter_moving = optc1_is_counter_moving,
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.get_position = optc1_get_position,
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@ -184,6 +184,7 @@ struct timing_generator_funcs {
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bool (*disable_crtc)(struct timing_generator *tg);
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#ifdef CONFIG_DRM_AMD_DC_DCN
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void (*phantom_crtc_post_enable)(struct timing_generator *tg);
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void (*disable_phantom_crtc)(struct timing_generator *tg);
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#endif
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bool (*immediate_disable_crtc)(struct timing_generator *tg);
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bool (*is_counter_moving)(struct timing_generator *tg);
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