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net: stmmac: xgmac: fix handling of DPP safety error for DMA channels

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[ Upstream commit 46eba193d04f8bd717e525eb4110f3c46c12aec3 ]

Commit 56e58d6c8a ("net: stmmac: Implement Safety Features in
XGMAC core") checks and reports safety errors, but leaves the
Data Path Parity Errors for each channel in DMA unhandled at all, lead to
a storm of interrupt.
Fix it by checking and clearing the DMA_DPP_Interrupt_Status register.

Fixes: 56e58d6c8a ("net: stmmac: Implement Safety Features in XGMAC core")
Signed-off-by: Furong Xu <0x1207@gmail.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Furong Xu 2024-01-31 10:08:28 +08:00 committed by Greg Kroah-Hartman
parent fb8bfc6ea3
commit e42ff0844f
3 changed files with 60 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/ethernet/stmicro/stmmac/common.h
View File

@ -209,6 +209,7 @@ struct stmmac_safety_stats {
unsigned long mac_errors[32];
unsigned long mtl_errors[32];
unsigned long dma_errors[32];
unsigned long dma_dpp_errors[32];
};
/* Number of fields in Safety Stats */

3
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
View File

@ -282,6 +282,8 @@
#define XGMAC_RXCEIE BIT(4)
#define XGMAC_TXCEIE BIT(0)
#define XGMAC_MTL_ECC_INT_STATUS 0x000010cc
#define XGMAC_MTL_DPP_CONTROL 0x000010e0
#define XGMAC_DDPP_DISABLE BIT(0)
#define XGMAC_MTL_TXQ_OPMODE(x) (0x00001100 + (0x80 * (x)))
#define XGMAC_TQS GENMASK(25, 16)
#define XGMAC_TQS_SHIFT 16
@ -364,6 +366,7 @@
#define XGMAC_DCEIE BIT(1)
#define XGMAC_TCEIE BIT(0)
#define XGMAC_DMA_ECC_INT_STATUS 0x0000306c
#define XGMAC_DMA_DPP_INT_STATUS 0x00003074
#define XGMAC_DMA_CH_CONTROL(x) (0x00003100 + (0x80 * (x)))
#define XGMAC_SPH BIT(24)
#define XGMAC_PBLx8 BIT(16)

57
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
View File

@ -789,6 +789,43 @@ static const struct dwxgmac3_error_desc dwxgmac3_dma_errors[32]= {
{ false, "UNKNOWN", "Unknown Error" }, /* 31 */
};
static const char * const dpp_rx_err = "Read Rx Descriptor Parity checker Error";
static const char * const dpp_tx_err = "Read Tx Descriptor Parity checker Error";
static const struct dwxgmac3_error_desc dwxgmac3_dma_dpp_errors[32] = {
{ true, "TDPES0", dpp_tx_err },
{ true, "TDPES1", dpp_tx_err },
{ true, "TDPES2", dpp_tx_err },
{ true, "TDPES3", dpp_tx_err },
{ true, "TDPES4", dpp_tx_err },
{ true, "TDPES5", dpp_tx_err },
{ true, "TDPES6", dpp_tx_err },
{ true, "TDPES7", dpp_tx_err },
{ true, "TDPES8", dpp_tx_err },
{ true, "TDPES9", dpp_tx_err },
{ true, "TDPES10", dpp_tx_err },
{ true, "TDPES11", dpp_tx_err },
{ true, "TDPES12", dpp_tx_err },
{ true, "TDPES13", dpp_tx_err },
{ true, "TDPES14", dpp_tx_err },
{ true, "TDPES15", dpp_tx_err },
{ true, "RDPES0", dpp_rx_err },
{ true, "RDPES1", dpp_rx_err },
{ true, "RDPES2", dpp_rx_err },
{ true, "RDPES3", dpp_rx_err },
{ true, "RDPES4", dpp_rx_err },
{ true, "RDPES5", dpp_rx_err },
{ true, "RDPES6", dpp_rx_err },
{ true, "RDPES7", dpp_rx_err },
{ true, "RDPES8", dpp_rx_err },
{ true, "RDPES9", dpp_rx_err },
{ true, "RDPES10", dpp_rx_err },
{ true, "RDPES11", dpp_rx_err },
{ true, "RDPES12", dpp_rx_err },
{ true, "RDPES13", dpp_rx_err },
{ true, "RDPES14", dpp_rx_err },
{ true, "RDPES15", dpp_rx_err },
};
static void dwxgmac3_handle_dma_err(struct net_device *ndev,
void __iomem *ioaddr, bool correctable,
struct stmmac_safety_stats *stats)
@ -800,6 +837,13 @@ static void dwxgmac3_handle_dma_err(struct net_device *ndev,
dwxgmac3_log_error(ndev, value, correctable, "DMA",
dwxgmac3_dma_errors, STAT_OFF(dma_errors), stats);
value = readl(ioaddr + XGMAC_DMA_DPP_INT_STATUS);
writel(value, ioaddr + XGMAC_DMA_DPP_INT_STATUS);
dwxgmac3_log_error(ndev, value, false, "DMA_DPP",
dwxgmac3_dma_dpp_errors,
STAT_OFF(dma_dpp_errors), stats);
}
static int
@ -838,6 +882,12 @@ dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp,
value |= XGMAC_TMOUTEN; /* FSM Timeout Feature */
writel(value, ioaddr + XGMAC_MAC_FSM_CONTROL);
/* 5. Enable Data Path Parity Protection */
value = readl(ioaddr + XGMAC_MTL_DPP_CONTROL);
/* already enabled by default, explicit enable it again */
value &= ~XGMAC_DDPP_DISABLE;
writel(value, ioaddr + XGMAC_MTL_DPP_CONTROL);
return 0;
}
@ -871,7 +921,11 @@ static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev,
ret |= !corr;
}
err = dma & (XGMAC_DEUIS | XGMAC_DECIS);
/* DMA_DPP_Interrupt_Status is indicated by MCSIS bit in
* DMA_Safety_Interrupt_Status, so we handle DMA Data Path
* Parity Errors here
*/
err = dma & (XGMAC_DEUIS | XGMAC_DECIS | XGMAC_MCSIS);
corr = dma & XGMAC_DECIS;
if (err) {
dwxgmac3_handle_dma_err(ndev, ioaddr, corr, stats);
@ -887,6 +941,7 @@ static const struct dwxgmac3_error {
{ dwxgmac3_mac_errors },
{ dwxgmac3_mtl_errors },
{ dwxgmac3_dma_errors },
{ dwxgmac3_dma_dpp_errors },
};
static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats,