drm/amd/display: Update Z8 watermarks for DCN314

[ Upstream commit fa24e116f1ce3dcc55474f0b6ab0cac4e3ee34e1 ]

[Why & How]
Update from HW, need to lower watermarks for enter/enter+exit latency.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: 8f586cc16c1f ("drm/amd/display: Change default Z8 watermark values")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Nicholas Kazlauskas 2022-11-07 11:35:25 -05:00 committed by Greg Kroah-Hartman
parent cf49b2ff25
commit e22ef15610

View File

@ -148,8 +148,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {
.num_states = 5, .num_states = 5,
.sr_exit_time_us = 16.5, .sr_exit_time_us = 16.5,
.sr_enter_plus_exit_time_us = 18.5, .sr_enter_plus_exit_time_us = 18.5,
.sr_exit_z8_time_us = 442.0, .sr_exit_z8_time_us = 280.0,
.sr_enter_plus_exit_z8_time_us = 560.0, .sr_enter_plus_exit_z8_time_us = 350.0,
.writeback_latency_us = 12.0, .writeback_latency_us = 12.0,
.dram_channel_width_bytes = 4, .dram_channel_width_bytes = 4,
.round_trip_ping_latency_dcfclk_cycles = 106, .round_trip_ping_latency_dcfclk_cycles = 106,