i2c: i2c-msm-geni: Enable multi descriptor support for shared SE
So far we bypassed multi-descriptor changes for shared-se, now enabled multi-descriptor changes for shared SE as well. Multi-descriptor uses block event interrupt(bei) to receive interrupt after transferring i2c messages specified by max number of transfers. HW will transfer data corresponding to all tre's and generate interrupt at the end of last transfer. In this implementation the number of interrupts are reduced and also ensured that while hardware is processing one set of tre's,software queues the next set of tre's if available. Change-Id: I983272681a7cbd99d4dab3d89e4f2b9edc8b3af7 Signed-off-by: Krishna Chaithanya Reddy G <quic_kgangapu@quicinc.com> Signed-off-by: Prasanna S <quic_prass@quicinc.com>
This commit is contained in:
Krishna Chaithanya Reddy G
Prasanna S
parent
659462265d
commit
da0999a52a
@ -631,6 +631,8 @@ struct gpii {
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bool unlock_tre_set;
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bool dual_ee_sync_flag;
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bool is_resumed;
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bool is_multi_desc;
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int num_msgs;
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};
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struct gpi_desc {
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@ -997,6 +999,25 @@ void gpi_dump_for_geni(struct dma_chan *chan)
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}
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EXPORT_SYMBOL(gpi_dump_for_geni);
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/**
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* gpi_update_multi_desc_flag() - update multi descriptor flag and num of msgs for
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* multi descriptor mode handling.
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* @chan: Base address of dma channel
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* @is_multi_descriptor: Is multi descriptor flag
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* @num_msgs: Number of client messages
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*
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* Return:None
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*/
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void gpi_update_multi_desc_flag(struct dma_chan *chan, bool is_multi_descriptor, int num_msgs)
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{
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struct gpii_chan *gpii_chan = to_gpii_chan(chan);
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struct gpii *gpii = gpii_chan->gpii;
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gpii->is_multi_desc = is_multi_descriptor;
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gpii->num_msgs = num_msgs;
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}
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EXPORT_SYMBOL_GPL(gpi_update_multi_desc_flag);
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static void gpi_disable_interrupts(struct gpii *gpii)
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{
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struct {
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@ -2191,6 +2212,8 @@ static void gpi_process_imed_data_event(struct gpii_chan *gpii_chan,
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gpi_desc = to_gpi_desc(vd);
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spin_unlock_irqrestore(&gpii_chan->vc.lock, flags);
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if (gpii->is_multi_desc)
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gpii->num_msgs--;
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/*
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* RP pointed by Event is to last TRE processed,
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@ -2213,22 +2236,32 @@ static void gpi_process_imed_data_event(struct gpii_chan *gpii_chan,
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*/
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chid = imed_event->chid;
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if (gpii->unlock_tre_set) {
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if (chid == GPI_RX_CHAN) {
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if (imed_event->code == MSM_GPI_TCE_EOT)
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goto gpi_free_desc;
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else if (imed_event->code == MSM_GPI_TCE_UNEXP_ERR)
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/*
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* In case of an error in a read transfer on a
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* shared se, unlock tre will not be processed
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* as channels go to bad state so tx desc should
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* be freed manually.
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*/
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gpi_free_chan_desc(gpii_tx_chan);
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else
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if (!gpii->is_multi_desc) {
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if (chid == GPI_RX_CHAN) {
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if (imed_event->code == MSM_GPI_TCE_EOT)
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goto gpi_free_desc;
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else if (imed_event->code == MSM_GPI_TCE_UNEXP_ERR)
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/*
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* In case of an error in a read transfer on a
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* shared se, unlock tre will not be processed
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* as channels go to bad state so tx desc should
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* be freed manually.
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*/
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gpi_free_chan_desc(gpii_tx_chan);
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else
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return;
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} else if (imed_event->code == MSM_GPI_TCE_EOT) {
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return;
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}
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} else {
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/*
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* Multi descriptor case waiting for unlock
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* tre eob, so not freeeing last descriptor
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*/
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if (gpii->num_msgs == 0)
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return;
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} else if (imed_event->code == MSM_GPI_TCE_EOT) {
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return;
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}
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} else if (imed_event->code == MSM_GPI_TCE_EOB) {
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goto gpi_free_desc;
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}
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@ -2297,6 +2330,8 @@ static void gpi_process_xfer_compl_event(struct gpii_chan *gpii_chan,
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gpi_desc = to_gpi_desc(vd);
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spin_unlock_irqrestore(&gpii_chan->vc.lock, flags);
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if (gpii->is_multi_desc)
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gpii->num_msgs--;
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/*
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* RP pointed by Event is to last TRE processed,
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@ -2319,28 +2354,37 @@ static void gpi_process_xfer_compl_event(struct gpii_chan *gpii_chan,
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*/
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chid = compl_event->chid;
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if (gpii->unlock_tre_set) {
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if (chid == GPI_RX_CHAN) {
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if (compl_event->code == MSM_GPI_TCE_EOT)
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goto gpi_free_desc;
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else if (compl_event->code == MSM_GPI_TCE_UNEXP_ERR)
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/*
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* In case of an error in a read transfer on a
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* shared se, unlock tre will not be processed
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* as channels go to bad state so tx desc should
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* be freed manually.
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*/
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gpi_free_chan_desc(gpii_tx_chan);
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else
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if (!gpii->is_multi_desc) {
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if (chid == GPI_RX_CHAN) {
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if (compl_event->code == MSM_GPI_TCE_EOT)
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goto gpi_free_desc;
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else if (compl_event->code == MSM_GPI_TCE_UNEXP_ERR)
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/*
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* In case of an error in a read transfer on a
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* shared se, unlock tre will not be processed
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* as channels go to bad state so tx desc should
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* be freed manually.
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*/
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gpi_free_chan_desc(gpii_tx_chan);
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else
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return;
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} else if (compl_event->code == MSM_GPI_TCE_EOT) {
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return;
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}
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} else {
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/*
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* Multi descriptor case waiting for unlock
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* tre eob, so not freeeing last descriptor
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*/
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if (gpii->num_msgs == 0)
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return;
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} else if (compl_event->code == MSM_GPI_TCE_EOT) {
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return;
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}
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} else if (compl_event->code == MSM_GPI_TCE_EOB) {
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if (!(gpii_chan->num_tre == 1 && gpii_chan->lock_tre_set)
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&& (gpii->protocol != SE_PROTOCOL_UART))
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goto gpi_free_desc;
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}
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tx_cb_param = vd->tx.callback_param;
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if (vd->tx.callback && tx_cb_param) {
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GPII_VERB(gpii, gpii_chan->chid,
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@ -24,6 +24,7 @@
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#include <linux/msm_gpi.h>
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#include <linux/ioctl.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/sched/clock.h>
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#include <linux/slab.h>
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#define SE_GENI_TEST_BUS_CTRL 0x44
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@ -118,6 +119,8 @@ if (dev) \
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#define NUM_TRE_MSGS_PER_INTR 64
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#define IMMEDIATE_DMA_LEN 8
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#define MIN_NUM_MSGS_FOR_MULTI_DESC_MODE 4
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/* FTRACE Logging */
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void i2c_trace_log(struct device *dev, const char *fmt, ...)
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{
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@ -1207,14 +1210,19 @@ static int geni_i2c_gsi_request_channel(struct geni_i2c_dev *gi2c)
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static struct msm_gpi_tre *setup_lock_tre(struct geni_i2c_dev *gi2c)
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{
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struct msm_gpi_tre *lock_t = &gi2c->lock_t;
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bool gsi_bei = false;
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/* lock: chain bit set */
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lock_t->dword[0] = MSM_GPI_LOCK_TRE_DWORD0;
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lock_t->dword[1] = MSM_GPI_LOCK_TRE_DWORD1;
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lock_t->dword[2] = MSM_GPI_LOCK_TRE_DWORD2;
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if (gi2c->gsi_tx.is_multi_descriptor)
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gsi_bei = true;
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/* ieob for le-vm and chain for shared se */
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if (gi2c->is_shared)
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lock_t->dword[3] = MSM_GPI_LOCK_TRE_DWORD3(0, 0, 0, 0, 1);
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lock_t->dword[3] = MSM_GPI_LOCK_TRE_DWORD3(0, gsi_bei, 0, 0, 1);
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else if (gi2c->is_le_vm)
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lock_t->dword[3] = MSM_GPI_LOCK_TRE_DWORD3(0, 0, 0, 1, 0);
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@ -1321,9 +1329,22 @@ static struct msm_gpi_tre *setup_tx_tre(struct geni_i2c_dev *gi2c,
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else
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*gsi_bei = false;
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/* BEI bit to be cleared for last TRE. */
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if (i == (num - 1))
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*gsi_bei = false;
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/*
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* Keep BEI = 0, for all last TREs
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* Shared SE : Last is unlock TRE, hence continue to have BEI = TRUE for DMA TX TRE.
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* BEI = 0, taken cared by setup_unlock_tre().
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* Rest all/non shared/Multi descriptor TREs : BEI = 0 for last transfer TRE.
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*/
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if (i == (num - 1)) {
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/* For Tx: for shared usecase unlock tre is send
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* for last transfer so set bei bit for last transfer
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* DMA tre
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*/
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if (gi2c->is_shared)
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*gsi_bei = true;
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else
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*gsi_bei = false;
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}
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}
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if (is_immediate_dma) {
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@ -1338,7 +1359,7 @@ static struct msm_gpi_tre *setup_tx_tre(struct geni_i2c_dev *gi2c,
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* For Tx: unlock tre is send for last transfer
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* so set chain bit for last transfer DMA tre.
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*/
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tx_t->dword[3] = MSM_GPI_DMA_IMMEDIATE_TRE_DWORD3(0, 0, 1, 0, 1);
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tx_t->dword[3] = MSM_GPI_DMA_IMMEDIATE_TRE_DWORD3(0, *gsi_bei, 1, 0, 1);
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else
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tx_t->dword[3] = MSM_GPI_DMA_IMMEDIATE_TRE_DWORD3(0, *gsi_bei, 1, 0, 0);
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} else {
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@ -1351,7 +1372,7 @@ static struct msm_gpi_tre *setup_tx_tre(struct geni_i2c_dev *gi2c,
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* For Tx: unlock tre is send for last transfer
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* so set chain bit for last transfer DMA tre.
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*/
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tx_t->dword[3] = MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(0, 0, 1, 0, 1);
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tx_t->dword[3] = MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(0, *gsi_bei, 1, 0, 1);
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else
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tx_t->dword[3] = MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(0, *gsi_bei, 1, 0, 0);
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}
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@ -1531,6 +1552,34 @@ static void geni_i2c_unlock_bus(struct geni_i2c_dev *gi2c)
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gi2c->i2c_kpi, start_time, 0, 0);
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}
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/**
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* geni_i2c_check_for_gsi_multi_desc_mode() - check for i2c multi descriptor mode.
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* @gi2c: Geni I2C device handle
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* @msgs: Base address of i2c msgs
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* @num: Number of messages
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*
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* This function check for multi desc mode.
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*
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* Return: None
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*/
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static void geni_i2c_check_for_gsi_multi_desc_mode(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[],
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int num)
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{
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u32 i = 0;
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if (num >= MIN_NUM_MSGS_FOR_MULTI_DESC_MODE) {
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gi2c->gsi_tx.is_multi_descriptor = true;
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/* assumes multi descriptor supports only for continuous writes */
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for (i = 0; i < num; i++)
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if (msgs[i].flags & I2C_M_RD)
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gi2c->gsi_tx.is_multi_descriptor = false;
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} else {
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gi2c->gsi_tx.is_multi_descriptor = false;
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}
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#if IS_ENABLED(CONFIG_MSM_GPI_DMA)
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gpi_update_multi_desc_flag(gi2c->tx_c, gi2c->gsi_tx.is_multi_descriptor, num);
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#endif
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}
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/**
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* geni_i2c_gsi_read() - Perform gsi i2c read
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* @gi2c: Geni I2C device handle
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@ -1701,6 +1750,9 @@ static int geni_i2c_gsi_write(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[],
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/* Send unlock tre at the end of last transfer */
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sg_set_buf(&gi2c->tx_sg[index++],
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unlock_t, sizeof(gi2c->unlock_t));
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/* to enable call back for unlock tre */
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if (gi2c->gsi_tx.is_multi_descriptor)
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gsi_bei = false;
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}
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gi2c->tx_desc = geni_i2c_prep_desc(gi2c, gi2c->tx_c, segs, true);
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@ -1765,7 +1817,7 @@ static int geni_i2c_gsi_tx_tre_optimization(struct geni_i2c_dev *gi2c, u32 num,
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* if it's last message, waiting for all pending tre's
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* including last submitted tre as well.
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*/
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if (gi2c->gsi_tx.is_multi_descriptor && !gi2c->is_shared) {
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if (gi2c->gsi_tx.is_multi_descriptor) {
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for (i = 0; i < max_irq_cnt; i++) {
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if (max_irq_cnt != atomic_read(&gi2c->gsi_tx.irq_cnt)) {
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I2C_LOG_DBG(gi2c->ipcl, false, gi2c->dev,
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@ -1801,7 +1853,7 @@ static int geni_i2c_gsi_tx_tre_optimization(struct geni_i2c_dev *gi2c, u32 num,
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/* process received tre's */
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if (timeout) {
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if (gi2c->gsi_tx.is_multi_descriptor && !gi2c->is_shared)
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if (gi2c->gsi_tx.is_multi_descriptor)
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gi2c_gsi_tre_process(gi2c, num);
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}
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@ -1877,16 +1929,7 @@ static int geni_i2c_gsi_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
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unlock_t = setup_unlock_tre(gi2c);
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}
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gi2c->gsi_tx.is_multi_descriptor = false;
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/* if num of msgs more than 4 checking for multi descriptor mode */
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if (num >= 4) {
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gi2c->gsi_tx.is_multi_descriptor = true;
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/* assumes multi descriptor supports only for continuous writes */
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for (i = 0; i < num; i++)
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if (msgs[i].flags & I2C_M_RD)
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gi2c->gsi_tx.is_multi_descriptor = false;
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}
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geni_i2c_check_for_gsi_multi_desc_mode(gi2c, msgs, num);
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if (!gi2c->cfg_sent)
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cfg0_t = setup_cfg0_tre(gi2c);
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@ -1975,8 +2018,7 @@ static int geni_i2c_gsi_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
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* continuously without waiting, in b/w if any one of the
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* tre is received processing and queuing next tre.
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*/
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if (gi2c->gsi_tx.is_multi_descriptor && !gi2c->is_shared &&
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(i != (num - 1)) &&
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if (gi2c->gsi_tx.is_multi_descriptor && (i != (num - 1)) &&
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(gi2c->gsi_tx.msg_cnt < MAX_NUM_TRE_MSGS + gi2c->gsi_tx.tre_freed_cnt))
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continue;
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@ -2037,7 +2079,7 @@ static int geni_i2c_gsi_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
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i2c_put_dma_safe_msg_buf(rd_dma_buf, &msgs[i], !gi2c->err);
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} else if (gi2c->err) {
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/* for multi descriptor unmap all submitted tre's */
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if (gi2c->gsi_tx.is_multi_descriptor && !gi2c->is_shared)
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if (gi2c->gsi_tx.is_multi_descriptor)
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gi2c_gsi_tre_process(gi2c, num);
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else
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gi2c_gsi_tx_unmap(gi2c, i, wr_idx - 1);
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@ -2049,6 +2091,11 @@ static int geni_i2c_gsi_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
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}
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geni_i2c_gsi_xfer_out:
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/* clearing the gpi multi descriptor flag */
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#if IS_ENABLED(CONFIG_MSM_GPI_DMA)
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if (gi2c->gsi_tx.is_multi_descriptor)
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gpi_update_multi_desc_flag(gi2c->tx_c, false, 0);
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#endif
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if (!ret && gi2c->err)
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ret = gi2c->err;
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I2C_LOG_DBG(gi2c->ipcl, false, gi2c->dev,
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@ -393,6 +393,17 @@ struct gsi_common {
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*/
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void gpi_dump_for_geni(struct dma_chan *chan);
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/**
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* gpi_update_multi_desc_flag() - update multi descriptor flag and num of msgs for
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* multi descriptor mode handling.
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* @chan: Base address of dma channel
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* @is_multi_descriptor: is multi descriptor flag
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* @num_msgs: number of client messages
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*
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* Return:None
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*/
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void gpi_update_multi_desc_flag(struct dma_chan *chan, bool is_multi_descriptor, int num_msgs);
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/**
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* gsi_common_tre_process() - Process received TRE's from GSI HW
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* @gsi: Base address of the gsi common structure.
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