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i3c-master-msm-geni: Fix Free running clock issue due to HW BUG

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During i3c enumeration while sending ccc commands we are seeing
intermediate clock frequency is running continuosuly b/w commands
and data, this can mislead to the slave. To solve this added
SWA changes like doing force default before enabling the ibi
controller. This SWA fixed in the HW from core version >=4.
Added required changes as per qup core version.

Change-Id: I70d4faeea22b782fee652c84c80bd9d873ff4965
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
This commit is contained in:
Anil Veshala Veshala 2023-10-19 23:49:00 -07:00
parent 97d1857b1b
commit d7f3019232
1 changed files with 13 additions and 3 deletions
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16
drivers/i3c/master/i3c-master-msm-geni.c
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@ -2718,9 +2718,16 @@ static void geni_i3c_enable_ibi_irq(struct geni_i3c_dev *gi3c, bool enable)
*/
static void geni_i3c_disable_free_running_clock(struct geni_i3c_dev *gi3c)
{
I3C_LOG_DBG(gi3c->ipcl, false, gi3c->se.dev, "Force default\n");
writel(FORCE_DEFAULT, gi3c->se.base + GENI_FORCE_DEFAULT_REG);
writel_relaxed(0x7f, gi3c->se.base + GENI_OUTPUT_CTRL);
/*
* Currently implemented as SWA.
* Fix is present from qup-core version 4.0.0 onwards[major = 4, minor = 0].
* So below SWA is not applicable from qup-core version 4.0.0 onwards.
*/
if (gi3c->ver_info.hw_major_ver < 4) {
I3C_LOG_DBG(gi3c->ipcl, false, gi3c->se.dev, "Force default\n");
writel(FORCE_DEFAULT, gi3c->se.base + GENI_FORCE_DEFAULT_REG);
writel(0x7f, gi3c->se.base + GENI_OUTPUT_CTRL);
}
gi3c->disable_free_run_clks = true;
}
@ -3235,6 +3242,9 @@ static void geni_i3c_get_ver_info(struct geni_i3c_dev *gi3c)
"%s hw_ver: 0x%x Major:%d Minor:%d step:%d\n",
__func__, hw_ver, major, minor, step);
gi3c->ver_info.hw_major_ver = major;
gi3c->ver_info.hw_minor_ver = minor;
gi3c->ver_info.hw_step_ver = step;
gi3c->ver_info.m_fw_ver = geni_se_common_get_m_fw(gi3c->se.base);
gi3c->ver_info.s_fw_ver = geni_se_common_get_s_fw(gi3c->se.base);
I3C_LOG_DBG(gi3c->ipcl, false, gi3c->se.dev, "%s:FW Ver:0x%x%x\n",