drm/amd/display: update dcn315 lpddr pstate latency
[ Upstream commit c92da0403d373c03ea5c65c0260c7db6762013b0 ] [WHY/HOW] Increase the pstate latency to improve ac/dc transition Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -324,7 +324,7 @@ static struct wm_table lpddr5_wm_table = {
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{
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.wm_inst = WM_A,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.pstate_latency_us = 129.0,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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@ -332,7 +332,7 @@ static struct wm_table lpddr5_wm_table = {
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{
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.pstate_latency_us = 129.0,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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@ -340,7 +340,7 @@ static struct wm_table lpddr5_wm_table = {
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{
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.pstate_latency_us = 129.0,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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@ -348,7 +348,7 @@ static struct wm_table lpddr5_wm_table = {
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{
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.65333,
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.pstate_latency_us = 129.0,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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