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arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table

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[ Upstream commit 08f399a818b0eff552b1f23c3171950a58aea78f ]

This is not a fix on its own but more a cleanup. Phy qmp pcie driver
currently have a workaround to handle pcs_misc not declared and add
0x400 offset to the pcs reg if pcs_misc is not declared.

Correctly declare pcs_misc reg and reduce PCS size to the common value
of 0x1f0 as done for every other qmp based pcie phy device.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@gmail.com
Stable-dep-of: 5c0dbe8b0584 ("arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Christian Marangi 2022-11-03 22:21:25 +01:00 committed by Greg Kroah-Hartman
parent 45d8d80cda
commit cb65c2caa1
1 changed files with 2 additions and 1 deletions
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arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@ -406,7 +406,8 @@ pcie_phy: phy@84000 {
pcie_phy0: phy@84200 {
reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
<0x0 0x84400 0x0 0x200>, /* Serdes Rx */
<0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
<0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
<0x0 0x84c00 0x0 0xf4>; /* pcs_misc */
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;