crypto: ccree - add CPP completion handling
Add the logic needed to track and report CPP operation rejection. The new logic will be used by the CPP feature introduced later. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Gilad Ben-Yossef
Herbert Xu
parent
f98f6e2134
commit
cadfd8987a
@ -55,6 +55,14 @@
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#define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX
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#define CC_CPP_NUM_SLOTS 8
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#define CC_CPP_NUM_ALGS 2
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enum cc_cpp_alg {
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CC_CPP_SM4 = 1,
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CC_CPP_AES = 0
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};
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enum drv_engine_type {
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DRV_ENGINE_NULL = 0,
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DRV_ENGINE_AES = 1,
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@ -118,12 +118,12 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
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drvdata->irq = irr;
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/* Completion interrupt - most probable */
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if (irr & CC_COMP_IRQ_MASK) {
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/* Mask AXI completion interrupt - will be unmasked in
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* Deferred service handler
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if (irr & drvdata->comp_mask) {
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/* Mask all completion interrupts - will be unmasked in
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* deferred service handler
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*/
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cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_COMP_IRQ_MASK);
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irr &= ~CC_COMP_IRQ_MASK;
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cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask);
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irr &= ~drvdata->comp_mask;
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complete_request(drvdata);
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}
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#ifdef CONFIG_CRYPTO_FIPS
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@ -175,7 +175,7 @@ int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe)
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cc_iowrite(drvdata, CC_REG(HOST_ICR), val);
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/* Unmask relevant interrupt cause */
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val = CC_COMP_IRQ_MASK | CC_AXI_ERR_IRQ_MASK;
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val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK;
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if (drvdata->hw_rev >= CC_HW_REV_712)
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val |= CC_GPR0_IRQ_MASK;
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@ -235,6 +235,8 @@ static int init_cc_resources(struct platform_device *plat_dev)
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new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
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}
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new_drvdata->comp_mask = CC_COMP_IRQ_MASK;
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platform_set_drvdata(plat_dev, new_drvdata);
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new_drvdata->plat_dev = plat_dev;
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@ -315,6 +317,8 @@ static int init_cc_resources(struct platform_device *plat_dev)
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return rc;
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}
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new_drvdata->sec_disabled = cc_sec_disable;
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if (hw_rev->rev <= CC_HW_REV_712) {
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/* Verify correct mapping */
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val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
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@ -328,10 +332,15 @@ static int init_cc_resources(struct platform_device *plat_dev)
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} else {
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val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
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val &= CC_SECURITY_DISABLED_MASK;
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new_drvdata->sec_disabled = !!val;
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new_drvdata->sec_disabled |= !!val;
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if (!new_drvdata->sec_disabled) {
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new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK;
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if (new_drvdata->std_bodies & CC_STD_NIST)
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new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK;
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}
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}
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new_drvdata->sec_disabled |= cc_sec_disable;
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if (new_drvdata->sec_disabled)
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dev_info(dev, "Security Disabled mode is in effect. Security functions disabled.\n");
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@ -71,6 +71,26 @@ enum cc_std_body {
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CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
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CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
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#define CC_CPP_AES_ABORT_MASK ( \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT))
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#define CC_CPP_SM4_ABORT_MASK ( \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \
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BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT))
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/* Register name mangling macro */
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#define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
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@ -92,6 +112,12 @@ enum cc_std_body {
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* field in the HW descriptor. The DMA engine +8 that value.
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*/
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struct cc_cpp_req {
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bool is_cpp;
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enum cc_cpp_alg alg;
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u8 slot;
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};
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#define CC_MAX_IVGEN_DMA_ADDRESSES 3
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struct cc_crypto_req {
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void (*user_cb)(struct device *dev, void *req, int err);
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@ -106,6 +132,7 @@ struct cc_crypto_req {
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/* The generated IV size required, 8/16 B allowed. */
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unsigned int ivgen_size;
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struct completion seq_compl; /* request completion */
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struct cc_cpp_req cpp;
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};
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/**
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@ -139,6 +166,7 @@ struct cc_drvdata {
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u32 ver_offset;
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int std_bodies;
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bool sec_disabled;
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u32 comp_mask;
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};
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struct cc_crypto_alg {
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@ -7,33 +7,102 @@
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// --------------------------------------
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// BLOCK: HOST_P
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// --------------------------------------
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/* IRR */
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#define CC_HOST_IRR_REG_OFFSET 0xA00UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL
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#define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT 0x3UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT 0x4UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT 0x5UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT 0x6UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT 0x7UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL
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#define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT 0x9UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT 0xAUL
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#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_GPR0_BIT_SHIFT 0xBUL
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#define CC_HOST_IRR_GPR0_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT 0xCUL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT 0xDUL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT 0xEUL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT 0xFUL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT 0x10UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT 0x11UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT 0x12UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL
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#define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT 0x14UL
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#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SIZE 0x1UL
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#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL
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#define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL
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#define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET 0xA10UL
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#define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT 0x0UL
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#define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE 0xCUL
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#define CC_HOST_IMR_REG_OFFSET 0xA04UL
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#define CC_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL
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#define CC_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL
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/* IMR */
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#define CC_HOST_IMR_REG_OFFSET 0x0A04UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL
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#define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT 0x3UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT 0x4UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT 0x5UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT 0x6UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT 0x7UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL
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#define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT 0x9UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT 0xAUL
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#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_GPR0_BIT_SHIFT 0xBUL
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#define CC_HOST_IMR_GPR0_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT 0xCUL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT 0xDUL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT 0xEUL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT 0xFUL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT 0x10UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT 0x11UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT 0x12UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL
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#define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT 0x14UL
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#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SIZE 0x1UL
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#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL
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#define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL
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/* ICR */
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#define CC_HOST_ICR_REG_OFFSET 0xA08UL
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#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL
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#define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL
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@ -2,6 +2,7 @@
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/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
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#include <linux/kernel.h>
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#include <linux/nospec.h>
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#include "cc_driver.h"
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#include "cc_buffer_mgr.h"
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#include "cc_request_mgr.h"
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@ -52,11 +53,38 @@ struct cc_bl_item {
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bool notif;
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};
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static const u32 cc_cpp_int_masks[CC_CPP_NUM_ALGS][CC_CPP_NUM_SLOTS] = {
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{ BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT) },
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{ BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT),
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BIT(CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT) }
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};
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static void comp_handler(unsigned long devarg);
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#ifdef COMP_IN_WQ
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static void comp_work_handler(struct work_struct *work);
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#endif
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static inline u32 cc_cpp_int_mask(enum cc_cpp_alg alg, int slot)
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{
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alg = array_index_nospec(alg, CC_CPP_NUM_ALGS);
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slot = array_index_nospec(slot, CC_CPP_NUM_SLOTS);
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return cc_cpp_int_masks[alg][slot];
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}
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void cc_req_mgr_fini(struct cc_drvdata *drvdata)
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{
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struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
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@ -579,6 +607,8 @@ static void proc_completions(struct cc_drvdata *drvdata)
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drvdata->request_mgr_handle;
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unsigned int *tail = &request_mgr_handle->req_queue_tail;
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unsigned int *head = &request_mgr_handle->req_queue_head;
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int rc;
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u32 mask;
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while (request_mgr_handle->axi_completed) {
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request_mgr_handle->axi_completed--;
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@ -596,8 +626,22 @@ static void proc_completions(struct cc_drvdata *drvdata)
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cc_req = &request_mgr_handle->req_queue[*tail];
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if (cc_req->cpp.is_cpp) {
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dev_dbg(dev, "CPP request completion slot: %d alg:%d\n",
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cc_req->cpp.slot, cc_req->cpp.alg);
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mask = cc_cpp_int_mask(cc_req->cpp.alg,
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cc_req->cpp.slot);
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rc = (drvdata->irq & mask ? -EPERM : 0);
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dev_dbg(dev, "Got mask: %x irq: %x rc: %d\n", mask,
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drvdata->irq, rc);
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} else {
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dev_dbg(dev, "None CPP request completion\n");
|
||||
rc = 0;
|
||||
}
|
||||
|
||||
if (cc_req->user_cb)
|
||||
cc_req->user_cb(dev, cc_req->user_arg, 0);
|
||||
cc_req->user_cb(dev, cc_req->user_arg, rc);
|
||||
*tail = (*tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1);
|
||||
dev_dbg(dev, "Dequeue request tail=%u\n", *tail);
|
||||
dev_dbg(dev, "Request completed. axi_completed=%d\n",
|
||||
@ -618,47 +662,50 @@ static void comp_handler(unsigned long devarg)
|
||||
struct cc_drvdata *drvdata = (struct cc_drvdata *)devarg;
|
||||
struct cc_req_mgr_handle *request_mgr_handle =
|
||||
drvdata->request_mgr_handle;
|
||||
|
||||
struct device *dev = drvdata_to_dev(drvdata);
|
||||
u32 irq;
|
||||
|
||||
irq = (drvdata->irq & CC_COMP_IRQ_MASK);
|
||||
dev_dbg(dev, "Completion handler called!\n");
|
||||
irq = (drvdata->irq & drvdata->comp_mask);
|
||||
|
||||
if (irq & CC_COMP_IRQ_MASK) {
|
||||
/* To avoid the interrupt from firing as we unmask it,
|
||||
* we clear it now
|
||||
*/
|
||||
cc_iowrite(drvdata, CC_REG(HOST_ICR), CC_COMP_IRQ_MASK);
|
||||
/* To avoid the interrupt from firing as we unmask it,
|
||||
* we clear it now
|
||||
*/
|
||||
cc_iowrite(drvdata, CC_REG(HOST_ICR), irq);
|
||||
|
||||
/* Avoid race with above clear: Test completion counter
|
||||
* once more
|
||||
*/
|
||||
request_mgr_handle->axi_completed +=
|
||||
cc_axi_comp_count(drvdata);
|
||||
/* Avoid race with above clear: Test completion counter once more */
|
||||
|
||||
while (request_mgr_handle->axi_completed) {
|
||||
do {
|
||||
proc_completions(drvdata);
|
||||
/* At this point (after proc_completions()),
|
||||
* request_mgr_handle->axi_completed is 0.
|
||||
*/
|
||||
request_mgr_handle->axi_completed =
|
||||
cc_axi_comp_count(drvdata);
|
||||
} while (request_mgr_handle->axi_completed > 0);
|
||||
request_mgr_handle->axi_completed += cc_axi_comp_count(drvdata);
|
||||
|
||||
cc_iowrite(drvdata, CC_REG(HOST_ICR),
|
||||
CC_COMP_IRQ_MASK);
|
||||
dev_dbg(dev, "AXI completion after updated: %d\n",
|
||||
request_mgr_handle->axi_completed);
|
||||
|
||||
while (request_mgr_handle->axi_completed) {
|
||||
do {
|
||||
drvdata->irq |= cc_ioread(drvdata, CC_REG(HOST_IRR));
|
||||
irq = (drvdata->irq & drvdata->comp_mask);
|
||||
proc_completions(drvdata);
|
||||
|
||||
/* At this point (after proc_completions()),
|
||||
* request_mgr_handle->axi_completed is 0.
|
||||
*/
|
||||
request_mgr_handle->axi_completed +=
|
||||
cc_axi_comp_count(drvdata);
|
||||
}
|
||||
cc_axi_comp_count(drvdata);
|
||||
} while (request_mgr_handle->axi_completed > 0);
|
||||
|
||||
cc_iowrite(drvdata, CC_REG(HOST_ICR), irq);
|
||||
|
||||
request_mgr_handle->axi_completed += cc_axi_comp_count(drvdata);
|
||||
}
|
||||
|
||||
/* after verifing that there is nothing to do,
|
||||
* unmask AXI completion interrupt
|
||||
*/
|
||||
cc_iowrite(drvdata, CC_REG(HOST_IMR),
|
||||
cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~irq);
|
||||
cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~drvdata->comp_mask);
|
||||
|
||||
cc_proc_backlog(drvdata);
|
||||
dev_dbg(dev, "Comp. handler done.\n");
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user