From 386225020c1d4812240931eb6d9263dbd9f6f424 Mon Sep 17 00:00:00 2001 From: Prashant Beniwal Date: Tue, 11 Jun 2024 13:33:31 +0530 Subject: [PATCH] clk: qcom: gcc-mdm9607: Update EMAC clocks The emac_0_125m_clk_src is added as a parent clock, but not registered with the clock framework, hence add support for the same. While at it, fix the parent mapping of gcc_emac_0_sys_25m_clk clock on MDM9607. Change-Id: I7a2aad91bd20e67c029cfd930952c56eba57c216 Signed-off-by: Prashant Beniwal Signed-off-by: Prerna Singh --- drivers/clk/qcom/gcc-mdm9607.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-mdm9607.c b/drivers/clk/qcom/gcc-mdm9607.c index cd99a3f850e8..d2424e322f09 100644 --- a/drivers/clk/qcom/gcc-mdm9607.c +++ b/drivers/clk/qcom/gcc-mdm9607.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, Konrad Dybcio - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1713,7 +1713,7 @@ static struct clk_branch gcc_emac_0_sys_25m_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_emac_0_sys_25m_clk", - .parent_hws = (const struct clk_hw *[]){ &emac_0_125m_clk_src.clkr.hw }, + .parent_hws = (const struct clk_hw *[]){ &emac_0_sys_25m_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1946,6 +1946,7 @@ static struct clk_regmap *gcc_mdm9607_clocks[] = { [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr, + [EMAC_0_125M_CLK_SRC] = &emac_0_125m_clk_src.clkr, [EMAC_0_SYS_25M_CLK_SRC] = &emac_0_sys_25m_clk_src.clkr, [EMAC_0_TX_CLK_SRC] = &emac_0_tx_clk_src.clkr, [GCC_EMAC_0_125M_CLK] = &gcc_emac_0_125m_clk.clkr,