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Merge "clk: qcom: gcc-holi: Add qupv3 clocks modelling"

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qctecmdr 2023-09-06 11:22:06 -07:00 committed by Gerrit - the friendly Code Review server
commit c577022ca5
1 changed files with 51 additions and 0 deletions
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51
drivers/clk/qcom/gcc-holi.c
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@ -3446,6 +3446,24 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x534d8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x53608,
.halt_check = BRANCH_HALT_VOTED,
@ -3494,6 +3512,36 @@ static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x53004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x53008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x38008,
.halt_check = BRANCH_HALT,
@ -4091,11 +4139,14 @@ static struct clk_regmap *gcc_holi_clocks[] = {
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,