From 5d7b6d2079894a7cb776e43fcbae70932153723e Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Fri, 17 Feb 2023 12:56:34 -0800 Subject: [PATCH 1/3] interconnect: qcom: icc-rpmh: Add CRM support Add support for voting BCMs through the CRM driver. Change-Id: I72d707b7d447e2326ddd9d029cf78937290b62a8 Signed-off-by: Mike Tipton --- drivers/interconnect/qcom/bcm-voter.c | 158 ++++++++++++++++++++++---- drivers/interconnect/qcom/icc-rpmh.h | 11 ++ 2 files changed, 149 insertions(+), 20 deletions(-) diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c index 40d482651201..87acf7c6744a 100644 --- a/drivers/interconnect/qcom/bcm-voter.c +++ b/drivers/interconnect/qcom/bcm-voter.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -36,6 +37,7 @@ static DEFINE_MUTEX(bcm_voter_lock); struct bcm_voter { struct device *dev; struct device_node *np; + struct qcom_icc_crm_voter *crm; struct mutex lock; struct list_head commit_list; struct list_head ws_list; @@ -285,19 +287,7 @@ static void qcom_icc_bcm_log(struct bcm_voter *voter, enum rpmh_state state, trace_bcm_voter_commit(rpmh_state[state], cmd); } -/** - * qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms - * @voter: voter that needs flushing - * - * This function generates a set of AMC commands and flushes to the BCM device - * associated with the voter. It conditionally generate WAKE and SLEEP commands - * based on deltas between WAKE/SLEEP requirements. The ws_list persists - * through multiple commit requests and bcm nodes are removed only when the - * requirements for WAKE matches SLEEP. - * - * Returns 0 on success, or an appropriate error code otherwise. - */ -int qcom_icc_bcm_voter_commit(struct bcm_voter *voter) +static int commit_rpmh(struct bcm_voter *voter) { struct qcom_icc_bcm *bcm; struct qcom_icc_bcm *bcm_tmp; @@ -305,13 +295,6 @@ int qcom_icc_bcm_voter_commit(struct bcm_voter *voter) struct tcs_cmd cmds[MAX_BCMS]; int ret = 0; - if (!voter) - return 0; - - mutex_lock(&voter->lock); - list_for_each_entry(bcm, &voter->commit_list, list) - bcm_aggregate(bcm, voter->init); - /* * Pre sort the BCMs based on VCD for ease of generating a command list * that groups the BCMs with the same VCD together. VCDs are numbered @@ -394,6 +377,111 @@ int qcom_icc_bcm_voter_commit(struct bcm_voter *voter) } out: + return ret; +} + +static int map_crm_pwr_state(enum crm_drv_type client_type, u32 bucket) +{ + if (client_type == CRM_HW_DRV) + return bucket; + + switch (bucket) { + case QCOM_ICC_BUCKET_AMC: return CRM_ACTIVE_STATE; + case QCOM_ICC_BUCKET_WAKE: return CRM_WAKE_STATE; + case QCOM_ICC_BUCKET_SLEEP: return CRM_SLEEP_STATE; + } + + return -EINVAL; +} + +static int crm_cmd_gen(struct crm_cmd *cmd, enum crm_drv_type client_type, + u32 bucket, u32 node, u64 vote_x, u64 vote_y) +{ + int pwr_state; + + if (!cmd) + return -EINVAL; + + memset(cmd, 0, sizeof(*cmd)); + + if (vote_x > BCM_TCS_CMD_VOTE_MASK) + vote_x = BCM_TCS_CMD_VOTE_MASK; + + if (vote_y > BCM_TCS_CMD_VOTE_MASK) + vote_y = BCM_TCS_CMD_VOTE_MASK; + + pwr_state = map_crm_pwr_state(client_type, bucket); + if (pwr_state < 0) + return pwr_state; + + cmd->pwr_state.hw = pwr_state; + cmd->resource_idx = node; + cmd->data = BCM_TCS_CMD(true, true, vote_x, vote_y); + cmd->wait = true; + + return 0; +} + +static int commit_crm(struct bcm_voter *voter) +{ + struct list_head *bcm_list = &voter->commit_list; + struct qcom_icc_crm_voter *crm = voter->crm; + struct qcom_icc_bcm *bcm; + struct crm_cmd crm_cmd; + int ret, i; + + list_for_each_entry(bcm, bcm_list, list) { + for (i = 0; i < crm->pwr_states; i++) { + ret = crm_cmd_gen(&crm_cmd, crm->client_type, i, bcm->crm_node, + bcm->vote_x[i], bcm->vote_y[i]); + if (ret) { + pr_err("Error generating crm_cmd: ret=%d\n", ret); + return ret; + } + + ret = crm_write_bw_vote(crm->dev, crm->client_type, + crm->client_idx, &crm_cmd); + if (ret) { + pr_err("Error writing crm bw: ret=%d\n", ret); + return ret; + } + } + } + + return 0; +} + +/** + * qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms + * @voter: voter that needs flushing + * + * This function generates a set of AMC commands and flushes to the BCM device + * associated with the voter. It conditionally generate WAKE and SLEEP commands + * based on deltas between WAKE/SLEEP requirements. The ws_list persists + * through multiple commit requests and bcm nodes are removed only when the + * requirements for WAKE matches SLEEP. + * + * Returns 0 on success, or an appropriate error code otherwise. + */ +int qcom_icc_bcm_voter_commit(struct bcm_voter *voter) +{ + struct qcom_icc_bcm *bcm; + struct qcom_icc_bcm *bcm_tmp; + int ret; + + if (!voter) + return 0; + + mutex_lock(&voter->lock); + + list_for_each_entry(bcm, &voter->commit_list, list) + bcm_aggregate(bcm, voter->init); + + if (voter->crm) + ret = commit_crm(voter); + else + ret = commit_rpmh(voter); + list_for_each_entry_safe(bcm, bcm_tmp, &voter->commit_list, list) list_del_init(&bcm->list); @@ -420,7 +508,10 @@ EXPORT_SYMBOL(qcom_icc_bcm_voter_clear_init); static int qcom_icc_bcm_voter_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + struct qcom_icc_crm_voter *crm; struct bcm_voter *voter; + const char *crm_name; + int ret; voter = devm_kzalloc(&pdev->dev, sizeof(*voter), GFP_KERNEL); if (!voter) @@ -437,6 +528,33 @@ static int qcom_icc_bcm_voter_probe(struct platform_device *pdev) INIT_LIST_HEAD(&voter->commit_list); INIT_LIST_HEAD(&voter->ws_list); + ret = of_property_read_string(np, "qcom,crm-name", &crm_name); + if (!ret) { + crm = devm_kzalloc(&pdev->dev, sizeof(*crm), GFP_KERNEL); + if (!crm) + return -ENOMEM; + + crm->dev = crm_get_device(crm_name); + if (IS_ERR(crm->dev)) + return PTR_ERR(crm->dev); + + crm->client_type = CRM_HW_DRV; + + ret = of_property_read_u32(np, "qcom,crm-client-idx", &crm->client_idx); + if (ret) { + dev_err(&pdev->dev, "Error getting crm-client-idx, ret=%d\n", ret); + return ret; + } + + ret = of_property_read_u32(np, "qcom,crm-pwr-states", &crm->pwr_states); + if (ret) { + dev_err(&pdev->dev, "Error getting crm-pwr-states, ret=%d\n", ret); + return ret; + } + + voter->crm = crm; + } + mutex_lock(&bcm_voter_lock); list_add_tail(&voter->voter_node, &bcm_voters); mutex_unlock(&bcm_voter_lock); diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index e60296177adb..0b1092e66586 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -10,6 +10,8 @@ #include #include +#include + #define to_qcom_provider(_provider) \ container_of(_provider, struct qcom_icc_provider, provider) @@ -55,6 +57,14 @@ struct bcm_db { #define MAX_BCM_PER_NODE 3 #define MAX_VCD 10 +struct qcom_icc_crm_voter { + const char *name; + const struct device *dev; + enum crm_drv_type client_type; + u32 client_idx; + u32 pwr_states; +}; + /** * struct qcom_icc_node - Qualcomm specific interconnect nodes * @name: the node name used in debugfs @@ -138,6 +148,7 @@ struct qcom_icc_bcm { struct list_head list; struct list_head ws_list; int voter_idx; + u8 crm_node; size_t num_nodes; struct qcom_icc_node *nodes[]; }; From 937c151efd1e140cfe2297e5b5e1c79e861af622 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Thu, 16 Feb 2023 04:59:34 -0800 Subject: [PATCH 2/3] dt-bindings: interconnect: Add PCIe CRM nodes for Pineapple Add PCIe CRM node bindings. Change-Id: I0546e3d8c3fb1b3d2b7120d7d31293f370648838 Signed-off-by: Mike Tipton --- .../dt-bindings/interconnect/qcom,pineapple.h | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/interconnect/qcom,pineapple.h b/include/dt-bindings/interconnect/qcom,pineapple.h index 3c8a13f2c965..5d438aa9d702 100644 --- a/include/dt-bindings/interconnect/qcom,pineapple.h +++ b/include/dt-bindings/interconnect/qcom,pineapple.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_PINEAPPLE_H @@ -175,5 +175,23 @@ #define SLAVE_LLCC_CAM_IFE_2 4513 #define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 4514 #define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 4515 +#define MASTER_IPA_CORE_PCIE_CRM_HW_0 5000 +#define MASTER_LLCC_PCIE_CRM_HW_0 5001 +#define MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 5002 +#define MASTER_PCIE_0_PCIE_CRM_HW_0 5003 +#define MASTER_PCIE_1_PCIE_CRM_HW_0 5004 +#define SLAVE_EBI1_PCIE_CRM_HW_0 5512 +#define SLAVE_IPA_CORE_PCIE_CRM_HW_0 5513 +#define SLAVE_LLCC_PCIE_CRM_HW_0 5514 +#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 5515 +#define MASTER_IPA_CORE_PCIE_CRM_HW_1 6000 +#define MASTER_LLCC_PCIE_CRM_HW_1 6001 +#define MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1 6002 +#define MASTER_PCIE_0_PCIE_CRM_HW_1 6003 +#define MASTER_PCIE_1_PCIE_CRM_HW_1 6004 +#define SLAVE_EBI1_PCIE_CRM_HW_1 6512 +#define SLAVE_IPA_CORE_PCIE_CRM_HW_1 6513 +#define SLAVE_LLCC_PCIE_CRM_HW_1 6514 +#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1 6515 #endif From 67fce3bd4b9a3874559dc8a149abb59feb27e519 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Thu, 16 Feb 2023 04:50:53 -0800 Subject: [PATCH 3/3] interconnect: qcom: pineapple: Add PCIe CRM nodes Add PCIe CRM nodes. Change-Id: I079270ae13080c85066f0e559c95a0ce3ac89e02 Signed-off-by: Mike Tipton --- drivers/interconnect/qcom/pineapple.c | 316 ++++++++++++++++++++++++++ 1 file changed, 316 insertions(+) diff --git a/drivers/interconnect/qcom/pineapple.c b/drivers/interconnect/qcom/pineapple.c index 3c4234d21706..240b8277eaf3 100644 --- a/drivers/interconnect/qcom/pineapple.c +++ b/drivers/interconnect/qcom/pineapple.c @@ -1257,6 +1257,106 @@ static struct qcom_icc_node qnm_camnoc_sf_cam_ife_2 = { .links = { SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 }, }; +static struct qcom_icc_node ipa_core_master_pcie_crm_hw_0 = { + .name = "ipa_core_master_pcie_crm_hw_0", + .id = MASTER_IPA_CORE_PCIE_CRM_HW_0, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_IPA_CORE_PCIE_CRM_HW_0 }, +}; + +static struct qcom_icc_node qnm_pcie_pcie_crm_hw_0 = { + .name = "qnm_pcie_pcie_crm_hw_0", + .id = MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_LLCC_PCIE_CRM_HW_0 }, +}; + +static struct qcom_icc_node llcc_mc_pcie_crm_hw_0 = { + .name = "llcc_mc_pcie_crm_hw_0", + .id = MASTER_LLCC_PCIE_CRM_HW_0, + .channels = 4, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_EBI1_PCIE_CRM_HW_0 }, +}; + +static struct qcom_icc_node xm_pcie3_0_pcie_crm_hw_0 = { + .name = "xm_pcie3_0_pcie_crm_hw_0", + .id = MASTER_PCIE_0_PCIE_CRM_HW_0, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 }, +}; + +static struct qcom_icc_node xm_pcie3_1_pcie_crm_hw_0 = { + .name = "xm_pcie3_1_pcie_crm_hw_0", + .id = MASTER_PCIE_1_PCIE_CRM_HW_0, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 }, +}; + +static struct qcom_icc_node ipa_core_master_pcie_crm_hw_1 = { + .name = "ipa_core_master_pcie_crm_hw_1", + .id = MASTER_IPA_CORE_PCIE_CRM_HW_1, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_IPA_CORE_PCIE_CRM_HW_1 }, +}; + +static struct qcom_icc_node qnm_pcie_pcie_crm_hw_1 = { + .name = "qnm_pcie_pcie_crm_hw_1", + .id = MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_LLCC_PCIE_CRM_HW_1 }, +}; + +static struct qcom_icc_node llcc_mc_pcie_crm_hw_1 = { + .name = "llcc_mc_pcie_crm_hw_1", + .id = MASTER_LLCC_PCIE_CRM_HW_1, + .channels = 4, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_EBI1_PCIE_CRM_HW_1 }, +}; + +static struct qcom_icc_node xm_pcie3_0_pcie_crm_hw_1 = { + .name = "xm_pcie3_0_pcie_crm_hw_1", + .id = MASTER_PCIE_0_PCIE_CRM_HW_1, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1 }, +}; + +static struct qcom_icc_node xm_pcie3_1_pcie_crm_hw_1 = { + .name = "xm_pcie3_1_pcie_crm_hw_1", + .id = MASTER_PCIE_1_PCIE_CRM_HW_1, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1 }, +}; + static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", .id = SLAVE_A1NOC_SNOC, @@ -2094,6 +2194,82 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = { .links = { MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 }, }; +static struct qcom_icc_node ipa_core_slave_pcie_crm_hw_0 = { + .name = "ipa_core_slave_pcie_crm_hw_0", + .id = SLAVE_IPA_CORE_PCIE_CRM_HW_0, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_llcc_pcie_crm_hw_0 = { + .name = "qns_llcc_pcie_crm_hw_0", + .id = SLAVE_LLCC_PCIE_CRM_HW_0, + .channels = 4, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_LLCC_PCIE_CRM_HW_0 }, +}; + +static struct qcom_icc_node ebi_pcie_crm_hw_0 = { + .name = "ebi_pcie_crm_hw_0", + .id = SLAVE_EBI1_PCIE_CRM_HW_0, + .channels = 4, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_pcie_mem_noc_pcie_crm_hw_0 = { + .name = "qns_pcie_mem_noc_pcie_crm_hw_0", + .id = SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0 }, +}; + +static struct qcom_icc_node ipa_core_slave_pcie_crm_hw_1 = { + .name = "ipa_core_slave_pcie_crm_hw_1", + .id = SLAVE_IPA_CORE_PCIE_CRM_HW_1, + .channels = 1, + .buswidth = 8, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_llcc_pcie_crm_hw_1 = { + .name = "qns_llcc_pcie_crm_hw_1", + .id = SLAVE_LLCC_PCIE_CRM_HW_1, + .channels = 4, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_LLCC_PCIE_CRM_HW_1 }, +}; + +static struct qcom_icc_node ebi_pcie_crm_hw_1 = { + .name = "ebi_pcie_crm_hw_1", + .id = SLAVE_EBI1_PCIE_CRM_HW_1, + .channels = 4, + .buswidth = 4, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 0, +}; + +static struct qcom_icc_node qns_pcie_mem_noc_pcie_crm_hw_1 = { + .name = "qns_pcie_mem_noc_pcie_crm_hw_1", + .id = SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1, + .channels = 1, + .buswidth = 16, + .noc_ops = &qcom_qnoc4_ops, + .num_links = 1, + .links = { MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1 }, +}; + static struct qcom_icc_bcm bcm_acv = { .name = "ACV", .voter_idx = 0, @@ -2448,6 +2624,108 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = { &qnm_pcie_cam_ife_2 }, }; +static struct qcom_icc_bcm bcm_acv_pcie_crm_hw_0 = { + .name = "ACV", + .voter_idx = 5, + .crm_node = 5, + .enable_mask = 0x1, + .num_nodes = 1, + .nodes = { &ebi_pcie_crm_hw_0 }, +}; + +static struct qcom_icc_bcm bcm_ip0_pcie_crm_hw_0 = { + .name = "IP0", + .voter_idx = 1, + .crm_node = 4, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &ipa_core_slave_pcie_crm_hw_0 }, +}; + +static struct qcom_icc_bcm bcm_mc0_pcie_crm_hw_0 = { + .name = "MC0", + .voter_idx = 5, + .crm_node = 0, + .num_nodes = 1, + .nodes = { &ebi_pcie_crm_hw_0 }, +}; + +static struct qcom_icc_bcm bcm_sh0_pcie_crm_hw_0 = { + .name = "SH0", + .voter_idx = 5, + .crm_node = 1, + .num_nodes = 1, + .nodes = { &qns_llcc_pcie_crm_hw_0 }, +}; + +static struct qcom_icc_bcm bcm_sh1_pcie_crm_hw_0 = { + .name = "SH1", + .voter_idx = 5, + .crm_node = 2, + .enable_mask = 0x1, + .num_nodes = 1, + .nodes = { &qnm_pcie_pcie_crm_hw_0 }, +}; + +static struct qcom_icc_bcm bcm_sn4_pcie_crm_hw_0 = { + .name = "SN4", + .voter_idx = 1, + .crm_node = 3, + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc_pcie_crm_hw_0 }, +}; + +static struct qcom_icc_bcm bcm_acv_pcie_crm_hw_1 = { + .name = "ACV", + .voter_idx = 6, + .crm_node = 5, + .enable_mask = 0x1, + .num_nodes = 1, + .nodes = { &ebi_pcie_crm_hw_1 }, +}; + +static struct qcom_icc_bcm bcm_ip0_pcie_crm_hw_1 = { + .name = "IP0", + .voter_idx = 1, + .crm_node = 4, + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &ipa_core_slave_pcie_crm_hw_1 }, +}; + +static struct qcom_icc_bcm bcm_mc0_pcie_crm_hw_1 = { + .name = "MC0", + .voter_idx = 6, + .crm_node = 0, + .num_nodes = 1, + .nodes = { &ebi_pcie_crm_hw_1 }, +}; + +static struct qcom_icc_bcm bcm_sh0_pcie_crm_hw_1 = { + .name = "SH0", + .voter_idx = 6, + .crm_node = 1, + .num_nodes = 1, + .nodes = { &qns_llcc_pcie_crm_hw_1 }, +}; + +static struct qcom_icc_bcm bcm_sh1_pcie_crm_hw_1 = { + .name = "SH1", + .voter_idx = 6, + .crm_node = 2, + .enable_mask = 0x1, + .num_nodes = 1, + .nodes = { &qnm_pcie_pcie_crm_hw_1 }, +}; + +static struct qcom_icc_bcm bcm_sn4_pcie_crm_hw_1 = { + .name = "SN4", + .voter_idx = 2, + .crm_node = 3, + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc_pcie_crm_hw_1 }, +}; + static struct qcom_icc_bcm *aggre1_noc_bcms[] = { }; @@ -2509,6 +2787,8 @@ static struct qcom_icc_bcm *clk_virt_bcms[] = { &bcm_qup0, &bcm_qup1, &bcm_qup2, + &bcm_ip0_pcie_crm_hw_0, + &bcm_ip0_pcie_crm_hw_1, }; static struct qcom_icc_node *clk_virt_nodes[] = { @@ -2518,10 +2798,16 @@ static struct qcom_icc_node *clk_virt_nodes[] = { [SLAVE_QUP_CORE_0] = &qup0_core_slave, [SLAVE_QUP_CORE_1] = &qup1_core_slave, [SLAVE_QUP_CORE_2] = &qup2_core_slave, + [MASTER_IPA_CORE_PCIE_CRM_HW_0] = &ipa_core_master_pcie_crm_hw_0, + [SLAVE_IPA_CORE_PCIE_CRM_HW_0] = &ipa_core_slave_pcie_crm_hw_0, + [MASTER_IPA_CORE_PCIE_CRM_HW_1] = &ipa_core_master_pcie_crm_hw_1, + [SLAVE_IPA_CORE_PCIE_CRM_HW_1] = &ipa_core_slave_pcie_crm_hw_1, }; static char *clk_virt_voters[] = { "hlos", + "pcie_crm_hw_0", + "pcie_crm_hw_1", }; static struct qcom_icc_desc pineapple_clk_virt = { @@ -2646,6 +2932,10 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh1_cam_ife_1, &bcm_sh0_cam_ife_2, &bcm_sh1_cam_ife_2, + &bcm_sh0_pcie_crm_hw_0, + &bcm_sh1_pcie_crm_hw_0, + &bcm_sh0_pcie_crm_hw_1, + &bcm_sh1_pcie_crm_hw_1, }; static struct qcom_icc_node *gem_noc_nodes[] = { @@ -2681,6 +2971,10 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_sf_cam_ife_2, [MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2] = &qnm_pcie_cam_ife_2, [SLAVE_LLCC_CAM_IFE_2] = &qns_llcc_cam_ife_2, + [MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0] = &qnm_pcie_pcie_crm_hw_0, + [SLAVE_LLCC_PCIE_CRM_HW_0] = &qns_llcc_pcie_crm_hw_0, + [MASTER_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1] = &qnm_pcie_pcie_crm_hw_1, + [SLAVE_LLCC_PCIE_CRM_HW_1] = &qns_llcc_pcie_crm_hw_1, }; static char *gem_noc_voters[] = { @@ -2689,6 +2983,8 @@ static char *gem_noc_voters[] = { "cam_ife_0", "cam_ife_1", "cam_ife_2", + "pcie_crm_hw_0", + "pcie_crm_hw_1", }; static struct qcom_icc_desc pineapple_gem_noc = { @@ -2779,6 +3075,10 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0_cam_ife_1, &bcm_acv_cam_ife_2, &bcm_mc0_cam_ife_2, + &bcm_acv_pcie_crm_hw_0, + &bcm_mc0_pcie_crm_hw_0, + &bcm_acv_pcie_crm_hw_1, + &bcm_mc0_pcie_crm_hw_1, }; static struct qcom_icc_node *mc_virt_nodes[] = { @@ -2792,6 +3092,10 @@ static struct qcom_icc_node *mc_virt_nodes[] = { [SLAVE_EBI1_CAM_IFE_1] = &ebi_cam_ife_1, [MASTER_LLCC_CAM_IFE_2] = &llcc_mc_cam_ife_2, [SLAVE_EBI1_CAM_IFE_2] = &ebi_cam_ife_2, + [MASTER_LLCC_PCIE_CRM_HW_0] = &llcc_mc_pcie_crm_hw_0, + [SLAVE_EBI1_PCIE_CRM_HW_0] = &ebi_pcie_crm_hw_0, + [MASTER_LLCC_PCIE_CRM_HW_1] = &llcc_mc_pcie_crm_hw_1, + [SLAVE_EBI1_PCIE_CRM_HW_1] = &ebi_pcie_crm_hw_1, }; static char *mc_virt_voters[] = { @@ -2800,6 +3104,8 @@ static char *mc_virt_voters[] = { "cam_ife_0", "cam_ife_1", "cam_ife_2", + "pcie_crm_hw_0", + "pcie_crm_hw_1", }; static struct qcom_icc_desc pineapple_mc_virt = { @@ -2900,6 +3206,8 @@ static struct qcom_icc_desc pineapple_nsp_noc = { static struct qcom_icc_bcm *pcie_anoc_bcms[] = { &bcm_sn4, + &bcm_sn4_pcie_crm_hw_0, + &bcm_sn4_pcie_crm_hw_1, }; static struct qcom_icc_node *pcie_anoc_nodes[] = { @@ -2908,10 +3216,18 @@ static struct qcom_icc_node *pcie_anoc_nodes[] = { [MASTER_PCIE_1] = &xm_pcie3_1, [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, + [MASTER_PCIE_0_PCIE_CRM_HW_0] = &xm_pcie3_0_pcie_crm_hw_0, + [MASTER_PCIE_1_PCIE_CRM_HW_0] = &xm_pcie3_1_pcie_crm_hw_0, + [SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_0] = &qns_pcie_mem_noc_pcie_crm_hw_0, + [MASTER_PCIE_0_PCIE_CRM_HW_1] = &xm_pcie3_0_pcie_crm_hw_1, + [MASTER_PCIE_1_PCIE_CRM_HW_1] = &xm_pcie3_1_pcie_crm_hw_1, + [SLAVE_ANOC_PCIE_GEM_NOC_PCIE_CRM_HW_1] = &qns_pcie_mem_noc_pcie_crm_hw_1, }; static char *pcie_anoc_voters[] = { "hlos", + "pcie_crm_hw_0", + "pcie_crm_hw_1", }; static struct qcom_icc_desc pineapple_pcie_anoc = {