drm/amd/display: fix some coding style issues
commit ae67558be712237109100fd14f12378adcf24356 upstream.
Fix the following checkpatch checks in amdgpu_dm.c
CHECK: Prefer kernel type 'u8' over 'uint8_t'
CHECK: Prefer kernel type 'u32' over 'uint32_t'
CHECK: Prefer kernel type 'u64' over 'uint64_t'
CHECK: Prefer kernel type 's32' over 'int32_t'
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[ PSR-SU support was introduced in kernel 6.2 with commits like
30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support")
but PSR-SU isn't enabled in 6.1.y, so this block needs to be skipped
when backporting. ]
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Srinivasan Shanmugam
Greg Kroah-Hartman
parent
374735cbe2
commit
c085ffaf67
@ -211,7 +211,7 @@ static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
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static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
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struct amdgpu_dm_connector *amdgpu_dm_connector,
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uint32_t link_index,
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u32 link_index,
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struct amdgpu_encoder *amdgpu_encoder);
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static int amdgpu_dm_encoder_init(struct drm_device *dev,
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struct amdgpu_encoder *aencoder,
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@ -263,7 +263,7 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
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static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
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u32 *vbl, u32 *position)
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{
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uint32_t v_blank_start, v_blank_end, h_position, v_position;
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u32 v_blank_start, v_blank_end, h_position, v_position;
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if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
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return -EINVAL;
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@ -391,7 +391,7 @@ static void dm_pflip_high_irq(void *interrupt_params)
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struct amdgpu_device *adev = irq_params->adev;
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unsigned long flags;
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struct drm_pending_vblank_event *e;
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uint32_t vpos, hpos, v_blank_start, v_blank_end;
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u32 vpos, hpos, v_blank_start, v_blank_end;
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bool vrr_active;
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amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
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@ -678,7 +678,7 @@ static void dmub_hpd_callback(struct amdgpu_device *adev,
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struct drm_connector *connector;
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struct drm_connector_list_iter iter;
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struct dc_link *link;
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uint8_t link_index = 0;
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u8 link_index = 0;
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struct drm_device *dev;
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if (adev == NULL)
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@ -779,7 +779,7 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
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struct amdgpu_device *adev = irq_params->adev;
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struct amdgpu_display_manager *dm = &adev->dm;
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struct dmcub_trace_buf_entry entry = { 0 };
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uint32_t count = 0;
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u32 count = 0;
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struct dmub_hpd_work *dmub_hpd_wrk;
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struct dc_link *plink = NULL;
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@ -1045,7 +1045,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
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struct dmub_srv_hw_params hw_params;
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enum dmub_status status;
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const unsigned char *fw_inst_const, *fw_bss_data;
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uint32_t i, fw_inst_const_size, fw_bss_data_size;
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u32 i, fw_inst_const_size, fw_bss_data_size;
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bool has_hw_support;
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if (!dmub_srv)
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@ -1206,10 +1206,10 @@ static void dm_dmub_hw_resume(struct amdgpu_device *adev)
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static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
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{
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uint64_t pt_base;
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uint32_t logical_addr_low;
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uint32_t logical_addr_high;
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uint32_t agp_base, agp_bot, agp_top;
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u64 pt_base;
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u32 logical_addr_low;
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u32 logical_addr_high;
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u32 agp_base, agp_bot, agp_top;
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PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
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memset(pa_config, 0, sizeof(*pa_config));
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@ -2536,7 +2536,7 @@ struct amdgpu_dm_connector *
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amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
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struct drm_crtc *crtc)
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{
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uint32_t i;
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u32 i;
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struct drm_connector_state *new_con_state;
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struct drm_connector *connector;
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struct drm_crtc *crtc_from_state;
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@ -3172,8 +3172,8 @@ static void handle_hpd_irq(void *param)
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static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
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{
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uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
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uint8_t dret;
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u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
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u8 dret;
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bool new_irq_handled = false;
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int dpcd_addr;
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int dpcd_bytes_to_read;
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@ -3201,7 +3201,7 @@ static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
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while (dret == dpcd_bytes_to_read &&
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process_count < max_process_count) {
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uint8_t retry;
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u8 retry;
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dret = 0;
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process_count++;
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@ -3220,7 +3220,7 @@ static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
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dpcd_bytes_to_read - 1;
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for (retry = 0; retry < 3; retry++) {
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uint8_t wret;
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u8 wret;
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wret = drm_dp_dpcd_write(
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&aconnector->dm_dp_aux.aux,
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@ -4236,12 +4236,12 @@ static void amdgpu_set_panel_orientation(struct drm_connector *connector);
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static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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{
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struct amdgpu_display_manager *dm = &adev->dm;
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int32_t i;
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s32 i;
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struct amdgpu_dm_connector *aconnector = NULL;
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struct amdgpu_encoder *aencoder = NULL;
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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uint32_t link_cnt;
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int32_t primary_planes;
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u32 link_cnt;
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s32 primary_planes;
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enum dc_connection_type new_connection_type = dc_connection_none;
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const struct dc_plane_cap *plane;
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bool psr_feature_enabled = false;
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@ -4768,7 +4768,7 @@ fill_plane_color_attributes(const struct drm_plane_state *plane_state,
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static int
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fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
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const struct drm_plane_state *plane_state,
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const uint64_t tiling_flags,
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const u64 tiling_flags,
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struct dc_plane_info *plane_info,
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struct dc_plane_address *address,
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bool tmz_surface,
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@ -4977,7 +4977,7 @@ static void fill_dc_dirty_rects(struct drm_plane *plane,
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uint32_t num_clips;
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bool bb_changed;
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bool fb_changed;
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uint32_t i = 0;
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u32 i = 0;
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flip_addrs->dirty_rect_count = 0;
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@ -5111,7 +5111,7 @@ static enum dc_color_depth
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convert_color_depth_from_display_info(const struct drm_connector *connector,
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bool is_y420, int requested_bpc)
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{
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uint8_t bpc;
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u8 bpc;
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if (is_y420) {
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bpc = 8;
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@ -5655,8 +5655,8 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
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uint32_t max_dsc_target_bpp_limit_override)
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{
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const struct dc_link_settings *verified_link_cap = NULL;
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uint32_t link_bw_in_kbps;
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uint32_t edp_min_bpp_x16, edp_max_bpp_x16;
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u32 link_bw_in_kbps;
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u32 edp_min_bpp_x16, edp_max_bpp_x16;
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struct dc *dc = sink->ctx->dc;
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struct dc_dsc_bw_range bw_range = {0};
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struct dc_dsc_config dsc_cfg = {0};
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@ -5713,11 +5713,11 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
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struct dsc_dec_dpcd_caps *dsc_caps)
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{
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struct drm_connector *drm_connector = &aconnector->base;
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uint32_t link_bandwidth_kbps;
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u32 link_bandwidth_kbps;
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struct dc *dc = sink->ctx->dc;
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uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
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uint32_t dsc_max_supported_bw_in_kbps;
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uint32_t max_dsc_target_bpp_limit_override =
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u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
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u32 dsc_max_supported_bw_in_kbps;
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u32 max_dsc_target_bpp_limit_override =
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drm_connector->display_info.max_dsc_bpp;
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link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
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@ -6871,7 +6871,7 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
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const struct drm_display_mode *m;
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struct drm_display_mode *new_mode;
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uint i;
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uint32_t new_modes_count = 0;
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u32 new_modes_count = 0;
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/* Standard FPS values
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*
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@ -6885,7 +6885,7 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
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* 60 - Commonly used
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* 48,72,96,120 - Multiples of 24
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*/
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static const uint32_t common_rates[] = {
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static const u32 common_rates[] = {
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23976, 24000, 25000, 29970, 30000,
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48000, 50000, 60000, 72000, 96000, 120000
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};
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@ -6901,8 +6901,8 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
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return 0;
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for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
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uint64_t target_vtotal, target_vtotal_diff;
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uint64_t num, den;
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u64 target_vtotal, target_vtotal_diff;
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u64 num, den;
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if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
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continue;
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@ -7150,7 +7150,7 @@ create_i2c(struct ddc_service *ddc_service,
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*/
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static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
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struct amdgpu_dm_connector *aconnector,
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uint32_t link_index,
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u32 link_index,
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struct amdgpu_encoder *aencoder)
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{
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int res = 0;
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@ -7641,8 +7641,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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struct drm_crtc *pcrtc,
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bool wait_for_vblank)
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{
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uint32_t i;
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uint64_t timestamp_ns;
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u32 i;
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u64 timestamp_ns;
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struct drm_plane *plane;
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struct drm_plane_state *old_plane_state, *new_plane_state;
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struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
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@ -7653,7 +7653,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
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int planes_count = 0, vpos, hpos;
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unsigned long flags;
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uint32_t target_vblank, last_flip_vblank;
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u32 target_vblank, last_flip_vblank;
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bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
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bool cursor_update = false;
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bool pflip_present = false;
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@ -8102,7 +8102,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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struct amdgpu_display_manager *dm = &adev->dm;
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struct dm_atomic_state *dm_state;
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struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
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uint32_t i, j;
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u32 i, j;
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struct drm_crtc *crtc;
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struct drm_crtc_state *old_crtc_state, *new_crtc_state;
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unsigned long flags;
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@ -8732,7 +8732,7 @@ is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
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}
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static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
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uint64_t num, den, res;
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u64 num, den, res;
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struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
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dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
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@ -9908,7 +9908,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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static bool is_dp_capable_without_timing_msa(struct dc *dc,
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struct amdgpu_dm_connector *amdgpu_dm_connector)
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{
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uint8_t dpcd_data;
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u8 dpcd_data;
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bool capable = false;
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if (amdgpu_dm_connector->dc_link &&
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@ -9927,7 +9927,7 @@ static bool is_dp_capable_without_timing_msa(struct dc *dc,
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static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
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unsigned int offset,
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unsigned int total_length,
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uint8_t *data,
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u8 *data,
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unsigned int length,
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struct amdgpu_hdmi_vsdb_info *vsdb)
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{
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@ -9982,7 +9982,7 @@ static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
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}
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static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
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uint8_t *edid_ext, int len,
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u8 *edid_ext, int len,
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struct amdgpu_hdmi_vsdb_info *vsdb_info)
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{
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int i;
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@ -10023,7 +10023,7 @@ static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
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}
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static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
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uint8_t *edid_ext, int len,
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u8 *edid_ext, int len,
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struct amdgpu_hdmi_vsdb_info *vsdb_info)
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{
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int i;
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@ -10039,7 +10039,7 @@ static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
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}
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static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
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uint8_t *edid_ext, int len,
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u8 *edid_ext, int len,
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struct amdgpu_hdmi_vsdb_info *vsdb_info)
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{
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struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
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@ -10053,7 +10053,7 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
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static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
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struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
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{
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uint8_t *edid_ext = NULL;
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u8 *edid_ext = NULL;
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int i;
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bool valid_vsdb_found = false;
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@ -10229,7 +10229,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
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}
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void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
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uint32_t value, const char *func_name)
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u32 value, const char *func_name)
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{
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#ifdef DM_CHECK_ADDR_0
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if (address == 0) {
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@ -10244,7 +10244,7 @@ void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
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uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
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const char *func_name)
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{
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uint32_t value;
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u32 value;
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#ifdef DM_CHECK_ADDR_0
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if (address == 0) {
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DC_ERR("invalid register read; address = 0\n");
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