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Merge "interconnect: qcom: Enable disp_rsc for Niobe"

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qctecmdr 2024-04-29 03:27:14 -07:00 committed by Gerrit - the friendly Code Review server
commit be12212a65
2 changed files with 17 additions and 563 deletions
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drivers/interconnect/qcom/niobe.c
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@ -1135,216 +1135,6 @@ static struct qcom_icc_node qnm_mdp1_disp2 = {
.links = { SLAVE_MNOC_HF_MEM_NOC_DISP2 },
};
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_0 = {
.name = "qnm_mnoc_hf_cam_ife_0",
.id = MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_0 },
};
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_0 = {
.name = "qnm_mnoc_sf_cam_ife_0",
.id = MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_0 },
};
static struct qcom_icc_node qnm_pcie_cam_ife_0 = {
.name = "qnm_pcie_cam_ife_0",
.id = MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0,
.channels = 1,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_0 },
};
static struct qcom_icc_node llcc_mc_cam_ife_0 = {
.name = "llcc_mc_cam_ife_0",
.id = MASTER_LLCC_CAM_IFE_0,
.channels = 4,
.buswidth = 4,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_EBI1_CAM_IFE_0 },
};
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_0 = {
.name = "qnm_camnoc_hf_cam_ife_0",
.id = MASTER_CAMNOC_HF_CAM_IFE_0,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 },
};
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_0 = {
.name = "qnm_camnoc_icp_cam_ife_0",
.id = MASTER_CAMNOC_ICP_CAM_IFE_0,
.channels = 1,
.buswidth = 8,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
};
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_0 = {
.name = "qnm_camnoc_sf_cam_ife_0",
.id = MASTER_CAMNOC_SF_CAM_IFE_0,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
};
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_1 = {
.name = "qnm_mnoc_hf_cam_ife_1",
.id = MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_1 },
};
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_1 = {
.name = "qnm_mnoc_sf_cam_ife_1",
.id = MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_1 },
};
static struct qcom_icc_node qnm_pcie_cam_ife_1 = {
.name = "qnm_pcie_cam_ife_1",
.id = MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1,
.channels = 1,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_1 },
};
static struct qcom_icc_node llcc_mc_cam_ife_1 = {
.name = "llcc_mc_cam_ife_1",
.id = MASTER_LLCC_CAM_IFE_1,
.channels = 4,
.buswidth = 4,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_EBI1_CAM_IFE_1 },
};
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_1 = {
.name = "qnm_camnoc_hf_cam_ife_1",
.id = MASTER_CAMNOC_HF_CAM_IFE_1,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 },
};
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_1 = {
.name = "qnm_camnoc_icp_cam_ife_1",
.id = MASTER_CAMNOC_ICP_CAM_IFE_1,
.channels = 1,
.buswidth = 8,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
};
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_1 = {
.name = "qnm_camnoc_sf_cam_ife_1",
.id = MASTER_CAMNOC_SF_CAM_IFE_1,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
};
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_2 = {
.name = "qnm_mnoc_hf_cam_ife_2",
.id = MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_2 },
};
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_2 = {
.name = "qnm_mnoc_sf_cam_ife_2",
.id = MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_2 },
};
static struct qcom_icc_node qnm_pcie_cam_ife_2 = {
.name = "qnm_pcie_cam_ife_2",
.id = MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2,
.channels = 1,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_LLCC_CAM_IFE_2 },
};
static struct qcom_icc_node llcc_mc_cam_ife_2 = {
.name = "llcc_mc_cam_ife_2",
.id = MASTER_LLCC_CAM_IFE_2,
.channels = 4,
.buswidth = 4,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_EBI1_CAM_IFE_2 },
};
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_2 = {
.name = "qnm_camnoc_hf_cam_ife_2",
.id = MASTER_CAMNOC_HF_CAM_IFE_2,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 },
};
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_2 = {
.name = "qnm_camnoc_icp_cam_ife_2",
.id = MASTER_CAMNOC_ICP_CAM_IFE_2,
.channels = 1,
.buswidth = 8,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
};
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_2 = {
.name = "qnm_camnoc_sf_cam_ife_2",
.id = MASTER_CAMNOC_SF_CAM_IFE_2,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
.id = SLAVE_A1NOC_SNOC,
@ -2076,124 +1866,6 @@ static struct qcom_icc_node qns_mem_noc_hf_disp2 = {
.links = { MASTER_MNOC_HF_MEM_NOC_DISP2 },
};
static struct qcom_icc_node qns_llcc_cam_ife_0 = {
.name = "qns_llcc_cam_ife_0",
.id = SLAVE_LLCC_CAM_IFE_0,
.channels = 4,
.buswidth = 16,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_LLCC_CAM_IFE_0 },
};
static struct qcom_icc_node ebi_cam_ife_0 = {
.name = "ebi_cam_ife_0",
.id = SLAVE_EBI1_CAM_IFE_0,
.channels = 4,
.buswidth = 4,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 0,
};
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_0 = {
.name = "qns_mem_noc_hf_cam_ife_0",
.id = SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 },
};
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_0 = {
.name = "qns_mem_noc_sf_cam_ife_0",
.id = SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 },
};
static struct qcom_icc_node qns_llcc_cam_ife_1 = {
.name = "qns_llcc_cam_ife_1",
.id = SLAVE_LLCC_CAM_IFE_1,
.channels = 4,
.buswidth = 16,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_LLCC_CAM_IFE_1 },
};
static struct qcom_icc_node ebi_cam_ife_1 = {
.name = "ebi_cam_ife_1",
.id = SLAVE_EBI1_CAM_IFE_1,
.channels = 4,
.buswidth = 4,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 0,
};
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_1 = {
.name = "qns_mem_noc_hf_cam_ife_1",
.id = SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 },
};
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_1 = {
.name = "qns_mem_noc_sf_cam_ife_1",
.id = SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 },
};
static struct qcom_icc_node qns_llcc_cam_ife_2 = {
.name = "qns_llcc_cam_ife_2",
.id = SLAVE_LLCC_CAM_IFE_2,
.channels = 4,
.buswidth = 16,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_LLCC_CAM_IFE_2 },
};
static struct qcom_icc_node ebi_cam_ife_2 = {
.name = "ebi_cam_ife_2",
.id = SLAVE_EBI1_CAM_IFE_2,
.channels = 4,
.buswidth = 4,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 0,
};
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_2 = {
.name = "qns_mem_noc_hf_cam_ife_2",
.id = SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 },
};
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
.name = "qns_mem_noc_sf_cam_ife_2",
.id = SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2,
.channels = 2,
.buswidth = 32,
.noc_ops = &qcom_qnoc4_ops,
.num_links = 1,
.links = { MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 },
};
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.voter_idx = VOTER_IDX_HLOS,
@ -2379,7 +2051,7 @@ static struct qcom_icc_bcm bcm_sn4 = {
static struct qcom_icc_bcm bcm_acv_disp = {
.name = "ACV",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP,
.enable_mask = 0x1,
.perf_mode_mask = 0x2,
.num_nodes = 1,
@ -2388,28 +2060,28 @@ static struct qcom_icc_bcm bcm_acv_disp = {
static struct qcom_icc_bcm bcm_mc0_disp = {
.name = "MC0",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP,
.num_nodes = 1,
.nodes = { &ebi_disp },
};
static struct qcom_icc_bcm bcm_mm0_disp = {
.name = "MM0",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP,
.num_nodes = 1,
.nodes = { &qns_mem_noc_hf_disp },
};
static struct qcom_icc_bcm bcm_sh0_disp = {
.name = "SH0",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP,
.num_nodes = 1,
.nodes = { &qns_llcc_disp },
};
static struct qcom_icc_bcm bcm_sh1_disp = {
.name = "SH1",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP,
.enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
@ -2417,182 +2089,42 @@ static struct qcom_icc_bcm bcm_sh1_disp = {
static struct qcom_icc_bcm bcm_acv_disp2 = {
.name = "ACV",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP2,
.enable_mask = 0x1,
.perf_mode_mask = 0x2,
.num_nodes = 1,
.nodes = { &ebi_disp2 },
};
static struct qcom_icc_bcm bcm_mc0_disp2 = {
.name = "MC0",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP2,
.num_nodes = 1,
.nodes = { &ebi_disp2 },
};
static struct qcom_icc_bcm bcm_mm0_disp2 = {
.name = "MM0",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP2,
.num_nodes = 1,
.nodes = { &qns_mem_noc_hf_disp2 },
};
static struct qcom_icc_bcm bcm_sh0_disp2 = {
.name = "SH0",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP2,
.num_nodes = 1,
.nodes = { &qns_llcc_disp2 },
};
static struct qcom_icc_bcm bcm_sh1_disp2 = {
.name = "SH1",
.voter_idx = VOTER_IDX_HLOS,
.voter_idx = VOTER_IDX_DISP2,
.enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qnm_mnoc_hf_disp2, &qnm_pcie_disp2 },
};
static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
.name = "ACV",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_0 },
};
static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = {
.name = "MC0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_0 },
};
static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
.name = "MM0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &qns_mem_noc_hf_cam_ife_0 },
};
static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
.name = "MM1",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
&qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
};
static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
.name = "SH0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &qns_llcc_cam_ife_0 },
};
static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
.name = "SH1",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
&qnm_pcie_cam_ife_0 },
};
static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
.name = "ACV",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_1 },
};
static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = {
.name = "MC0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_1 },
};
static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
.name = "MM0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &qns_mem_noc_hf_cam_ife_1 },
};
static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
.name = "MM1",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
&qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
};
static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
.name = "SH0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &qns_llcc_cam_ife_1 },
};
static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
.name = "SH1",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
&qnm_pcie_cam_ife_1 },
};
static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
.name = "ACV",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_2 },
};
static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = {
.name = "MC0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_2 },
};
static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
.name = "MM0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &qns_mem_noc_hf_cam_ife_2 },
};
static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
.name = "MM1",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
&qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
};
static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
.name = "SH0",
.voter_idx = VOTER_IDX_HLOS,
.num_nodes = 1,
.nodes = { &qns_llcc_cam_ife_2 },
};
static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
.name = "SH1",
.voter_idx = VOTER_IDX_HLOS,
.enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
&qnm_pcie_cam_ife_2 },
};
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
};
@ -2780,12 +2312,6 @@ static struct qcom_icc_bcm *gem_noc_bcms[] = {
&bcm_sh1_disp,
&bcm_sh0_disp2,
&bcm_sh1_disp2,
&bcm_sh0_cam_ife_0,
&bcm_sh1_cam_ife_0,
&bcm_sh0_cam_ife_1,
&bcm_sh1_cam_ife_1,
&bcm_sh0_cam_ife_2,
&bcm_sh1_cam_ife_2,
};
static struct qcom_icc_node *gem_noc_nodes[] = {
@ -2809,22 +2335,12 @@ static struct qcom_icc_node *gem_noc_nodes[] = {
[MASTER_MNOC_HF_MEM_NOC_DISP2] = &qnm_mnoc_hf_disp2,
[MASTER_ANOC_PCIE_GEM_NOC_DISP2] = &qnm_pcie_disp2,
[SLAVE_LLCC_DISP2] = &qns_llcc_disp2,
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_hf_cam_ife_0,
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_sf_cam_ife_0,
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0] = &qnm_pcie_cam_ife_0,
[SLAVE_LLCC_CAM_IFE_0] = &qns_llcc_cam_ife_0,
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_hf_cam_ife_1,
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_sf_cam_ife_1,
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1] = &qnm_pcie_cam_ife_1,
[SLAVE_LLCC_CAM_IFE_1] = &qns_llcc_cam_ife_1,
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_hf_cam_ife_2,
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_sf_cam_ife_2,
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2] = &qnm_pcie_cam_ife_2,
[SLAVE_LLCC_CAM_IFE_2] = &qns_llcc_cam_ife_2,
};
static char *gem_noc_voters[] = {
[VOTER_IDX_HLOS] = "hlos",
[VOTER_IDX_DISP] = "disp",
[VOTER_IDX_DISP2] = "disp2",
};
static struct qcom_icc_desc niobe_gem_noc = {
@ -2874,12 +2390,6 @@ static struct qcom_icc_bcm *mc_virt_bcms[] = {
&bcm_mc0_disp,
&bcm_acv_disp2,
&bcm_mc0_disp2,
&bcm_acv_cam_ife_0,
&bcm_mc0_cam_ife_0,
&bcm_acv_cam_ife_1,
&bcm_mc0_cam_ife_1,
&bcm_acv_cam_ife_2,
&bcm_mc0_cam_ife_2,
};
static struct qcom_icc_node *mc_virt_nodes[] = {
@ -2891,16 +2401,12 @@ static struct qcom_icc_node *mc_virt_nodes[] = {
[SLAVE_EBI1_DISP] = &ebi_disp,
[MASTER_LLCC_DISP2] = &llcc_mc_disp2,
[SLAVE_EBI1_DISP2] = &ebi_disp2,
[MASTER_LLCC_CAM_IFE_0] = &llcc_mc_cam_ife_0,
[SLAVE_EBI1_CAM_IFE_0] = &ebi_cam_ife_0,
[MASTER_LLCC_CAM_IFE_1] = &llcc_mc_cam_ife_1,
[SLAVE_EBI1_CAM_IFE_1] = &ebi_cam_ife_1,
[MASTER_LLCC_CAM_IFE_2] = &llcc_mc_cam_ife_2,
[SLAVE_EBI1_CAM_IFE_2] = &ebi_cam_ife_2,
};
static char *mc_virt_voters[] = {
[VOTER_IDX_HLOS] = "hlos",
[VOTER_IDX_DISP] = "disp",
[VOTER_IDX_DISP2] = "disp2",
};
static struct qcom_icc_desc niobe_mc_virt = {
@ -2918,12 +2424,6 @@ static struct qcom_icc_bcm *mmss_noc_bcms[] = {
&bcm_mm1,
&bcm_mm0_disp,
&bcm_mm0_disp2,
&bcm_mm0_cam_ife_0,
&bcm_mm1_cam_ife_0,
&bcm_mm0_cam_ife_1,
&bcm_mm1_cam_ife_1,
&bcm_mm0_cam_ife_2,
&bcm_mm1_cam_ife_2,
};
static struct qcom_icc_node *mmss_noc_nodes[] = {
@ -2946,25 +2446,12 @@ static struct qcom_icc_node *mmss_noc_nodes[] = {
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
[MASTER_MDP1_DISP2] = &qnm_mdp1_disp2,
[SLAVE_MNOC_HF_MEM_NOC_DISP2] = &qns_mem_noc_hf_disp2,
[MASTER_CAMNOC_HF_CAM_IFE_0] = &qnm_camnoc_hf_cam_ife_0,
[MASTER_CAMNOC_ICP_CAM_IFE_0] = &qnm_camnoc_icp_cam_ife_0,
[MASTER_CAMNOC_SF_CAM_IFE_0] = &qnm_camnoc_sf_cam_ife_0,
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_hf_cam_ife_0,
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_sf_cam_ife_0,
[MASTER_CAMNOC_HF_CAM_IFE_1] = &qnm_camnoc_hf_cam_ife_1,
[MASTER_CAMNOC_ICP_CAM_IFE_1] = &qnm_camnoc_icp_cam_ife_1,
[MASTER_CAMNOC_SF_CAM_IFE_1] = &qnm_camnoc_sf_cam_ife_1,
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_hf_cam_ife_1,
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_sf_cam_ife_1,
[MASTER_CAMNOC_HF_CAM_IFE_2] = &qnm_camnoc_hf_cam_ife_2,
[MASTER_CAMNOC_ICP_CAM_IFE_2] = &qnm_camnoc_icp_cam_ife_2,
[MASTER_CAMNOC_SF_CAM_IFE_2] = &qnm_camnoc_sf_cam_ife_2,
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_hf_cam_ife_2,
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_sf_cam_ife_2,
};
static char *mmss_noc_voters[] = {
[VOTER_IDX_HLOS] = "hlos",
[VOTER_IDX_DISP] = "disp",
[VOTER_IDX_DISP2] = "disp2",
};
static struct qcom_icc_desc niobe_mmss_noc = {

33
include/dt-bindings/interconnect/qcom,niobe.h
View File

@ -148,38 +148,5 @@
#define SLAVE_EBI1_DISP2 2512
#define SLAVE_LLCC_DISP2 2513
#define SLAVE_MNOC_HF_MEM_NOC_DISP2 2514
#define MASTER_LLCC_CAM_IFE_0 3000
#define MASTER_CAMNOC_HF_CAM_IFE_0 3001
#define MASTER_CAMNOC_ICP_CAM_IFE_0 3002
#define MASTER_CAMNOC_SF_CAM_IFE_0 3003
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 3004
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 3005
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 3006
#define SLAVE_EBI1_CAM_IFE_0 3512
#define SLAVE_LLCC_CAM_IFE_0 3513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 3514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 3515
#define MASTER_LLCC_CAM_IFE_1 4000
#define MASTER_CAMNOC_HF_CAM_IFE_1 4001
#define MASTER_CAMNOC_ICP_CAM_IFE_1 4002
#define MASTER_CAMNOC_SF_CAM_IFE_1 4003
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 4004
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 4005
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 4006
#define SLAVE_EBI1_CAM_IFE_1 4512
#define SLAVE_LLCC_CAM_IFE_1 4513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 4514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 4515
#define MASTER_LLCC_CAM_IFE_2 5000
#define MASTER_CAMNOC_HF_CAM_IFE_2 5001
#define MASTER_CAMNOC_ICP_CAM_IFE_2 5002
#define MASTER_CAMNOC_SF_CAM_IFE_2 5003
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 5004
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 5005
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 5006
#define SLAVE_EBI1_CAM_IFE_2 5512
#define SLAVE_LLCC_CAM_IFE_2 5513
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 5514
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 5515
#endif