Linux 6.0-rc6
-----BEGIN PGP SIGNATURE----- iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAmMngx4eHHRvcnZhbGRz QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGQ1AH/1p4oOT4iqaoTueO MaTQhyvFFcTSLL4y1qejtytNXe4ZEJHyf03jrwtYlfx8RROkZFMJh15G1uWu2deu 43XsUuSWpJ18/C7hRNl1LUazBbuQe30d09zLe7dvD64IAABU6/iQCIorxheTl4EU NXsda2egJUIbTwn2zdFSgMMJPNORxq8KHgvNY/psIEteC+lFln2l2ZXZ21JAIdBj lcTbvx6JpJC0AqX1UuO6NsN4nUnEEh110UtYF6lxQ7olkQKwRaUjQIVuWOFLz75n wDrJxPlVGbDR5zeitDaHkKqWn8LNcqHpDIuAKMxTjT0N/1/sUwHNkyGZXyy1EDJu e0+SX1c= =ITjo -----END PGP SIGNATURE----- Merge tag 'v6.0-rc6' into android-mainline Linux 6.0-rc6 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I4a39b53deee7410c0b365a31c6b07f8d0b831232
This commit is contained in:
Greg Kroah-Hartman
commit
b587df1dd1
1
.mailmap
1
.mailmap
@ -315,6 +315,7 @@ Morten Welinder <welinder@troll.com>
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||||
Mythri P K <mythripk@ti.com>
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||||
Nadia Yvette Chambers <nyc@holomorphy.com> William Lee Irwin III <wli@holomorphy.com>
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||||
Nathan Chancellor <nathan@kernel.org> <natechancellor@gmail.com>
|
||||
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
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||||
Nguyen Anh Quynh <aquynh@gmail.com>
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||||
Nicholas Piggin <npiggin@gmail.com> <npiggen@suse.de>
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||||
Nicholas Piggin <npiggin@gmail.com> <npiggin@kernel.dk>
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||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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||||
title: Amlogic Meson Firmware registers Interface
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||||
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||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
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||||
description: |
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||||
The Meson SoCs have a register bank with status and data shared with the
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||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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||||
title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
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||||
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||||
maintainers:
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
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||||
allOf:
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||||
- $ref: /schemas/sound/name-prefix.yaml#
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||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson Display Controller
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||||
maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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description: |
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||||
The Amlogic Meson Display controller is composed of several components
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@ -8,7 +8,7 @@ title: Analogix ANX7814 SlimPort (Full-HD Transmitter)
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maintainers:
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- Andrzej Hajda <andrzej.hajda@intel.com>
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Robert Foss <robert.foss@linaro.org>
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properties:
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@ -8,7 +8,7 @@ title: ITE it66121 HDMI bridge Device Tree Bindings
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maintainers:
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- Phong LE <ple@baylibre.com>
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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description: |
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The IT66121 is a high-performance and low-power single channel HDMI
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||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel
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||||
maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
- Thierry Reding <thierry.reding@gmail.com>
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||||
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||||
allOf:
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||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson I2C Controller
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Beniamino Galvani <b.galvani@gmail.com>
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||||
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allOf:
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||||
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic i.MX bus frequency device
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maintainers:
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- Leonard Crestez <leonard.crestez@nxp.com>
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- Peng Fan <peng.fan@nxp.com>
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description: |
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The i.MX SoC family has multiple buses for which clock frequency (and
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@ -96,7 +96,7 @@ properties:
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Documentation/devicetree/bindings/arm/cpus.yaml).
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required:
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- fiq-index
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- apple,fiq-index
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- cpus
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required:
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||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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||||
title: Amlogic Meson Message-Handling-Unit Controller
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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description: |
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The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
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@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic GE2D Acceleration Unit
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||||
maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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properties:
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compatible:
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@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Video Decoder
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Maxime Jourdan <mjourdan@baylibre.com>
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||||
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||||
description: |
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||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson AO-CEC Controller
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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description: |
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||||
The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Khadas on-board Microcontroller Device Tree Bindings
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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description: |
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||||
Khadas embeds a microcontroller on their VIM and Edge boards adding some
|
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@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson DWMAC Ethernet controller
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||||
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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# We need a select here so we don't match all nodes with 'snps,dwmac'
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@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic AXG MIPI D-PHY
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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- Neil Armstrong <neil.armstrong@linaro.org>
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||||
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||||
properties:
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||||
compatible:
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||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic G12A USB2 PHY
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||||
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||||
maintainers:
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
|
||||
properties:
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||||
compatible:
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||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic G12A USB3 + PCIE Combo PHY
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||||
maintainers:
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
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||||
properties:
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||||
compatible:
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||||
|
||||
@ -8,7 +8,6 @@ title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
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||||
Low Power Island (LPI) TLMM block
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||||
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||||
maintainers:
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||||
- Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
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||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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||||
|
||||
description: |
|
||||
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||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SC7280 TLMM block
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||||
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||||
maintainers:
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||||
- Rajendra Nayak <rnayak@codeaurora.org>
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||||
- Bjorn Andersson <andersson@kernel.org>
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||||
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||||
description: |
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||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
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||||
@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic Meson Everything-Else Power Domains
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||||
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||||
maintainers:
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
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||||
description: |+
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||||
The Everything-Else Power Domains node should be the child of a syscon
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||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
title: Qualcomm RPM/RPMh Power domains
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||||
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||||
maintainers:
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||||
- Rajendra Nayak <rnayak@codeaurora.org>
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- Bjorn Andersson <andersson@kernel.org>
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||||
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||||
description:
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||||
For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh
|
||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson SoC Reset Controller
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||||
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||||
maintainers:
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
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||||
properties:
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||||
compatible:
|
||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
title: Amlogic Meson Random number generator
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||||
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||||
maintainers:
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
title: Amlogic Meson SoC UART Serial Interface
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The Amlogic Meson SoC UART Serial Interface is present on a large range
|
||||
|
||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
title: Amlogic Canvas Video Lookup Table
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Maxime Jourdan <mjourdan@baylibre.com>
|
||||
|
||||
description: |
|
||||
|
||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
title: Amlogic Meson SPI Communication Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
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||||
allOf:
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||||
- $ref: "spi-controller.yaml#"
|
||||
|
||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
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||||
title: Amlogic Meson SPI Flash Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
allOf:
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||||
- $ref: "spi-controller.yaml#"
|
||||
|
||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
|
||||
|
||||
maintainers:
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
|
||||
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||||
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
title: Meson GXBB SoCs Watchdog timer
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||||
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||||
maintainers:
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||||
- Neil Armstrong <narmstrong@baylibre.com>
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||||
- Neil Armstrong <neil.armstrong@linaro.org>
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||||
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||||
allOf:
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||||
- $ref: watchdog.yaml#
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||||
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||||
22
MAINTAINERS
22
MAINTAINERS
@ -1803,7 +1803,7 @@ N: sun[x456789]i
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N: sun50i
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||||
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||||
ARM/Amlogic Meson SoC CLOCK FRAMEWORK
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
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||||
M: Neil Armstrong <neil.armstrong@linaro.org>
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||||
M: Jerome Brunet <jbrunet@baylibre.com>
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||||
L: linux-amlogic@lists.infradead.org
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||||
S: Maintained
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@ -1828,7 +1828,7 @@ F: Documentation/devicetree/bindings/sound/amlogic*
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F: sound/soc/meson/
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||||
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||||
ARM/Amlogic Meson SoC support
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||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
M: Kevin Hilman <khilman@baylibre.com>
|
||||
R: Jerome Brunet <jbrunet@baylibre.com>
|
||||
R: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
@ -2531,7 +2531,7 @@ W: http://www.digriz.org.uk/ts78xx/kernel
|
||||
F: arch/arm/mach-orion5x/ts78xx-*
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||||
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||||
ARM/OXNAS platform support
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
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||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-oxnas@groups.io (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
@ -6792,7 +6792,7 @@ F: Documentation/devicetree/bindings/display/allwinner*
|
||||
F: drivers/gpu/drm/sun4i/
|
||||
|
||||
DRM DRIVERS FOR AMLOGIC SOCS
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Supported
|
||||
@ -6814,7 +6814,7 @@ F: drivers/gpu/drm/atmel-hlcdc/
|
||||
|
||||
DRM DRIVERS FOR BRIDGE CHIPS
|
||||
M: Andrzej Hajda <andrzej.hajda@intel.com>
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
M: Robert Foss <robert.foss@linaro.org>
|
||||
R: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
|
||||
R: Jonas Karlman <jonas@kwiboo.se>
|
||||
@ -9122,7 +9122,7 @@ S: Maintained
|
||||
F: drivers/dma/hisi_dma.c
|
||||
|
||||
HISILICON GPIO DRIVER
|
||||
M: Luo Jiaxing <luojiaxing@huawei.com>
|
||||
M: Jay Fang <f.fangjian@huawei.com>
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/gpio/gpio-hisi.c
|
||||
@ -10835,7 +10835,7 @@ F: drivers/media/tuners/it913x*
|
||||
|
||||
ITE IT66121 HDMI BRIDGE DRIVER
|
||||
M: Phong LE <ple@baylibre.com>
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
S: Maintained
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
|
||||
@ -11354,7 +11354,7 @@ F: kernel/debug/
|
||||
F: kernel/module/kdb.c
|
||||
|
||||
KHADAS MCU MFD DRIVER
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
|
||||
@ -13225,7 +13225,7 @@ S: Maintained
|
||||
F: drivers/watchdog/menz69_wdt.c
|
||||
|
||||
MESON AO CEC DRIVER FOR AMLOGIC SOCS
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Supported
|
||||
@ -13236,7 +13236,7 @@ F: drivers/media/cec/platform/meson/ao-cec-g12a.c
|
||||
F: drivers/media/cec/platform/meson/ao-cec.c
|
||||
|
||||
MESON GE2D DRIVER FOR AMLOGIC SOCS
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Supported
|
||||
@ -13252,7 +13252,7 @@ F: Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
|
||||
F: drivers/mtd/nand/raw/meson_*
|
||||
|
||||
MESON VIDEO DECODER DRIVER FOR AMLOGIC SOCS
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Supported
|
||||
|
||||
2
Makefile
2
Makefile
@ -2,7 +2,7 @@
|
||||
VERSION = 6
|
||||
PATCHLEVEL = 0
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Hurr durr I'ma ninja sloth
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
||||
@ -224,8 +224,18 @@ config MLONGCALLS
|
||||
Enabling this option will probably slow down your kernel.
|
||||
|
||||
config 64BIT
|
||||
def_bool "$(ARCH)" = "parisc64"
|
||||
def_bool y if "$(ARCH)" = "parisc64"
|
||||
bool "64-bit kernel" if "$(ARCH)" = "parisc"
|
||||
depends on PA8X00
|
||||
help
|
||||
Enable this if you want to support 64bit kernel on PA-RISC platform.
|
||||
|
||||
At the moment, only people willing to use more than 2GB of RAM,
|
||||
or having a 64bit-only capable PA-RISC machine should say Y here.
|
||||
|
||||
Since there is no 64bit userland on PA-RISC, there is no point to
|
||||
enable this option otherwise. The 64bit kernel is significantly bigger
|
||||
and slower than the 32bit one.
|
||||
|
||||
choice
|
||||
prompt "Kernel page size"
|
||||
|
||||
@ -295,7 +295,7 @@ int blk_queue_enter(struct request_queue *q, blk_mq_req_flags_t flags)
|
||||
|
||||
while (!blk_try_enter_queue(q, pm)) {
|
||||
if (flags & BLK_MQ_REQ_NOWAIT)
|
||||
return -EBUSY;
|
||||
return -EAGAIN;
|
||||
|
||||
/*
|
||||
* read pair of barrier in blk_freeze_queue_start(), we need to
|
||||
@ -325,7 +325,7 @@ int __bio_queue_enter(struct request_queue *q, struct bio *bio)
|
||||
if (test_bit(GD_DEAD, &disk->state))
|
||||
goto dead;
|
||||
bio_wouldblock_error(bio);
|
||||
return -EBUSY;
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -309,6 +309,11 @@ int blkdev_issue_secure_erase(struct block_device *bdev, sector_t sector,
|
||||
struct blk_plug plug;
|
||||
int ret = 0;
|
||||
|
||||
/* make sure that "len << SECTOR_SHIFT" doesn't overflow */
|
||||
if (max_sectors > UINT_MAX >> SECTOR_SHIFT)
|
||||
max_sectors = UINT_MAX >> SECTOR_SHIFT;
|
||||
max_sectors &= ~bs_mask;
|
||||
|
||||
if (max_sectors == 0)
|
||||
return -EOPNOTSUPP;
|
||||
if ((sector | nr_sects) & bs_mask)
|
||||
@ -322,10 +327,10 @@ int blkdev_issue_secure_erase(struct block_device *bdev, sector_t sector,
|
||||
|
||||
bio = blk_next_bio(bio, bdev, 0, REQ_OP_SECURE_ERASE, gfp);
|
||||
bio->bi_iter.bi_sector = sector;
|
||||
bio->bi_iter.bi_size = len;
|
||||
bio->bi_iter.bi_size = len << SECTOR_SHIFT;
|
||||
|
||||
sector += len << SECTOR_SHIFT;
|
||||
nr_sects -= len << SECTOR_SHIFT;
|
||||
sector += len;
|
||||
nr_sects -= len;
|
||||
if (!nr_sects) {
|
||||
ret = submit_bio_wait(bio);
|
||||
bio_put(bio);
|
||||
|
||||
@ -63,6 +63,14 @@ static void ixp4xx_gpio_irq_ack(struct irq_data *d)
|
||||
__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
|
||||
}
|
||||
|
||||
static void ixp4xx_gpio_mask_irq(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
irq_chip_mask_parent(d);
|
||||
gpiochip_disable_irq(gc, d->hwirq);
|
||||
}
|
||||
|
||||
static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
@ -72,6 +80,7 @@ static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
|
||||
if (!(g->irq_edge & BIT(d->hwirq)))
|
||||
ixp4xx_gpio_irq_ack(d);
|
||||
|
||||
gpiochip_enable_irq(gc, d->hwirq);
|
||||
irq_chip_unmask_parent(d);
|
||||
}
|
||||
|
||||
@ -149,12 +158,14 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
|
||||
}
|
||||
|
||||
static struct irq_chip ixp4xx_gpio_irqchip = {
|
||||
static const struct irq_chip ixp4xx_gpio_irqchip = {
|
||||
.name = "IXP4GPIO",
|
||||
.irq_ack = ixp4xx_gpio_irq_ack,
|
||||
.irq_mask = irq_chip_mask_parent,
|
||||
.irq_mask = ixp4xx_gpio_mask_irq,
|
||||
.irq_unmask = ixp4xx_gpio_irq_unmask,
|
||||
.irq_set_type = ixp4xx_gpio_irq_set_type,
|
||||
.flags = IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
|
||||
@ -263,7 +274,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev)
|
||||
g->gc.owner = THIS_MODULE;
|
||||
|
||||
girq = &g->gc.irq;
|
||||
girq->chip = &ixp4xx_gpio_irqchip;
|
||||
gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip);
|
||||
girq->fwnode = g->fwnode;
|
||||
girq->parent_domain = parent;
|
||||
girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
|
||||
|
||||
@ -169,6 +169,7 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
||||
|
||||
switch (flow_type) {
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||||
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
|
||||
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
|
||||
|
||||
@ -112,6 +112,8 @@ mediatek_gpio_irq_unmask(struct irq_data *d)
|
||||
unsigned long flags;
|
||||
u32 rise, fall, high, low;
|
||||
|
||||
gpiochip_enable_irq(gc, d->hwirq);
|
||||
|
||||
spin_lock_irqsave(&rg->lock, flags);
|
||||
rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
|
||||
fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
|
||||
@ -143,6 +145,8 @@ mediatek_gpio_irq_mask(struct irq_data *d)
|
||||
mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
|
||||
mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
|
||||
spin_unlock_irqrestore(&rg->lock, flags);
|
||||
|
||||
gpiochip_disable_irq(gc, d->hwirq);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -204,6 +208,16 @@ mediatek_gpio_xlate(struct gpio_chip *chip,
|
||||
return gpio % MTK_BANK_WIDTH;
|
||||
}
|
||||
|
||||
static const struct irq_chip mt7621_irq_chip = {
|
||||
.name = "mt7621-gpio",
|
||||
.irq_mask_ack = mediatek_gpio_irq_mask,
|
||||
.irq_mask = mediatek_gpio_irq_mask,
|
||||
.irq_unmask = mediatek_gpio_irq_unmask,
|
||||
.irq_set_type = mediatek_gpio_irq_type,
|
||||
.flags = IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int
|
||||
mediatek_gpio_bank_probe(struct device *dev, int bank)
|
||||
{
|
||||
@ -238,11 +252,6 @@ mediatek_gpio_bank_probe(struct device *dev, int bank)
|
||||
return -ENOMEM;
|
||||
|
||||
rg->chip.offset = bank * MTK_BANK_WIDTH;
|
||||
rg->irq_chip.name = dev_name(dev);
|
||||
rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
|
||||
rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
|
||||
rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
|
||||
rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
|
||||
|
||||
if (mtk->gpio_irq) {
|
||||
struct gpio_irq_chip *girq;
|
||||
@ -262,7 +271,7 @@ mediatek_gpio_bank_probe(struct device *dev, int bank)
|
||||
}
|
||||
|
||||
girq = &rg->chip.irq;
|
||||
girq->chip = &rg->irq_chip;
|
||||
gpio_irq_chip_set_chip(girq, &mt7621_irq_chip);
|
||||
/* This will let us handle the parent IRQ in the driver */
|
||||
girq->parent_handler = NULL;
|
||||
girq->num_parents = 0;
|
||||
|
||||
@ -419,11 +419,11 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
goto out;
|
||||
} else {
|
||||
bank->toggle_edge_mode |= mask;
|
||||
level |= mask;
|
||||
level &= ~mask;
|
||||
|
||||
/*
|
||||
* Determine gpio state. If 1 next interrupt should be
|
||||
* falling otherwise rising.
|
||||
* low otherwise high.
|
||||
*/
|
||||
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
|
||||
if (data & mask)
|
||||
|
||||
@ -2365,8 +2365,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
|
||||
}
|
||||
adev->ip_blocks[i].status.sw = true;
|
||||
|
||||
/* need to do gmc hw init early so we can allocate gpu mem */
|
||||
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
|
||||
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
|
||||
/* need to do common hw init early so everything is set up for gmc */
|
||||
r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
|
||||
if (r) {
|
||||
DRM_ERROR("hw_init %d failed %d\n", i, r);
|
||||
goto init_failed;
|
||||
}
|
||||
adev->ip_blocks[i].status.hw = true;
|
||||
} else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
|
||||
/* need to do gmc hw init early so we can allocate gpu mem */
|
||||
/* Try to reserve bad pages early */
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
amdgpu_virt_exchange_data(adev);
|
||||
@ -3052,8 +3060,8 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
|
||||
int i, r;
|
||||
|
||||
static enum amd_ip_block_type ip_order[] = {
|
||||
AMD_IP_BLOCK_TYPE_GMC,
|
||||
AMD_IP_BLOCK_TYPE_COMMON,
|
||||
AMD_IP_BLOCK_TYPE_GMC,
|
||||
AMD_IP_BLOCK_TYPE_PSP,
|
||||
AMD_IP_BLOCK_TYPE_IH,
|
||||
};
|
||||
|
||||
@ -38,6 +38,7 @@
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
#include <drm/drm_damage_helper.h>
|
||||
#include <drm/drm_edid.h>
|
||||
#include <drm/drm_gem_framebuffer_helper.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
@ -496,6 +497,7 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
|
||||
static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
|
||||
.destroy = drm_gem_fb_destroy,
|
||||
.create_handle = drm_gem_fb_create_handle,
|
||||
.dirty = drm_atomic_helper_dirtyfb,
|
||||
};
|
||||
|
||||
uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
|
||||
|
||||
@ -756,7 +756,7 @@ static int psp_tmr_init(struct psp_context *psp)
|
||||
}
|
||||
|
||||
pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
|
||||
ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
|
||||
ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
|
||||
|
||||
|
||||
@ -36,6 +36,7 @@
|
||||
#define PSP_CMD_BUFFER_SIZE 0x1000
|
||||
#define PSP_1_MEG 0x100000
|
||||
#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
|
||||
#define PSP_TMR_ALIGNMENT 0x100000
|
||||
#define PSP_FW_NAME_LEN 0x24
|
||||
|
||||
enum psp_shared_mem_size {
|
||||
|
||||
@ -1811,7 +1811,8 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
|
||||
amdgpu_ras_query_error_status(adev, &info);
|
||||
|
||||
if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
|
||||
adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
|
||||
adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
|
||||
adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
|
||||
if (amdgpu_ras_reset_error_status(adev, info.head.block))
|
||||
dev_warn(adev->dev, "Failed to reset error counter and error status");
|
||||
}
|
||||
|
||||
@ -380,6 +380,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL, data);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t def, data;
|
||||
@ -401,9 +402,11 @@ static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
|
||||
{
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
uint32_t def, data;
|
||||
|
||||
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
|
||||
@ -459,7 +462,10 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL6, data);
|
||||
|
||||
nbio_v2_3_program_ltr(adev);
|
||||
/* Don't bother about LTR if LTR is not enabled
|
||||
* in the path */
|
||||
if (adev->pdev->ltr_path)
|
||||
nbio_v2_3_program_ltr(adev);
|
||||
|
||||
def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
|
||||
data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
|
||||
@ -483,6 +489,7 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
|
||||
data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL3, data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
|
||||
|
||||
@ -282,6 +282,7 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
|
||||
mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t def, data;
|
||||
@ -303,9 +304,11 @@ static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)
|
||||
{
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
uint32_t def, data;
|
||||
|
||||
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
|
||||
@ -361,7 +364,10 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL6, data);
|
||||
|
||||
nbio_v6_1_program_ltr(adev);
|
||||
/* Don't bother about LTR if LTR is not enabled
|
||||
* in the path */
|
||||
if (adev->pdev->ltr_path)
|
||||
nbio_v6_1_program_ltr(adev);
|
||||
|
||||
def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
|
||||
data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
|
||||
@ -385,6 +391,7 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)
|
||||
data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL3, data);
|
||||
#endif
|
||||
}
|
||||
|
||||
const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
|
||||
|
||||
@ -673,6 +673,7 @@ struct amdgpu_nbio_ras nbio_v7_4_ras = {
|
||||
};
|
||||
|
||||
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t def, data;
|
||||
@ -694,9 +695,11 @@ static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
|
||||
{
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
uint32_t def, data;
|
||||
|
||||
if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(7, 4, 4))
|
||||
@ -755,7 +758,10 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL6, data);
|
||||
|
||||
nbio_v7_4_program_ltr(adev);
|
||||
/* Don't bother about LTR if LTR is not enabled
|
||||
* in the path */
|
||||
if (adev->pdev->ltr_path)
|
||||
nbio_v7_4_program_ltr(adev);
|
||||
|
||||
def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
|
||||
data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
|
||||
@ -779,6 +785,7 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
|
||||
data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL3, data);
|
||||
#endif
|
||||
}
|
||||
|
||||
const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
|
||||
|
||||
@ -28,6 +28,14 @@
|
||||
#include "nbio/nbio_7_7_0_sh_mask.h"
|
||||
#include <uapi/linux/kfd_ioctl.h>
|
||||
|
||||
static void nbio_v7_7_remap_hdp_registers(struct amdgpu_device *adev)
|
||||
{
|
||||
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
|
||||
adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
|
||||
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
|
||||
adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
|
||||
}
|
||||
|
||||
static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
|
||||
{
|
||||
u32 tmp;
|
||||
@ -336,4 +344,5 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
|
||||
.get_clockgating_state = nbio_v7_7_get_clockgating_state,
|
||||
.ih_control = nbio_v7_7_ih_control,
|
||||
.init_registers = nbio_v7_7_init_registers,
|
||||
.remap_hdp_registers = nbio_v7_7_remap_hdp_registers,
|
||||
};
|
||||
|
||||
@ -1504,6 +1504,11 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
|
||||
WREG32_SDMA(i, mmSDMA0_CNTL, temp);
|
||||
|
||||
if (!amdgpu_sriov_vf(adev)) {
|
||||
ring = &adev->sdma.instance[i].ring;
|
||||
adev->nbio.funcs->sdma_doorbell_range(adev, i,
|
||||
ring->use_doorbell, ring->doorbell_index,
|
||||
adev->doorbell_index.sdma_doorbell_range);
|
||||
|
||||
/* unhalt engine */
|
||||
temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
|
||||
temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
|
||||
|
||||
@ -1211,25 +1211,6 @@ static int soc15_common_sw_fini(void *handle)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void soc15_doorbell_range_init(struct amdgpu_device *adev)
|
||||
{
|
||||
int i;
|
||||
struct amdgpu_ring *ring;
|
||||
|
||||
/* sdma/ih doorbell range are programed by hypervisor */
|
||||
if (!amdgpu_sriov_vf(adev)) {
|
||||
for (i = 0; i < adev->sdma.num_instances; i++) {
|
||||
ring = &adev->sdma.instance[i].ring;
|
||||
adev->nbio.funcs->sdma_doorbell_range(adev, i,
|
||||
ring->use_doorbell, ring->doorbell_index,
|
||||
adev->doorbell_index.sdma_doorbell_range);
|
||||
}
|
||||
|
||||
adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
|
||||
adev->irq.ih.doorbell_index);
|
||||
}
|
||||
}
|
||||
|
||||
static int soc15_common_hw_init(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
@ -1249,12 +1230,6 @@ static int soc15_common_hw_init(void *handle)
|
||||
|
||||
/* enable the doorbell aperture */
|
||||
soc15_enable_doorbell_aperture(adev, true);
|
||||
/* HW doorbell routing policy: doorbell writing not
|
||||
* in SDMA/IH/MM/ACV range will be routed to CP. So
|
||||
* we need to init SDMA/IH/MM/ACV doorbell range prior
|
||||
* to CP ip block init and ring test.
|
||||
*/
|
||||
soc15_doorbell_range_init(adev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -421,6 +421,7 @@ static bool soc21_need_full_reset(struct amdgpu_device *adev)
|
||||
{
|
||||
switch (adev->ip_versions[GC_HWIP][0]) {
|
||||
case IP_VERSION(11, 0, 0):
|
||||
return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
|
||||
case IP_VERSION(11, 0, 2):
|
||||
return false;
|
||||
default:
|
||||
|
||||
@ -289,6 +289,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
|
||||
}
|
||||
}
|
||||
|
||||
if (!amdgpu_sriov_vf(adev))
|
||||
adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
|
||||
adev->irq.ih.doorbell_index);
|
||||
|
||||
pci_set_master(adev->pdev);
|
||||
|
||||
/* enable interrupts */
|
||||
|
||||
@ -340,6 +340,10 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
|
||||
}
|
||||
}
|
||||
|
||||
if (!amdgpu_sriov_vf(adev))
|
||||
adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
|
||||
adev->irq.ih.doorbell_index);
|
||||
|
||||
pci_set_master(adev->pdev);
|
||||
|
||||
/* enable interrupts */
|
||||
|
||||
@ -670,6 +670,8 @@ static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *cl
|
||||
}
|
||||
ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
|
||||
bw_params->vram_type = bios_info->memory_type;
|
||||
|
||||
bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
|
||||
bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
|
||||
|
||||
for (i = 0; i < WM_SET_COUNT; i++) {
|
||||
|
||||
@ -329,7 +329,7 @@ bool dc_stream_set_cursor_attributes(
|
||||
|
||||
dc = stream->ctx->dc;
|
||||
|
||||
if (attributes->height * attributes->width * 4 > 16384)
|
||||
if (dc->debug.allow_sw_cursor_fallback && attributes->height * attributes->width * 4 > 16384)
|
||||
if (stream->mall_stream_config.type == SUBVP_MAIN)
|
||||
return false;
|
||||
|
||||
|
||||
@ -745,6 +745,7 @@ struct dc_debug_options {
|
||||
bool disable_fixed_vs_aux_timeout_wa;
|
||||
bool force_disable_subvp;
|
||||
bool force_subvp_mclk_switch;
|
||||
bool allow_sw_cursor_fallback;
|
||||
bool force_usr_allow;
|
||||
/* uses value at boot and disables switch */
|
||||
bool disable_dtb_ref_clk_switch;
|
||||
|
||||
@ -417,44 +417,42 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,
|
||||
struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
|
||||
struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
|
||||
struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
|
||||
int16_t drr_frame_us = 0;
|
||||
int16_t min_drr_supported_us = 0;
|
||||
int16_t max_drr_supported_us = 0;
|
||||
int16_t max_drr_vblank_us = 0;
|
||||
int16_t max_drr_mallregion_us = 0;
|
||||
int16_t mall_region_us = 0;
|
||||
int16_t prefetch_us = 0;
|
||||
int16_t subvp_active_us = 0;
|
||||
int16_t drr_active_us = 0;
|
||||
int16_t min_vtotal_supported = 0;
|
||||
int16_t max_vtotal_supported = 0;
|
||||
uint16_t drr_frame_us = 0;
|
||||
uint16_t min_drr_supported_us = 0;
|
||||
uint16_t max_drr_supported_us = 0;
|
||||
uint16_t max_drr_vblank_us = 0;
|
||||
uint16_t max_drr_mallregion_us = 0;
|
||||
uint16_t mall_region_us = 0;
|
||||
uint16_t prefetch_us = 0;
|
||||
uint16_t subvp_active_us = 0;
|
||||
uint16_t drr_active_us = 0;
|
||||
uint16_t min_vtotal_supported = 0;
|
||||
uint16_t max_vtotal_supported = 0;
|
||||
|
||||
pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true;
|
||||
pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
|
||||
pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
|
||||
|
||||
drr_frame_us = div64_s64(drr_timing->v_total * drr_timing->h_total,
|
||||
(int64_t)(drr_timing->pix_clk_100hz * 100) * 1000000);
|
||||
drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000),
|
||||
(((uint64_t)drr_timing->pix_clk_100hz * 100)));
|
||||
// P-State allow width and FW delays already included phantom_timing->v_addressable
|
||||
mall_region_us = div64_s64(phantom_timing->v_addressable * phantom_timing->h_total,
|
||||
(int64_t)(phantom_timing->pix_clk_100hz * 100) * 1000000);
|
||||
mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000),
|
||||
(((uint64_t)phantom_timing->pix_clk_100hz * 100)));
|
||||
min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
|
||||
min_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 *
|
||||
(div64_s64((int64_t)min_drr_supported_us, 1000000)),
|
||||
(int64_t)drr_timing->h_total);
|
||||
min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us),
|
||||
(((uint64_t)drr_timing->h_total * 1000000)));
|
||||
|
||||
prefetch_us = div64_s64((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total,
|
||||
(int64_t)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
|
||||
dc->caps.subvp_prefetch_end_to_mall_start_us);
|
||||
subvp_active_us = div64_s64(main_timing->v_addressable * main_timing->h_total,
|
||||
(int64_t)(main_timing->pix_clk_100hz * 100) * 1000000);
|
||||
drr_active_us = div64_s64(drr_timing->v_addressable * drr_timing->h_total,
|
||||
(int64_t)(drr_timing->pix_clk_100hz * 100) * 1000000);
|
||||
max_drr_vblank_us = div64_s64((int64_t)(subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us;
|
||||
prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000),
|
||||
(((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
|
||||
subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000),
|
||||
(((uint64_t)main_timing->pix_clk_100hz * 100)));
|
||||
drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000),
|
||||
(((uint64_t)drr_timing->pix_clk_100hz * 100)));
|
||||
max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us;
|
||||
max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us;
|
||||
max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
|
||||
max_vtotal_supported = div64_s64(drr_timing->pix_clk_100hz * 100 * (div64_s64((int64_t)max_drr_supported_us, 1000000)),
|
||||
(int64_t)drr_timing->h_total);
|
||||
max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us),
|
||||
(((uint64_t)drr_timing->h_total * 1000000)));
|
||||
|
||||
pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
|
||||
pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
|
||||
@ -548,10 +546,12 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
|
||||
struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
|
||||
struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
|
||||
|
||||
subvp0_prefetch_us = div64_s64((phantom_timing0->v_total - phantom_timing0->v_front_porch) * phantom_timing0->h_total,
|
||||
(int64_t)(phantom_timing0->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us);
|
||||
subvp1_prefetch_us = div64_s64((phantom_timing1->v_total - phantom_timing1->v_front_porch) * phantom_timing1->h_total,
|
||||
(int64_t)(phantom_timing1->pix_clk_100hz * 100) * 1000000 + dc->caps.subvp_prefetch_end_to_mall_start_us);
|
||||
subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
|
||||
(uint64_t)phantom_timing0->h_total * 1000000),
|
||||
(((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
|
||||
subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
|
||||
(uint64_t)phantom_timing1->h_total * 1000000),
|
||||
(((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
|
||||
|
||||
// Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
|
||||
// should increase it's prefetch time to match the other
|
||||
@ -559,16 +559,17 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
|
||||
pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
|
||||
prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
|
||||
pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
|
||||
div64_s64(((div64_s64((int64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us), 1000000)) *
|
||||
(phantom_timing1->pix_clk_100hz * 100) + phantom_timing1->h_total - 1),
|
||||
(int64_t)phantom_timing1->h_total);
|
||||
div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
|
||||
((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
|
||||
((uint64_t)phantom_timing1->h_total * 1000000));
|
||||
|
||||
} else if (subvp1_prefetch_us > subvp0_prefetch_us) {
|
||||
pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
|
||||
prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
|
||||
pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
|
||||
div64_s64(((div64_s64((int64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us), 1000000)) *
|
||||
(phantom_timing0->pix_clk_100hz * 100) + phantom_timing0->h_total - 1),
|
||||
(int64_t)phantom_timing0->h_total);
|
||||
div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
|
||||
((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
|
||||
((uint64_t)phantom_timing0->h_total * 1000000));
|
||||
}
|
||||
}
|
||||
|
||||
@ -630,13 +631,11 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
|
||||
|
||||
// Round up
|
||||
pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
|
||||
div64_s64(((div64_s64((int64_t)dc->caps.subvp_prefetch_end_to_mall_start_us, 1000000)) *
|
||||
(phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1),
|
||||
(int64_t)phantom_timing->h_total);
|
||||
div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
|
||||
((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
|
||||
pipe_data->pipe_config.subvp_data.processing_delay_lines =
|
||||
div64_s64(((div64_s64((int64_t)dc->caps.subvp_fw_processing_delay_us, 1000000)) *
|
||||
(phantom_timing->pix_clk_100hz * 100) + phantom_timing->h_total - 1),
|
||||
(int64_t)phantom_timing->h_total);
|
||||
div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
|
||||
((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
|
||||
// Find phantom pipe index based on phantom stream
|
||||
for (j = 0; j < dc->res_pool->pipe_count; j++) {
|
||||
struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j];
|
||||
|
||||
@ -67,8 +67,7 @@ static void enc314_disable_fifo(struct stream_encoder *enc)
|
||||
{
|
||||
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
||||
|
||||
REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0,
|
||||
DIG_FIFO_READ_START_LEVEL, 0);
|
||||
REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);
|
||||
}
|
||||
|
||||
static void enc314_dp_set_odm_combine(
|
||||
|
||||
@ -103,6 +103,11 @@ void hubp32_cursor_set_attributes(
|
||||
enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
|
||||
attr->width, attr->color_format);
|
||||
|
||||
//Round cursor width up to next multiple of 64
|
||||
uint32_t cursor_width = ((attr->width + 63) / 64) * 64;
|
||||
uint32_t cursor_height = attr->height;
|
||||
uint32_t cursor_size = cursor_width * cursor_height;
|
||||
|
||||
hubp->curs_attr = *attr;
|
||||
|
||||
REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
|
||||
@ -126,7 +131,24 @@ void hubp32_cursor_set_attributes(
|
||||
/* used to shift the cursor chunk request deadline */
|
||||
CURSOR0_CHUNK_HDL_ADJUST, 3);
|
||||
|
||||
if (attr->width * attr->height * 4 > 16384)
|
||||
switch (attr->color_format) {
|
||||
case CURSOR_MODE_MONO:
|
||||
cursor_size /= 2;
|
||||
break;
|
||||
case CURSOR_MODE_COLOR_1BIT_AND:
|
||||
case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
|
||||
case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
|
||||
cursor_size *= 4;
|
||||
break;
|
||||
|
||||
case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
|
||||
case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
|
||||
default:
|
||||
cursor_size *= 8;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cursor_size > 16384)
|
||||
REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true);
|
||||
else
|
||||
REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false);
|
||||
|
||||
@ -741,7 +741,29 @@ void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
|
||||
struct hubp *hubp = pipe->plane_res.hubp;
|
||||
|
||||
if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
|
||||
if (hubp->curs_attr.width * hubp->curs_attr.height * 4 > 16384)
|
||||
//Round cursor width up to next multiple of 64
|
||||
int cursor_width = ((hubp->curs_attr.width + 63) / 64) * 64;
|
||||
int cursor_height = hubp->curs_attr.height;
|
||||
int cursor_size = cursor_width * cursor_height;
|
||||
|
||||
switch (hubp->curs_attr.color_format) {
|
||||
case CURSOR_MODE_MONO:
|
||||
cursor_size /= 2;
|
||||
break;
|
||||
case CURSOR_MODE_COLOR_1BIT_AND:
|
||||
case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
|
||||
case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
|
||||
cursor_size *= 4;
|
||||
break;
|
||||
|
||||
case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
|
||||
case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
|
||||
default:
|
||||
cursor_size *= 8;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cursor_size > 16384)
|
||||
cache_cursor = true;
|
||||
|
||||
if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
|
||||
|
||||
@ -871,6 +871,7 @@ static const struct dc_debug_options debug_defaults_drv = {
|
||||
.exit_idle_opt_for_cursor_updates = true,
|
||||
.enable_single_display_2to1_odm_policy = true,
|
||||
.enable_dp_dig_pixel_rate_div_policy = 1,
|
||||
.allow_sw_cursor_fallback = false,
|
||||
};
|
||||
|
||||
static const struct dc_debug_options debug_defaults_diags = {
|
||||
@ -2039,7 +2040,8 @@ static bool dcn32_resource_construct(
|
||||
dc->caps.max_downscale_ratio = 600;
|
||||
dc->caps.i2c_speed_in_khz = 100;
|
||||
dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
|
||||
dc->caps.max_cursor_size = 256;
|
||||
/* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/
|
||||
dc->caps.max_cursor_size = 64;
|
||||
dc->caps.min_horizontal_blanking_period = 80;
|
||||
dc->caps.dmdata_alloc_size = 2048;
|
||||
dc->caps.mall_size_per_mem_channel = 0;
|
||||
|
||||
@ -30,6 +30,9 @@
|
||||
|
||||
#define DCN3_2_DET_SEG_SIZE 64
|
||||
#define DCN3_2_MALL_MBLK_SIZE_BYTES 65536 // 64 * 1024
|
||||
#define DCN3_2_MBLK_WIDTH 128
|
||||
#define DCN3_2_MBLK_HEIGHT_4BPE 128
|
||||
#define DCN3_2_MBLK_HEIGHT_8BPE 64
|
||||
|
||||
#define TO_DCN32_RES_POOL(pool)\
|
||||
container_of(pool, struct dcn32_resource_pool, base)
|
||||
|
||||
@ -46,7 +46,6 @@
|
||||
uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc *dc, struct dc_state *context)
|
||||
{
|
||||
uint32_t num_ways = 0;
|
||||
uint32_t mall_region_pixels = 0;
|
||||
uint32_t bytes_per_pixel = 0;
|
||||
uint32_t cache_lines_used = 0;
|
||||
uint32_t lines_per_way = 0;
|
||||
@ -54,20 +53,64 @@ uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc *dc, struct dc_stat
|
||||
uint32_t bytes_in_mall = 0;
|
||||
uint32_t num_mblks = 0;
|
||||
uint32_t cache_lines_per_plane = 0;
|
||||
uint32_t i = 0;
|
||||
uint32_t i = 0, j = 0;
|
||||
uint32_t mblk_width = 0;
|
||||
uint32_t mblk_height = 0;
|
||||
uint32_t full_vp_width_blk_aligned = 0;
|
||||
uint32_t full_vp_height_blk_aligned = 0;
|
||||
uint32_t mall_alloc_width_blk_aligned = 0;
|
||||
uint32_t mall_alloc_height_blk_aligned = 0;
|
||||
uint32_t full_vp_height = 0;
|
||||
|
||||
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
||||
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
|
||||
|
||||
// Find the phantom pipes
|
||||
if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
|
||||
if (pipe->stream && pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe &&
|
||||
pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
|
||||
bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;
|
||||
mall_region_pixels = pipe->plane_state->plane_size.surface_pitch * pipe->stream->timing.v_addressable;
|
||||
struct pipe_ctx *main_pipe = NULL;
|
||||
|
||||
// For bytes required in MALL, calculate based on number of MBlks required
|
||||
num_mblks = (mall_region_pixels * bytes_per_pixel +
|
||||
DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / DCN3_2_MALL_MBLK_SIZE_BYTES;
|
||||
/* Get full viewport height from main pipe (required for MBLK calculation) */
|
||||
for (j = 0; j < dc->res_pool->pipe_count; j++) {
|
||||
main_pipe = &context->res_ctx.pipe_ctx[j];
|
||||
if (main_pipe->stream == pipe->stream->mall_stream_config.paired_stream) {
|
||||
full_vp_height = main_pipe->plane_res.scl_data.viewport.height;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
bytes_per_pixel = pipe->plane_state->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;
|
||||
mblk_width = DCN3_2_MBLK_WIDTH;
|
||||
mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE;
|
||||
|
||||
/* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) -
|
||||
* FLOOR(vp_x_start, blk_width)
|
||||
*/
|
||||
full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x +
|
||||
pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) +
|
||||
(pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width);
|
||||
|
||||
/* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) -
|
||||
* FLOOR(vp_y_start, blk_height)
|
||||
*/
|
||||
full_vp_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y +
|
||||
full_vp_height + mblk_height - 1) / mblk_height * mblk_height) +
|
||||
(pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height);
|
||||
|
||||
/* mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c */
|
||||
mall_alloc_width_blk_aligned = full_vp_width_blk_aligned;
|
||||
|
||||
/* mall_alloc_height_blk_aligned_l/c = CEILING(sub_vp_height_l/c - 1, blk_height_l/c) + blk_height_l/c */
|
||||
mall_alloc_height_blk_aligned = (pipe->stream->timing.v_addressable - 1 + mblk_height - 1) /
|
||||
mblk_height * mblk_height + mblk_height;
|
||||
|
||||
/* full_mblk_width_ub_l/c = mall_alloc_width_blk_aligned_l/c;
|
||||
* full_mblk_height_ub_l/c = mall_alloc_height_blk_aligned_l/c;
|
||||
* num_mblk_l/c = (full_mblk_width_ub_l/c / mblk_width_l/c) * (full_mblk_height_ub_l/c / mblk_height_l/c);
|
||||
* (Should be divisible, but round up if not)
|
||||
*/
|
||||
num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *
|
||||
((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);
|
||||
bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;
|
||||
// cache lines used is total bytes / cache_line size. Add +2 for worst case alignment
|
||||
// (MALL is 64-byte aligned)
|
||||
|
||||
@ -872,6 +872,7 @@ static const struct dc_debug_options debug_defaults_drv = {
|
||||
.exit_idle_opt_for_cursor_updates = true,
|
||||
.enable_single_display_2to1_odm_policy = true,
|
||||
.enable_dp_dig_pixel_rate_div_policy = 1,
|
||||
.allow_sw_cursor_fallback = false,
|
||||
};
|
||||
|
||||
static const struct dc_debug_options debug_defaults_diags = {
|
||||
@ -1651,7 +1652,8 @@ static bool dcn321_resource_construct(
|
||||
dc->caps.max_downscale_ratio = 600;
|
||||
dc->caps.i2c_speed_in_khz = 100;
|
||||
dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
|
||||
dc->caps.max_cursor_size = 256;
|
||||
/* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
|
||||
dc->caps.max_cursor_size = 64;
|
||||
dc->caps.min_horizontal_blanking_period = 80;
|
||||
dc->caps.dmdata_alloc_size = 2048;
|
||||
dc->caps.mall_size_per_mem_channel = 0;
|
||||
|
||||
@ -70,6 +70,8 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) $(fram
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn314/display_mode_vba_314.o := $(dml_ccflags) $(frame_warn_flag)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn314/display_rq_dlg_calc_314.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn314/dcn314_fpu.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/dcn32_fpu.o := $(dml_ccflags)
|
||||
@ -123,6 +125,7 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
|
||||
DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
|
||||
DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
|
||||
DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o
|
||||
DML += dcn314/display_mode_vba_314.o dcn314/display_rq_dlg_calc_314.o
|
||||
DML += dcn32/display_mode_vba_32.o dcn32/display_rq_dlg_calc_32.o dcn32/display_mode_vba_util_32.o
|
||||
DML += dcn31/dcn31_fpu.o
|
||||
DML += dcn32/dcn32_fpu.o
|
||||
|
||||
@ -6610,8 +6610,7 @@ static double CalculateUrgentLatency(
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void UseMinimumDCFCLK(
|
||||
static noinline_for_stack void UseMinimumDCFCLK(
|
||||
struct display_mode_lib *mode_lib,
|
||||
int MaxInterDCNTileRepeaters,
|
||||
int MaxPrefetchMode,
|
||||
|
||||
@ -251,33 +251,13 @@ static void CalculateRowBandwidth(
|
||||
|
||||
static void CalculateFlipSchedule(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int k,
|
||||
double HostVMInefficiencyFactor,
|
||||
double UrgentExtraLatency,
|
||||
double UrgentLatency,
|
||||
unsigned int GPUVMMaxPageTableLevels,
|
||||
bool HostVMEnable,
|
||||
unsigned int HostVMMaxNonCachedPageTableLevels,
|
||||
bool GPUVMEnable,
|
||||
double HostVMMinPageSize,
|
||||
double PDEAndMetaPTEBytesPerFrame,
|
||||
double MetaRowBytes,
|
||||
double DPTEBytesPerRow,
|
||||
double BandwidthAvailableForImmediateFlip,
|
||||
unsigned int TotImmediateFlipBytes,
|
||||
enum source_format_class SourcePixelFormat,
|
||||
double LineTime,
|
||||
double VRatio,
|
||||
double VRatioChroma,
|
||||
double Tno_bw,
|
||||
bool DCCEnable,
|
||||
unsigned int dpte_row_height,
|
||||
unsigned int meta_row_height,
|
||||
unsigned int dpte_row_height_chroma,
|
||||
unsigned int meta_row_height_chroma,
|
||||
double *DestinationLinesToRequestVMInImmediateFlip,
|
||||
double *DestinationLinesToRequestRowInImmediateFlip,
|
||||
double *final_flip_bw,
|
||||
bool *ImmediateFlipSupportedForPipe);
|
||||
double DPTEBytesPerRow);
|
||||
static double CalculateWriteBackDelay(
|
||||
enum source_format_class WritebackPixelFormat,
|
||||
double WritebackHRatio,
|
||||
@ -311,64 +291,28 @@ static void CalculateVupdateAndDynamicMetadataParameters(
|
||||
static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int PrefetchMode,
|
||||
unsigned int NumberOfActivePlanes,
|
||||
unsigned int MaxLineBufferLines,
|
||||
unsigned int LineBufferSize,
|
||||
unsigned int WritebackInterfaceBufferSize,
|
||||
double DCFCLK,
|
||||
double ReturnBW,
|
||||
bool SynchronizedVBlank,
|
||||
unsigned int dpte_group_bytes[],
|
||||
unsigned int MetaChunkSize,
|
||||
double UrgentLatency,
|
||||
double ExtraLatency,
|
||||
double WritebackLatency,
|
||||
double WritebackChunkSize,
|
||||
double SOCCLK,
|
||||
double DRAMClockChangeLatency,
|
||||
double SRExitTime,
|
||||
double SREnterPlusExitTime,
|
||||
double SRExitZ8Time,
|
||||
double SREnterPlusExitZ8Time,
|
||||
double DCFCLKDeepSleep,
|
||||
unsigned int DETBufferSizeY[],
|
||||
unsigned int DETBufferSizeC[],
|
||||
unsigned int SwathHeightY[],
|
||||
unsigned int SwathHeightC[],
|
||||
unsigned int LBBitPerPixel[],
|
||||
double SwathWidthY[],
|
||||
double SwathWidthC[],
|
||||
double HRatio[],
|
||||
double HRatioChroma[],
|
||||
unsigned int vtaps[],
|
||||
unsigned int VTAPsChroma[],
|
||||
double VRatio[],
|
||||
double VRatioChroma[],
|
||||
unsigned int HTotal[],
|
||||
double PixelClock[],
|
||||
unsigned int BlendingAndTiming[],
|
||||
unsigned int DPPPerPlane[],
|
||||
double BytePerPixelDETY[],
|
||||
double BytePerPixelDETC[],
|
||||
double DSTXAfterScaler[],
|
||||
double DSTYAfterScaler[],
|
||||
bool WritebackEnable[],
|
||||
enum source_format_class WritebackPixelFormat[],
|
||||
double WritebackDestinationWidth[],
|
||||
double WritebackDestinationHeight[],
|
||||
double WritebackSourceHeight[],
|
||||
bool UnboundedRequestEnabled,
|
||||
int unsigned CompressedBufferSizeInkByte,
|
||||
enum clock_change_support *DRAMClockChangeSupport,
|
||||
double *UrgentWatermark,
|
||||
double *WritebackUrgentWatermark,
|
||||
double *DRAMClockChangeWatermark,
|
||||
double *WritebackDRAMClockChangeWatermark,
|
||||
double *StutterExitWatermark,
|
||||
double *StutterEnterPlusExitWatermark,
|
||||
double *Z8StutterExitWatermark,
|
||||
double *Z8StutterEnterPlusExitWatermark,
|
||||
double *MinActiveDRAMClockChangeLatencySupported);
|
||||
double *Z8StutterEnterPlusExitWatermark);
|
||||
|
||||
static void CalculateDCFCLKDeepSleep(
|
||||
struct display_mode_lib *mode_lib,
|
||||
@ -2904,33 +2848,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
CalculateFlipSchedule(
|
||||
mode_lib,
|
||||
k,
|
||||
HostVMInefficiencyFactor,
|
||||
v->UrgentExtraLatency,
|
||||
v->UrgentLatency,
|
||||
v->GPUVMMaxPageTableLevels,
|
||||
v->HostVMEnable,
|
||||
v->HostVMMaxNonCachedPageTableLevels,
|
||||
v->GPUVMEnable,
|
||||
v->HostVMMinPageSize,
|
||||
v->PDEAndMetaPTEBytesFrame[k],
|
||||
v->MetaRowByte[k],
|
||||
v->PixelPTEBytesPerRow[k],
|
||||
v->BandwidthAvailableForImmediateFlip,
|
||||
v->TotImmediateFlipBytes,
|
||||
v->SourcePixelFormat[k],
|
||||
v->HTotal[k] / v->PixelClock[k],
|
||||
v->VRatio[k],
|
||||
v->VRatioChroma[k],
|
||||
v->Tno_bw[k],
|
||||
v->DCCEnable[k],
|
||||
v->dpte_row_height[k],
|
||||
v->meta_row_height[k],
|
||||
v->dpte_row_height_chroma[k],
|
||||
v->meta_row_height_chroma[k],
|
||||
&v->DestinationLinesToRequestVMInImmediateFlip[k],
|
||||
&v->DestinationLinesToRequestRowInImmediateFlip[k],
|
||||
&v->final_flip_bw[k],
|
||||
&v->ImmediateFlipSupportedForPipe[k]);
|
||||
v->PixelPTEBytesPerRow[k]);
|
||||
}
|
||||
|
||||
v->total_dcn_read_bw_with_flip = 0.0;
|
||||
@ -3017,64 +2941,28 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
||||
CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
mode_lib,
|
||||
PrefetchMode,
|
||||
v->NumberOfActivePlanes,
|
||||
v->MaxLineBufferLines,
|
||||
v->LineBufferSize,
|
||||
v->WritebackInterfaceBufferSize,
|
||||
v->DCFCLK,
|
||||
v->ReturnBW,
|
||||
v->SynchronizedVBlank,
|
||||
v->dpte_group_bytes,
|
||||
v->MetaChunkSize,
|
||||
v->UrgentLatency,
|
||||
v->UrgentExtraLatency,
|
||||
v->WritebackLatency,
|
||||
v->WritebackChunkSize,
|
||||
v->SOCCLK,
|
||||
v->DRAMClockChangeLatency,
|
||||
v->SRExitTime,
|
||||
v->SREnterPlusExitTime,
|
||||
v->SRExitZ8Time,
|
||||
v->SREnterPlusExitZ8Time,
|
||||
v->DCFCLKDeepSleep,
|
||||
v->DETBufferSizeY,
|
||||
v->DETBufferSizeC,
|
||||
v->SwathHeightY,
|
||||
v->SwathHeightC,
|
||||
v->LBBitPerPixel,
|
||||
v->SwathWidthY,
|
||||
v->SwathWidthC,
|
||||
v->HRatio,
|
||||
v->HRatioChroma,
|
||||
v->vtaps,
|
||||
v->VTAPsChroma,
|
||||
v->VRatio,
|
||||
v->VRatioChroma,
|
||||
v->HTotal,
|
||||
v->PixelClock,
|
||||
v->BlendingAndTiming,
|
||||
v->DPPPerPlane,
|
||||
v->BytePerPixelDETY,
|
||||
v->BytePerPixelDETC,
|
||||
v->DSTXAfterScaler,
|
||||
v->DSTYAfterScaler,
|
||||
v->WritebackEnable,
|
||||
v->WritebackPixelFormat,
|
||||
v->WritebackDestinationWidth,
|
||||
v->WritebackDestinationHeight,
|
||||
v->WritebackSourceHeight,
|
||||
v->UnboundedRequestEnabled,
|
||||
v->CompressedBufferSizeInkByte,
|
||||
&DRAMClockChangeSupport,
|
||||
&v->UrgentWatermark,
|
||||
&v->WritebackUrgentWatermark,
|
||||
&v->DRAMClockChangeWatermark,
|
||||
&v->WritebackDRAMClockChangeWatermark,
|
||||
&v->StutterExitWatermark,
|
||||
&v->StutterEnterPlusExitWatermark,
|
||||
&v->Z8StutterExitWatermark,
|
||||
&v->Z8StutterEnterPlusExitWatermark,
|
||||
&v->MinActiveDRAMClockChangeLatencySupported);
|
||||
&v->Z8StutterEnterPlusExitWatermark);
|
||||
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (v->WritebackEnable[k] == true) {
|
||||
@ -3598,61 +3486,43 @@ static void CalculateRowBandwidth(
|
||||
|
||||
static void CalculateFlipSchedule(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int k,
|
||||
double HostVMInefficiencyFactor,
|
||||
double UrgentExtraLatency,
|
||||
double UrgentLatency,
|
||||
unsigned int GPUVMMaxPageTableLevels,
|
||||
bool HostVMEnable,
|
||||
unsigned int HostVMMaxNonCachedPageTableLevels,
|
||||
bool GPUVMEnable,
|
||||
double HostVMMinPageSize,
|
||||
double PDEAndMetaPTEBytesPerFrame,
|
||||
double MetaRowBytes,
|
||||
double DPTEBytesPerRow,
|
||||
double BandwidthAvailableForImmediateFlip,
|
||||
unsigned int TotImmediateFlipBytes,
|
||||
enum source_format_class SourcePixelFormat,
|
||||
double LineTime,
|
||||
double VRatio,
|
||||
double VRatioChroma,
|
||||
double Tno_bw,
|
||||
bool DCCEnable,
|
||||
unsigned int dpte_row_height,
|
||||
unsigned int meta_row_height,
|
||||
unsigned int dpte_row_height_chroma,
|
||||
unsigned int meta_row_height_chroma,
|
||||
double *DestinationLinesToRequestVMInImmediateFlip,
|
||||
double *DestinationLinesToRequestRowInImmediateFlip,
|
||||
double *final_flip_bw,
|
||||
bool *ImmediateFlipSupportedForPipe)
|
||||
double DPTEBytesPerRow)
|
||||
{
|
||||
struct vba_vars_st *v = &mode_lib->vba;
|
||||
double min_row_time = 0.0;
|
||||
unsigned int HostVMDynamicLevelsTrips;
|
||||
double TimeForFetchingMetaPTEImmediateFlip;
|
||||
double TimeForFetchingRowInVBlankImmediateFlip;
|
||||
double ImmediateFlipBW;
|
||||
double LineTime = v->HTotal[k] / v->PixelClock[k];
|
||||
|
||||
if (GPUVMEnable == true && HostVMEnable == true) {
|
||||
HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
|
||||
if (v->GPUVMEnable == true && v->HostVMEnable == true) {
|
||||
HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
|
||||
} else {
|
||||
HostVMDynamicLevelsTrips = 0;
|
||||
}
|
||||
|
||||
if (GPUVMEnable == true || DCCEnable == true) {
|
||||
ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
|
||||
if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {
|
||||
ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * v->BandwidthAvailableForImmediateFlip / v->TotImmediateFlipBytes;
|
||||
}
|
||||
|
||||
if (GPUVMEnable == true) {
|
||||
if (v->GPUVMEnable == true) {
|
||||
TimeForFetchingMetaPTEImmediateFlip = dml_max3(
|
||||
Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
|
||||
UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1),
|
||||
v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
|
||||
UrgentExtraLatency + UrgentLatency * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1),
|
||||
LineTime / 4.0);
|
||||
} else {
|
||||
TimeForFetchingMetaPTEImmediateFlip = 0;
|
||||
}
|
||||
|
||||
*DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
|
||||
if ((GPUVMEnable == true || DCCEnable == true)) {
|
||||
v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
|
||||
if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
|
||||
TimeForFetchingRowInVBlankImmediateFlip = dml_max3(
|
||||
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW,
|
||||
UrgentLatency * (HostVMDynamicLevelsTrips + 1),
|
||||
@ -3661,54 +3531,54 @@ static void CalculateFlipSchedule(
|
||||
TimeForFetchingRowInVBlankImmediateFlip = 0;
|
||||
}
|
||||
|
||||
*DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
|
||||
v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
|
||||
|
||||
if (GPUVMEnable == true) {
|
||||
*final_flip_bw = dml_max(
|
||||
PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime),
|
||||
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime));
|
||||
} else if ((GPUVMEnable == true || DCCEnable == true)) {
|
||||
*final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime);
|
||||
if (v->GPUVMEnable == true) {
|
||||
v->final_flip_bw[k] = dml_max(
|
||||
PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime),
|
||||
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime));
|
||||
} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
|
||||
v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime);
|
||||
} else {
|
||||
*final_flip_bw = 0;
|
||||
v->final_flip_bw[k] = 0;
|
||||
}
|
||||
|
||||
if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) {
|
||||
if (GPUVMEnable == true && DCCEnable != true) {
|
||||
min_row_time = dml_min(dpte_row_height * LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma);
|
||||
} else if (GPUVMEnable != true && DCCEnable == true) {
|
||||
min_row_time = dml_min(meta_row_height * LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma);
|
||||
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
|
||||
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
|
||||
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
|
||||
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
|
||||
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
|
||||
} else {
|
||||
min_row_time = dml_min4(
|
||||
dpte_row_height * LineTime / VRatio,
|
||||
meta_row_height * LineTime / VRatio,
|
||||
dpte_row_height_chroma * LineTime / VRatioChroma,
|
||||
meta_row_height_chroma * LineTime / VRatioChroma);
|
||||
v->dpte_row_height[k] * LineTime / v->VRatio[k],
|
||||
v->meta_row_height[k] * LineTime / v->VRatio[k],
|
||||
v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k],
|
||||
v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
|
||||
}
|
||||
} else {
|
||||
if (GPUVMEnable == true && DCCEnable != true) {
|
||||
min_row_time = dpte_row_height * LineTime / VRatio;
|
||||
} else if (GPUVMEnable != true && DCCEnable == true) {
|
||||
min_row_time = meta_row_height * LineTime / VRatio;
|
||||
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
|
||||
min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k];
|
||||
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
|
||||
min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k];
|
||||
} else {
|
||||
min_row_time = dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio);
|
||||
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
|
||||
}
|
||||
}
|
||||
|
||||
if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16
|
||||
if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16
|
||||
|| TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) {
|
||||
*ImmediateFlipSupportedForPipe = false;
|
||||
v->ImmediateFlipSupportedForPipe[k] = false;
|
||||
} else {
|
||||
*ImmediateFlipSupportedForPipe = true;
|
||||
v->ImmediateFlipSupportedForPipe[k] = true;
|
||||
}
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestVMInImmediateFlip);
|
||||
dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestRowInImmediateFlip);
|
||||
dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]);
|
||||
dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]);
|
||||
dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip);
|
||||
dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n", __func__, TimeForFetchingRowInVBlankImmediateFlip);
|
||||
dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time);
|
||||
dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe);
|
||||
dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]);
|
||||
#endif
|
||||
|
||||
}
|
||||
@ -5300,33 +5170,13 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
||||
for (k = 0; k < v->NumberOfActivePlanes; k++) {
|
||||
CalculateFlipSchedule(
|
||||
mode_lib,
|
||||
k,
|
||||
HostVMInefficiencyFactor,
|
||||
v->ExtraLatency,
|
||||
v->UrgLatency[i],
|
||||
v->GPUVMMaxPageTableLevels,
|
||||
v->HostVMEnable,
|
||||
v->HostVMMaxNonCachedPageTableLevels,
|
||||
v->GPUVMEnable,
|
||||
v->HostVMMinPageSize,
|
||||
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
|
||||
v->MetaRowBytes[i][j][k],
|
||||
v->DPTEBytesPerRow[i][j][k],
|
||||
v->BandwidthAvailableForImmediateFlip,
|
||||
v->TotImmediateFlipBytes,
|
||||
v->SourcePixelFormat[k],
|
||||
v->HTotal[k] / v->PixelClock[k],
|
||||
v->VRatio[k],
|
||||
v->VRatioChroma[k],
|
||||
v->Tno_bw[k],
|
||||
v->DCCEnable[k],
|
||||
v->dpte_row_height[k],
|
||||
v->meta_row_height[k],
|
||||
v->dpte_row_height_chroma[k],
|
||||
v->meta_row_height_chroma[k],
|
||||
&v->DestinationLinesToRequestVMInImmediateFlip[k],
|
||||
&v->DestinationLinesToRequestRowInImmediateFlip[k],
|
||||
&v->final_flip_bw[k],
|
||||
&v->ImmediateFlipSupportedForPipe[k]);
|
||||
v->DPTEBytesPerRow[i][j][k]);
|
||||
}
|
||||
v->total_dcn_read_bw_with_flip = 0.0;
|
||||
for (k = 0; k < v->NumberOfActivePlanes; k++) {
|
||||
@ -5384,64 +5234,28 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
||||
CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
mode_lib,
|
||||
v->PrefetchModePerState[i][j],
|
||||
v->NumberOfActivePlanes,
|
||||
v->MaxLineBufferLines,
|
||||
v->LineBufferSize,
|
||||
v->WritebackInterfaceBufferSize,
|
||||
v->DCFCLKState[i][j],
|
||||
v->ReturnBWPerState[i][j],
|
||||
v->SynchronizedVBlank,
|
||||
v->dpte_group_bytes,
|
||||
v->MetaChunkSize,
|
||||
v->UrgLatency[i],
|
||||
v->ExtraLatency,
|
||||
v->WritebackLatency,
|
||||
v->WritebackChunkSize,
|
||||
v->SOCCLKPerState[i],
|
||||
v->DRAMClockChangeLatency,
|
||||
v->SRExitTime,
|
||||
v->SREnterPlusExitTime,
|
||||
v->SRExitZ8Time,
|
||||
v->SREnterPlusExitZ8Time,
|
||||
v->ProjectedDCFCLKDeepSleep[i][j],
|
||||
v->DETBufferSizeYThisState,
|
||||
v->DETBufferSizeCThisState,
|
||||
v->SwathHeightYThisState,
|
||||
v->SwathHeightCThisState,
|
||||
v->LBBitPerPixel,
|
||||
v->SwathWidthYThisState,
|
||||
v->SwathWidthCThisState,
|
||||
v->HRatio,
|
||||
v->HRatioChroma,
|
||||
v->vtaps,
|
||||
v->VTAPsChroma,
|
||||
v->VRatio,
|
||||
v->VRatioChroma,
|
||||
v->HTotal,
|
||||
v->PixelClock,
|
||||
v->BlendingAndTiming,
|
||||
v->NoOfDPPThisState,
|
||||
v->BytePerPixelInDETY,
|
||||
v->BytePerPixelInDETC,
|
||||
v->DSTXAfterScaler,
|
||||
v->DSTYAfterScaler,
|
||||
v->WritebackEnable,
|
||||
v->WritebackPixelFormat,
|
||||
v->WritebackDestinationWidth,
|
||||
v->WritebackDestinationHeight,
|
||||
v->WritebackSourceHeight,
|
||||
UnboundedRequestEnabledThisState,
|
||||
CompressedBufferSizeInkByteThisState,
|
||||
&v->DRAMClockChangeSupport[i][j],
|
||||
&v->UrgentWatermark,
|
||||
&v->WritebackUrgentWatermark,
|
||||
&v->DRAMClockChangeWatermark,
|
||||
&v->WritebackDRAMClockChangeWatermark,
|
||||
&dummy,
|
||||
&dummy,
|
||||
&dummy,
|
||||
&dummy,
|
||||
&v->MinActiveDRAMClockChangeLatencySupported);
|
||||
&dummy);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5566,64 +5380,28 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
||||
static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int PrefetchMode,
|
||||
unsigned int NumberOfActivePlanes,
|
||||
unsigned int MaxLineBufferLines,
|
||||
unsigned int LineBufferSize,
|
||||
unsigned int WritebackInterfaceBufferSize,
|
||||
double DCFCLK,
|
||||
double ReturnBW,
|
||||
bool SynchronizedVBlank,
|
||||
unsigned int dpte_group_bytes[],
|
||||
unsigned int MetaChunkSize,
|
||||
double UrgentLatency,
|
||||
double ExtraLatency,
|
||||
double WritebackLatency,
|
||||
double WritebackChunkSize,
|
||||
double SOCCLK,
|
||||
double DRAMClockChangeLatency,
|
||||
double SRExitTime,
|
||||
double SREnterPlusExitTime,
|
||||
double SRExitZ8Time,
|
||||
double SREnterPlusExitZ8Time,
|
||||
double DCFCLKDeepSleep,
|
||||
unsigned int DETBufferSizeY[],
|
||||
unsigned int DETBufferSizeC[],
|
||||
unsigned int SwathHeightY[],
|
||||
unsigned int SwathHeightC[],
|
||||
unsigned int LBBitPerPixel[],
|
||||
double SwathWidthY[],
|
||||
double SwathWidthC[],
|
||||
double HRatio[],
|
||||
double HRatioChroma[],
|
||||
unsigned int vtaps[],
|
||||
unsigned int VTAPsChroma[],
|
||||
double VRatio[],
|
||||
double VRatioChroma[],
|
||||
unsigned int HTotal[],
|
||||
double PixelClock[],
|
||||
unsigned int BlendingAndTiming[],
|
||||
unsigned int DPPPerPlane[],
|
||||
double BytePerPixelDETY[],
|
||||
double BytePerPixelDETC[],
|
||||
double DSTXAfterScaler[],
|
||||
double DSTYAfterScaler[],
|
||||
bool WritebackEnable[],
|
||||
enum source_format_class WritebackPixelFormat[],
|
||||
double WritebackDestinationWidth[],
|
||||
double WritebackDestinationHeight[],
|
||||
double WritebackSourceHeight[],
|
||||
bool UnboundedRequestEnabled,
|
||||
int unsigned CompressedBufferSizeInkByte,
|
||||
enum clock_change_support *DRAMClockChangeSupport,
|
||||
double *UrgentWatermark,
|
||||
double *WritebackUrgentWatermark,
|
||||
double *DRAMClockChangeWatermark,
|
||||
double *WritebackDRAMClockChangeWatermark,
|
||||
double *StutterExitWatermark,
|
||||
double *StutterEnterPlusExitWatermark,
|
||||
double *Z8StutterExitWatermark,
|
||||
double *Z8StutterEnterPlusExitWatermark,
|
||||
double *MinActiveDRAMClockChangeLatencySupported)
|
||||
double *Z8StutterEnterPlusExitWatermark)
|
||||
{
|
||||
struct vba_vars_st *v = &mode_lib->vba;
|
||||
double EffectiveLBLatencyHidingY;
|
||||
@ -5643,103 +5421,103 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
double TotalPixelBW = 0.0;
|
||||
int k, j;
|
||||
|
||||
*UrgentWatermark = UrgentLatency + ExtraLatency;
|
||||
v->UrgentWatermark = UrgentLatency + ExtraLatency;
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: UrgentLatency = %f\n", __func__, UrgentLatency);
|
||||
dml_print("DML::%s: ExtraLatency = %f\n", __func__, ExtraLatency);
|
||||
dml_print("DML::%s: UrgentWatermark = %f\n", __func__, *UrgentWatermark);
|
||||
dml_print("DML::%s: UrgentWatermark = %f\n", __func__, v->UrgentWatermark);
|
||||
#endif
|
||||
|
||||
*DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark;
|
||||
v->DRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->UrgentWatermark;
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, DRAMClockChangeLatency);
|
||||
dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, *DRAMClockChangeWatermark);
|
||||
dml_print("DML::%s: v->DRAMClockChangeLatency = %f\n", __func__, v->DRAMClockChangeLatency);
|
||||
dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, v->DRAMClockChangeWatermark);
|
||||
#endif
|
||||
|
||||
v->TotalActiveWriteback = 0;
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (WritebackEnable[k] == true) {
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (v->WritebackEnable[k] == true) {
|
||||
v->TotalActiveWriteback = v->TotalActiveWriteback + 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (v->TotalActiveWriteback <= 1) {
|
||||
*WritebackUrgentWatermark = WritebackLatency;
|
||||
v->WritebackUrgentWatermark = v->WritebackLatency;
|
||||
} else {
|
||||
*WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
}
|
||||
|
||||
if (v->TotalActiveWriteback <= 1) {
|
||||
*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency;
|
||||
v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency;
|
||||
} else {
|
||||
*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
}
|
||||
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
TotalPixelBW = TotalPixelBW
|
||||
+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k])
|
||||
/ (HTotal[k] / PixelClock[k]);
|
||||
+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k])
|
||||
/ (v->HTotal[k] / v->PixelClock[k]);
|
||||
}
|
||||
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
double EffectiveDETBufferSizeY = DETBufferSizeY[k];
|
||||
|
||||
v->LBLatencyHidingSourceLinesY = dml_min(
|
||||
(double) MaxLineBufferLines,
|
||||
dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1);
|
||||
(double) v->MaxLineBufferLines,
|
||||
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
|
||||
|
||||
v->LBLatencyHidingSourceLinesC = dml_min(
|
||||
(double) MaxLineBufferLines,
|
||||
dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1);
|
||||
(double) v->MaxLineBufferLines,
|
||||
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
|
||||
|
||||
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]);
|
||||
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
|
||||
|
||||
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]);
|
||||
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
|
||||
|
||||
if (UnboundedRequestEnabled) {
|
||||
EffectiveDETBufferSizeY = EffectiveDETBufferSizeY
|
||||
+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] / (HTotal[k] / PixelClock[k]) / TotalPixelBW;
|
||||
+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
|
||||
}
|
||||
|
||||
LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
|
||||
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
|
||||
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
|
||||
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
|
||||
if (BytePerPixelDETC[k] > 0) {
|
||||
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
|
||||
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
|
||||
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k];
|
||||
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
|
||||
} else {
|
||||
LinesInDETC = 0;
|
||||
FullDETBufferingTimeC = 999999;
|
||||
}
|
||||
|
||||
ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY
|
||||
- ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark;
|
||||
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
|
||||
|
||||
if (NumberOfActivePlanes > 1) {
|
||||
if (v->NumberOfActivePlanes > 1) {
|
||||
ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY
|
||||
- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
|
||||
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
|
||||
}
|
||||
|
||||
if (BytePerPixelDETC[k] > 0) {
|
||||
ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC
|
||||
- ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark;
|
||||
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
|
||||
|
||||
if (NumberOfActivePlanes > 1) {
|
||||
if (v->NumberOfActivePlanes > 1) {
|
||||
ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC
|
||||
- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k];
|
||||
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
|
||||
}
|
||||
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
|
||||
} else {
|
||||
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
|
||||
}
|
||||
|
||||
if (WritebackEnable[k] == true) {
|
||||
WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024
|
||||
/ (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4);
|
||||
if (WritebackPixelFormat[k] == dm_444_64) {
|
||||
if (v->WritebackEnable[k] == true) {
|
||||
WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024
|
||||
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
|
||||
if (v->WritebackPixelFormat[k] == dm_444_64) {
|
||||
WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2;
|
||||
}
|
||||
WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark;
|
||||
@ -5749,14 +5527,14 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
|
||||
v->MinActiveDRAMClockChangeMargin = 999999;
|
||||
PlaneWithMinActiveDRAMClockChangeMargin = 0;
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
|
||||
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
|
||||
if (BlendingAndTiming[k] == k) {
|
||||
if (v->BlendingAndTiming[k] == k) {
|
||||
PlaneWithMinActiveDRAMClockChangeMargin = k;
|
||||
} else {
|
||||
for (j = 0; j < NumberOfActivePlanes; ++j) {
|
||||
if (BlendingAndTiming[k] == j) {
|
||||
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
|
||||
if (v->BlendingAndTiming[k] == j) {
|
||||
PlaneWithMinActiveDRAMClockChangeMargin = j;
|
||||
}
|
||||
}
|
||||
@ -5764,11 +5542,11 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
}
|
||||
}
|
||||
|
||||
*MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency;
|
||||
v->MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + v->DRAMClockChangeLatency ;
|
||||
|
||||
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999;
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
|
||||
&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
|
||||
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
|
||||
}
|
||||
@ -5776,25 +5554,25 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
|
||||
|
||||
v->TotalNumberOfActiveOTG = 0;
|
||||
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k) {
|
||||
if (BlendingAndTiming[k] == k) {
|
||||
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
|
||||
if (v->BlendingAndTiming[k] == k) {
|
||||
v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (v->MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) {
|
||||
*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
|
||||
} else if ((SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1
|
||||
} else if ((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1
|
||||
|| SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0) {
|
||||
*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
|
||||
} else {
|
||||
*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
|
||||
}
|
||||
|
||||
*StutterExitWatermark = SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
|
||||
*StutterEnterPlusExitWatermark = (SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep);
|
||||
*Z8StutterExitWatermark = SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
|
||||
*Z8StutterEnterPlusExitWatermark = SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
|
||||
*StutterExitWatermark = v->SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
|
||||
*StutterEnterPlusExitWatermark = (v->SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep);
|
||||
*Z8StutterExitWatermark = v->SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
|
||||
*Z8StutterEnterPlusExitWatermark = v->SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, *StutterExitWatermark);
|
||||
|
||||
@ -194,6 +194,9 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
|
||||
dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
|
||||
dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;
|
||||
|
||||
if (bw_params->dram_channel_width_bytes > 0)
|
||||
dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes;
|
||||
|
||||
if (bw_params->num_channels > 0)
|
||||
dcn3_14_soc.num_chans = bw_params->num_channels;
|
||||
|
||||
@ -262,7 +265,7 @@ void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
|
||||
}
|
||||
|
||||
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
|
||||
dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31);
|
||||
dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN314);
|
||||
else
|
||||
dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA);
|
||||
}
|
||||
|
||||
@ -61,7 +61,7 @@
|
||||
// fudge factor for min dcfclk calclation
|
||||
#define __DML_MIN_DCFCLK_FACTOR__ 1.15
|
||||
|
||||
struct {
|
||||
typedef struct {
|
||||
double DPPCLK;
|
||||
double DISPCLK;
|
||||
double PixelClock;
|
||||
@ -1599,7 +1599,7 @@ static void CalculateDCCConfiguration(
|
||||
int segment_order_vert_contiguous_luma;
|
||||
int segment_order_vert_contiguous_chroma;
|
||||
|
||||
enum {
|
||||
typedef enum {
|
||||
REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
|
||||
} RequestType;
|
||||
RequestType RequestLuma;
|
||||
@ -4071,9 +4071,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
|
||||
|
||||
v->SourceFormatPixelAndScanSupport = true;
|
||||
for (k = 0; k < v->NumberOfActivePlanes; k++) {
|
||||
if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
|
||||
|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t
|
||||
|| v->SurfaceTiling[k] == dm_sw_64kb_d_x) && !(v->SourcePixelFormat[k] == dm_444_64))) {
|
||||
if (v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) {
|
||||
v->SourceFormatPixelAndScanSupport = false;
|
||||
}
|
||||
}
|
||||
@ -7157,12 +7155,13 @@ static double CalculateExtraLatencyBytes(
|
||||
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
|
||||
else
|
||||
HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
|
||||
else
|
||||
} else {
|
||||
HostVMDynamicLevels = 0;
|
||||
}
|
||||
|
||||
ret = ReorderingBytes + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte + TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0;
|
||||
|
||||
if (GPUVMEnable == true)
|
||||
if (GPUVMEnable == true) {
|
||||
for (k = 0; k < NumberOfActivePlanes; ++k)
|
||||
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
|
||||
}
|
||||
|
||||
@ -755,30 +755,18 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
||||
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelY = v->BytePerPixelY[k];
|
||||
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelC = v->BytePerPixelC[k];
|
||||
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
|
||||
v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
|
||||
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe, v->DSCDelay[k],
|
||||
mode_lib->vba.DPPCLKDelaySubtotal + mode_lib->vba.DPPCLKDelayCNVCFormater,
|
||||
mode_lib->vba.DPPCLKDelaySCL,
|
||||
mode_lib->vba.DPPCLKDelaySCLLBOnly,
|
||||
mode_lib->vba.DPPCLKDelayCNVCCursor,
|
||||
mode_lib->vba.DISPCLKDelaySubtotal,
|
||||
(unsigned int) (v->SwathWidthY[k] / mode_lib->vba.HRatio[k]),
|
||||
mode_lib->vba.OutputFormat[k],
|
||||
mode_lib->vba.MaxInterDCNTileRepeaters,
|
||||
v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(
|
||||
v,
|
||||
k,
|
||||
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
|
||||
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe,
|
||||
v->DSCDelay[k],
|
||||
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
|
||||
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
|
||||
v->MaxVStartupLines[k],
|
||||
mode_lib->vba.GPUVMMaxPageTableLevels,
|
||||
mode_lib->vba.GPUVMEnable,
|
||||
mode_lib->vba.HostVMEnable,
|
||||
mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
|
||||
mode_lib->vba.HostVMMinPageSize,
|
||||
mode_lib->vba.DynamicMetadataEnable[k],
|
||||
mode_lib->vba.DynamicMetadataVMEnabled,
|
||||
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
|
||||
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
|
||||
v->UrgentLatency,
|
||||
v->UrgentExtraLatency,
|
||||
mode_lib->vba.TCalc,
|
||||
v->TCalc,
|
||||
v->PDEAndMetaPTEBytesFrame[k],
|
||||
v->MetaRowByte[k],
|
||||
v->PixelPTEBytesPerRow[k],
|
||||
@ -792,8 +780,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
||||
v->MaxNumSwathC[k],
|
||||
v->swath_width_luma_ub[k],
|
||||
v->swath_width_chroma_ub[k],
|
||||
mode_lib->vba.SwathHeightY[k],
|
||||
mode_lib->vba.SwathHeightC[k],
|
||||
v->SwathHeightY[k],
|
||||
v->SwathHeightC[k],
|
||||
TWait,
|
||||
/* Output */
|
||||
&v->DSTXAfterScaler[k],
|
||||
@ -1163,58 +1151,28 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
||||
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.SMNLatency = mode_lib->vba.SMNLatency;
|
||||
|
||||
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
mode_lib->vba.USRRetrainingRequiredFinal,
|
||||
mode_lib->vba.UsesMALLForPStateChange,
|
||||
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
|
||||
mode_lib->vba.NumberOfActiveSurfaces,
|
||||
mode_lib->vba.MaxLineBufferLines,
|
||||
mode_lib->vba.LineBufferSizeFinal,
|
||||
mode_lib->vba.WritebackInterfaceBufferSize,
|
||||
mode_lib->vba.DCFCLK,
|
||||
mode_lib->vba.ReturnBW,
|
||||
mode_lib->vba.SynchronizeTimingsFinal,
|
||||
mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
|
||||
mode_lib->vba.DRRDisplay,
|
||||
v->dpte_group_bytes,
|
||||
v->meta_row_height,
|
||||
v->meta_row_height_chroma,
|
||||
v,
|
||||
v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb],
|
||||
v->DCFCLK,
|
||||
v->ReturnBW,
|
||||
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters,
|
||||
mode_lib->vba.WritebackChunkSize,
|
||||
mode_lib->vba.SOCCLK,
|
||||
v->SOCCLK,
|
||||
v->DCFCLKDeepSleep,
|
||||
mode_lib->vba.DETBufferSizeY,
|
||||
mode_lib->vba.DETBufferSizeC,
|
||||
mode_lib->vba.SwathHeightY,
|
||||
mode_lib->vba.SwathHeightC,
|
||||
mode_lib->vba.LBBitPerPixel,
|
||||
v->DETBufferSizeY,
|
||||
v->DETBufferSizeC,
|
||||
v->SwathHeightY,
|
||||
v->SwathHeightC,
|
||||
v->SwathWidthY,
|
||||
v->SwathWidthC,
|
||||
mode_lib->vba.HRatio,
|
||||
mode_lib->vba.HRatioChroma,
|
||||
mode_lib->vba.vtaps,
|
||||
mode_lib->vba.VTAPsChroma,
|
||||
mode_lib->vba.VRatio,
|
||||
mode_lib->vba.VRatioChroma,
|
||||
mode_lib->vba.HTotal,
|
||||
mode_lib->vba.VTotal,
|
||||
mode_lib->vba.VActive,
|
||||
mode_lib->vba.PixelClock,
|
||||
mode_lib->vba.BlendingAndTiming,
|
||||
mode_lib->vba.DPPPerPlane,
|
||||
v->DPPPerPlane,
|
||||
v->BytePerPixelDETY,
|
||||
v->BytePerPixelDETC,
|
||||
v->DSTXAfterScaler,
|
||||
v->DSTYAfterScaler,
|
||||
mode_lib->vba.WritebackEnable,
|
||||
mode_lib->vba.WritebackPixelFormat,
|
||||
mode_lib->vba.WritebackDestinationWidth,
|
||||
mode_lib->vba.WritebackDestinationHeight,
|
||||
mode_lib->vba.WritebackSourceHeight,
|
||||
v->UnboundedRequestEnabled,
|
||||
v->CompressedBufferSizeInkByte,
|
||||
|
||||
/* Output */
|
||||
&v->Watermark,
|
||||
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_dramchange_support,
|
||||
v->MaxActiveDRAMClockChangeLatencySupported,
|
||||
v->SubViewportLinesNeededInMALL,
|
||||
@ -1806,10 +1764,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
||||
&mode_lib->vba.Read256BlockHeightC[k],
|
||||
&mode_lib->vba.Read256BlockWidthY[k],
|
||||
&mode_lib->vba.Read256BlockWidthC[k],
|
||||
&mode_lib->vba.MicroTileHeightY[k],
|
||||
&mode_lib->vba.MicroTileHeightC[k],
|
||||
&mode_lib->vba.MicroTileWidthY[k],
|
||||
&mode_lib->vba.MicroTileWidthC[k]);
|
||||
&mode_lib->vba.MacroTileHeightY[k],
|
||||
&mode_lib->vba.MacroTileHeightC[k],
|
||||
&mode_lib->vba.MacroTileWidthY[k],
|
||||
&mode_lib->vba.MacroTileWidthC[k]);
|
||||
}
|
||||
|
||||
/*Bandwidth Support Check*/
|
||||
@ -2659,10 +2617,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
||||
mode_lib->vba.Read256BlockWidthC,
|
||||
mode_lib->vba.Read256BlockHeightY,
|
||||
mode_lib->vba.Read256BlockHeightC,
|
||||
mode_lib->vba.MicroTileWidthY,
|
||||
mode_lib->vba.MicroTileWidthC,
|
||||
mode_lib->vba.MicroTileHeightY,
|
||||
mode_lib->vba.MicroTileHeightC,
|
||||
mode_lib->vba.MacroTileWidthY,
|
||||
mode_lib->vba.MacroTileWidthC,
|
||||
mode_lib->vba.MacroTileHeightY,
|
||||
mode_lib->vba.MacroTileHeightC,
|
||||
|
||||
/* Output */
|
||||
mode_lib->vba.SurfaceSizeInMALL,
|
||||
@ -2709,10 +2667,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MicroTileWidthY[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MicroTileHeightY[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MicroTileWidthC[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MicroTileHeightC[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MacroTileWidthY[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MacroTileHeightY[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MacroTileWidthC[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MacroTileHeightC[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k];
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
|
||||
@ -3258,63 +3216,47 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
||||
|
||||
mode_lib->vba.NoTimeForPrefetch[i][j][k] =
|
||||
dml32_CalculatePrefetchSchedule(
|
||||
v,
|
||||
k,
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor,
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe,
|
||||
mode_lib->vba.DSCDelayPerState[i][k],
|
||||
mode_lib->vba.DPPCLKDelaySubtotal +
|
||||
mode_lib->vba.DPPCLKDelayCNVCFormater,
|
||||
mode_lib->vba.DPPCLKDelaySCL,
|
||||
mode_lib->vba.DPPCLKDelaySCLLBOnly,
|
||||
mode_lib->vba.DPPCLKDelayCNVCCursor,
|
||||
mode_lib->vba.DISPCLKDelaySubtotal,
|
||||
mode_lib->vba.SwathWidthYThisState[k] /
|
||||
mode_lib->vba.HRatio[k],
|
||||
mode_lib->vba.OutputFormat[k],
|
||||
mode_lib->vba.MaxInterDCNTileRepeaters,
|
||||
dml_min(mode_lib->vba.MaxVStartup,
|
||||
mode_lib->vba.MaximumVStartup[i][j][k]),
|
||||
mode_lib->vba.MaximumVStartup[i][j][k],
|
||||
mode_lib->vba.GPUVMMaxPageTableLevels,
|
||||
mode_lib->vba.GPUVMEnable, mode_lib->vba.HostVMEnable,
|
||||
mode_lib->vba.HostVMMaxNonCachedPageTableLevels,
|
||||
mode_lib->vba.HostVMMinPageSize,
|
||||
mode_lib->vba.DynamicMetadataEnable[k],
|
||||
mode_lib->vba.DynamicMetadataVMEnabled,
|
||||
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
|
||||
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
|
||||
mode_lib->vba.UrgLatency[i],
|
||||
mode_lib->vba.ExtraLatency,
|
||||
mode_lib->vba.TimeCalc,
|
||||
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k],
|
||||
mode_lib->vba.MetaRowBytes[i][j][k],
|
||||
mode_lib->vba.DPTEBytesPerRow[i][j][k],
|
||||
mode_lib->vba.PrefetchLinesY[i][j][k],
|
||||
mode_lib->vba.SwathWidthYThisState[k],
|
||||
mode_lib->vba.PrefillY[k],
|
||||
mode_lib->vba.MaxNumSwY[k],
|
||||
mode_lib->vba.PrefetchLinesC[i][j][k],
|
||||
mode_lib->vba.SwathWidthCThisState[k],
|
||||
mode_lib->vba.PrefillC[k],
|
||||
mode_lib->vba.MaxNumSwC[k],
|
||||
mode_lib->vba.swath_width_luma_ub_this_state[k],
|
||||
mode_lib->vba.swath_width_chroma_ub_this_state[k],
|
||||
mode_lib->vba.SwathHeightYThisState[k],
|
||||
mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.TWait,
|
||||
v->DSCDelayPerState[i][k],
|
||||
v->SwathWidthYThisState[k] / v->HRatio[k],
|
||||
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
|
||||
v->MaximumVStartup[i][j][k],
|
||||
v->UrgLatency[i],
|
||||
v->ExtraLatency,
|
||||
v->TimeCalc,
|
||||
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
|
||||
v->MetaRowBytes[i][j][k],
|
||||
v->DPTEBytesPerRow[i][j][k],
|
||||
v->PrefetchLinesY[i][j][k],
|
||||
v->SwathWidthYThisState[k],
|
||||
v->PrefillY[k],
|
||||
v->MaxNumSwY[k],
|
||||
v->PrefetchLinesC[i][j][k],
|
||||
v->SwathWidthCThisState[k],
|
||||
v->PrefillC[k],
|
||||
v->MaxNumSwC[k],
|
||||
v->swath_width_luma_ub_this_state[k],
|
||||
v->swath_width_chroma_ub_this_state[k],
|
||||
v->SwathHeightYThisState[k],
|
||||
v->SwathHeightCThisState[k], v->TWait,
|
||||
|
||||
/* Output */
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler[k],
|
||||
&mode_lib->vba.LineTimesForPrefetch[k],
|
||||
&mode_lib->vba.PrefetchBW[k],
|
||||
&mode_lib->vba.LinesForMetaPTE[k],
|
||||
&mode_lib->vba.LinesForMetaAndDPTERow[k],
|
||||
&mode_lib->vba.VRatioPreY[i][j][k],
|
||||
&mode_lib->vba.VRatioPreC[i][j][k],
|
||||
&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[0][0][k],
|
||||
&mode_lib->vba.RequiredPrefetchPixelDataBWChroma[0][0][k],
|
||||
&mode_lib->vba.NoTimeForDynamicMetadata[i][j][k],
|
||||
&mode_lib->vba.Tno_bw[k],
|
||||
&mode_lib->vba.prefetch_vmrow_bw[k],
|
||||
&v->LineTimesForPrefetch[k],
|
||||
&v->PrefetchBW[k],
|
||||
&v->LinesForMetaPTE[k],
|
||||
&v->LinesForMetaAndDPTERow[k],
|
||||
&v->VRatioPreY[i][j][k],
|
||||
&v->VRatioPreC[i][j][k],
|
||||
&v->RequiredPrefetchPixelDataBWLuma[0][0][k],
|
||||
&v->RequiredPrefetchPixelDataBWChroma[0][0][k],
|
||||
&v->NoTimeForDynamicMetadata[i][j][k],
|
||||
&v->Tno_bw[k],
|
||||
&v->prefetch_vmrow_bw[k],
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // double *Tdmdl_vm
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // double *Tdmdl
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[2], // double *TSetup
|
||||
@ -3557,62 +3499,32 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
||||
|
||||
{
|
||||
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
mode_lib->vba.USRRetrainingRequiredFinal,
|
||||
mode_lib->vba.UsesMALLForPStateChange,
|
||||
mode_lib->vba.PrefetchModePerState[i][j],
|
||||
mode_lib->vba.NumberOfActiveSurfaces,
|
||||
mode_lib->vba.MaxLineBufferLines,
|
||||
mode_lib->vba.LineBufferSizeFinal,
|
||||
mode_lib->vba.WritebackInterfaceBufferSize,
|
||||
mode_lib->vba.DCFCLKState[i][j],
|
||||
mode_lib->vba.ReturnBWPerState[i][j],
|
||||
mode_lib->vba.SynchronizeTimingsFinal,
|
||||
mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
|
||||
mode_lib->vba.DRRDisplay,
|
||||
mode_lib->vba.dpte_group_bytes,
|
||||
mode_lib->vba.meta_row_height,
|
||||
mode_lib->vba.meta_row_height_chroma,
|
||||
v,
|
||||
v->PrefetchModePerState[i][j],
|
||||
v->DCFCLKState[i][j],
|
||||
v->ReturnBWPerState[i][j],
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters,
|
||||
mode_lib->vba.WritebackChunkSize,
|
||||
mode_lib->vba.SOCCLKPerState[i],
|
||||
mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j],
|
||||
mode_lib->vba.DETBufferSizeYThisState,
|
||||
mode_lib->vba.DETBufferSizeCThisState,
|
||||
mode_lib->vba.SwathHeightYThisState,
|
||||
mode_lib->vba.SwathHeightCThisState,
|
||||
mode_lib->vba.LBBitPerPixel,
|
||||
mode_lib->vba.SwathWidthYThisState, // 24
|
||||
mode_lib->vba.SwathWidthCThisState,
|
||||
mode_lib->vba.HRatio,
|
||||
mode_lib->vba.HRatioChroma,
|
||||
mode_lib->vba.vtaps,
|
||||
mode_lib->vba.VTAPsChroma,
|
||||
mode_lib->vba.VRatio,
|
||||
mode_lib->vba.VRatioChroma,
|
||||
mode_lib->vba.HTotal,
|
||||
mode_lib->vba.VTotal,
|
||||
mode_lib->vba.VActive,
|
||||
mode_lib->vba.PixelClock,
|
||||
mode_lib->vba.BlendingAndTiming,
|
||||
mode_lib->vba.NoOfDPPThisState,
|
||||
mode_lib->vba.BytePerPixelInDETY,
|
||||
mode_lib->vba.BytePerPixelInDETC,
|
||||
v->SOCCLKPerState[i],
|
||||
v->ProjectedDCFCLKDeepSleep[i][j],
|
||||
v->DETBufferSizeYThisState,
|
||||
v->DETBufferSizeCThisState,
|
||||
v->SwathHeightYThisState,
|
||||
v->SwathHeightCThisState,
|
||||
v->SwathWidthYThisState, // 24
|
||||
v->SwathWidthCThisState,
|
||||
v->NoOfDPPThisState,
|
||||
v->BytePerPixelInDETY,
|
||||
v->BytePerPixelInDETC,
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler,
|
||||
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler,
|
||||
mode_lib->vba.WritebackEnable,
|
||||
mode_lib->vba.WritebackPixelFormat,
|
||||
mode_lib->vba.WritebackDestinationWidth,
|
||||
mode_lib->vba.WritebackDestinationHeight,
|
||||
mode_lib->vba.WritebackSourceHeight,
|
||||
mode_lib->vba.UnboundedRequestEnabledThisState,
|
||||
mode_lib->vba.CompressedBufferSizeInkByteThisState,
|
||||
v->UnboundedRequestEnabledThisState,
|
||||
v->CompressedBufferSizeInkByteThisState,
|
||||
|
||||
/* Output */
|
||||
&mode_lib->vba.Watermark, // Store the values in vba
|
||||
&mode_lib->vba.DRAMClockChangeSupport[i][j],
|
||||
&v->DRAMClockChangeSupport[i][j],
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[0], // double *MaxActiveDRAMClockChangeLatencySupported
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer[0], // Long SubViewportLinesNeededInMALL[]
|
||||
&mode_lib->vba.FCLKChangeSupport[i][j],
|
||||
&v->FCLKChangeSupport[i][j],
|
||||
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[1], // double *MinActiveFCLKChangeLatencySupported
|
||||
&mode_lib->vba.USRRetrainingSupport[i][j],
|
||||
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin);
|
||||
|
||||
@ -3363,28 +3363,14 @@ double dml32_CalculateExtraLatency(
|
||||
} // CalculateExtraLatency
|
||||
|
||||
bool dml32_CalculatePrefetchSchedule(
|
||||
struct vba_vars_st *v,
|
||||
unsigned int k,
|
||||
double HostVMInefficiencyFactor,
|
||||
DmlPipe *myPipe,
|
||||
unsigned int DSCDelay,
|
||||
double DPPCLKDelaySubtotalPlusCNVCFormater,
|
||||
double DPPCLKDelaySCL,
|
||||
double DPPCLKDelaySCLLBOnly,
|
||||
double DPPCLKDelayCNVCCursor,
|
||||
double DISPCLKDelaySubtotal,
|
||||
unsigned int DPP_RECOUT_WIDTH,
|
||||
enum output_format_class OutputFormat,
|
||||
unsigned int MaxInterDCNTileRepeaters,
|
||||
unsigned int VStartup,
|
||||
unsigned int MaxVStartup,
|
||||
unsigned int GPUVMPageTableLevels,
|
||||
bool GPUVMEnable,
|
||||
bool HostVMEnable,
|
||||
unsigned int HostVMMaxNonCachedPageTableLevels,
|
||||
double HostVMMinPageSize,
|
||||
bool DynamicMetadataEnable,
|
||||
bool DynamicMetadataVMEnabled,
|
||||
int DynamicMetadataLinesBeforeActiveRequired,
|
||||
unsigned int DynamicMetadataTransmittedBytes,
|
||||
double UrgentLatency,
|
||||
double UrgentExtraLatency,
|
||||
double TCalc,
|
||||
@ -3425,6 +3411,7 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
double *VUpdateWidthPix,
|
||||
double *VReadyOffsetPix)
|
||||
{
|
||||
double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater;
|
||||
bool MyError = false;
|
||||
unsigned int DPPCycles, DISPCLKCycles;
|
||||
double DSTTotalPixelsAfterScaler;
|
||||
@ -3461,27 +3448,27 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
double Tsw_est1 = 0;
|
||||
double Tsw_est3 = 0;
|
||||
|
||||
if (GPUVMEnable == true && HostVMEnable == true)
|
||||
HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
|
||||
if (v->GPUVMEnable == true && v->HostVMEnable == true)
|
||||
HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
|
||||
else
|
||||
HostVMDynamicLevelsTrips = 0;
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: GPUVMEnable = %d\n", __func__, GPUVMEnable);
|
||||
dml_print("DML::%s: GPUVMPageTableLevels = %d\n", __func__, GPUVMPageTableLevels);
|
||||
dml_print("DML::%s: v->GPUVMEnable = %d\n", __func__, v->GPUVMEnable);
|
||||
dml_print("DML::%s: v->GPUVMMaxPageTableLevels = %d\n", __func__, v->GPUVMMaxPageTableLevels);
|
||||
dml_print("DML::%s: DCCEnable = %d\n", __func__, myPipe->DCCEnable);
|
||||
dml_print("DML::%s: HostVMEnable=%d HostVMInefficiencyFactor=%f\n",
|
||||
__func__, HostVMEnable, HostVMInefficiencyFactor);
|
||||
dml_print("DML::%s: v->HostVMEnable=%d HostVMInefficiencyFactor=%f\n",
|
||||
__func__, v->HostVMEnable, HostVMInefficiencyFactor);
|
||||
#endif
|
||||
dml32_CalculateVUpdateAndDynamicMetadataParameters(
|
||||
MaxInterDCNTileRepeaters,
|
||||
v->MaxInterDCNTileRepeaters,
|
||||
myPipe->Dppclk,
|
||||
myPipe->Dispclk,
|
||||
myPipe->DCFClkDeepSleep,
|
||||
myPipe->PixelClock,
|
||||
myPipe->HTotal,
|
||||
myPipe->VBlank,
|
||||
DynamicMetadataTransmittedBytes,
|
||||
DynamicMetadataLinesBeforeActiveRequired,
|
||||
v->DynamicMetadataTransmittedBytes[k],
|
||||
v->DynamicMetadataLinesBeforeActiveRequired[k],
|
||||
myPipe->InterlaceEnable,
|
||||
myPipe->ProgressiveToInterlaceUnitInOPP,
|
||||
TSetup,
|
||||
@ -3496,19 +3483,19 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
|
||||
LineTime = myPipe->HTotal / myPipe->PixelClock;
|
||||
trip_to_mem = UrgentLatency;
|
||||
Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
|
||||
Tvm_trips = UrgentExtraLatency + trip_to_mem * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
|
||||
|
||||
if (DynamicMetadataVMEnabled == true)
|
||||
if (v->DynamicMetadataVMEnabled == true)
|
||||
*Tdmdl = TWait + Tvm_trips + trip_to_mem;
|
||||
else
|
||||
*Tdmdl = TWait + UrgentExtraLatency;
|
||||
|
||||
#ifdef __DML_VBA_ALLOW_DELTA__
|
||||
if (DynamicMetadataEnable == false)
|
||||
if (v->DynamicMetadataEnable[k] == false)
|
||||
*Tdmdl = 0.0;
|
||||
#endif
|
||||
|
||||
if (DynamicMetadataEnable == true) {
|
||||
if (v->DynamicMetadataEnable[k] == true) {
|
||||
if (VStartup * LineTime < *TSetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) {
|
||||
*NotEnoughTimeForDynamicMetadata = true;
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
@ -3528,17 +3515,17 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
*NotEnoughTimeForDynamicMetadata = false;
|
||||
}
|
||||
|
||||
*Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true &&
|
||||
GPUVMEnable == true ? TWait + Tvm_trips : 0);
|
||||
*Tdmdl_vm = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true &&
|
||||
v->GPUVMEnable == true ? TWait + Tvm_trips : 0);
|
||||
|
||||
if (myPipe->ScalerEnabled)
|
||||
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL;
|
||||
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL;
|
||||
else
|
||||
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly;
|
||||
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly;
|
||||
|
||||
DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor;
|
||||
DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor;
|
||||
|
||||
DISPCLKCycles = DISPCLKDelaySubtotal;
|
||||
DISPCLKCycles = v->DISPCLKDelaySubtotal;
|
||||
|
||||
if (myPipe->Dppclk == 0.0 || myPipe->Dispclk == 0.0)
|
||||
return true;
|
||||
@ -3564,7 +3551,7 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
dml_print("DML::%s: DSTXAfterScaler: %d\n", __func__, *DSTXAfterScaler);
|
||||
#endif
|
||||
|
||||
if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
|
||||
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
|
||||
*DSTYAfterScaler = 1;
|
||||
else
|
||||
*DSTYAfterScaler = 0;
|
||||
@ -3581,13 +3568,13 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
|
||||
Tr0_trips = trip_to_mem * (HostVMDynamicLevelsTrips + 1);
|
||||
|
||||
if (GPUVMEnable == true) {
|
||||
if (v->GPUVMEnable == true) {
|
||||
Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1.0) / 4.0 * LineTime;
|
||||
Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1.0) / 4.0 * LineTime;
|
||||
if (GPUVMPageTableLevels >= 3) {
|
||||
if (v->GPUVMMaxPageTableLevels >= 3) {
|
||||
*Tno_bw = UrgentExtraLatency + trip_to_mem *
|
||||
(double) ((GPUVMPageTableLevels - 2) * (HostVMDynamicLevelsTrips + 1) - 1);
|
||||
} else if (GPUVMPageTableLevels == 1 && myPipe->DCCEnable != true) {
|
||||
(double) ((v->GPUVMMaxPageTableLevels - 2) * (HostVMDynamicLevelsTrips + 1) - 1);
|
||||
} else if (v->GPUVMMaxPageTableLevels == 1 && myPipe->DCCEnable != true) {
|
||||
Tr0_trips_rounded = dml_ceil(4.0 * UrgentExtraLatency / LineTime, 1.0) /
|
||||
4.0 * LineTime; // VBA_ERROR
|
||||
*Tno_bw = UrgentExtraLatency;
|
||||
@ -3622,7 +3609,7 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
min_Lsw = dml_max(min_Lsw, 1.0);
|
||||
Lsw_oto = dml_ceil(4.0 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1.0) / 4.0;
|
||||
|
||||
if (GPUVMEnable == true) {
|
||||
if (v->GPUVMEnable == true) {
|
||||
Tvm_oto = dml_max3(
|
||||
Tvm_trips,
|
||||
*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
|
||||
@ -3630,7 +3617,7 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
} else
|
||||
Tvm_oto = LineTime / 4.0;
|
||||
|
||||
if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
|
||||
if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {
|
||||
Tr0_oto = dml_max4(
|
||||
Tr0_trips,
|
||||
(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto,
|
||||
@ -3833,7 +3820,7 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
#endif
|
||||
|
||||
if (prefetch_bw_equ > 0) {
|
||||
if (GPUVMEnable == true) {
|
||||
if (v->GPUVMEnable == true) {
|
||||
Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame *
|
||||
HostVMInefficiencyFactor / prefetch_bw_equ,
|
||||
Tvm_trips, LineTime / 4);
|
||||
@ -3841,7 +3828,7 @@ bool dml32_CalculatePrefetchSchedule(
|
||||
Tvm_equ = LineTime / 4;
|
||||
}
|
||||
|
||||
if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
|
||||
if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {
|
||||
Tr0_equ = dml_max4((MetaRowByte + PixelPTEBytesPerRow *
|
||||
HostVMInefficiencyFactor) / prefetch_bw_equ, Tr0_trips,
|
||||
(LineTime - Tvm_equ) / 2, LineTime / 4);
|
||||
@ -4206,58 +4193,28 @@ void dml32_CalculateFlipSchedule(
|
||||
} // CalculateFlipSchedule
|
||||
|
||||
void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
bool USRRetrainingRequiredFinal,
|
||||
enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
|
||||
struct vba_vars_st *v,
|
||||
unsigned int PrefetchMode,
|
||||
unsigned int NumberOfActiveSurfaces,
|
||||
unsigned int MaxLineBufferLines,
|
||||
unsigned int LineBufferSize,
|
||||
unsigned int WritebackInterfaceBufferSize,
|
||||
double DCFCLK,
|
||||
double ReturnBW,
|
||||
bool SynchronizeTimingsFinal,
|
||||
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
|
||||
bool DRRDisplay[],
|
||||
unsigned int dpte_group_bytes[],
|
||||
unsigned int meta_row_height[],
|
||||
unsigned int meta_row_height_chroma[],
|
||||
SOCParametersList mmSOCParameters,
|
||||
unsigned int WritebackChunkSize,
|
||||
double SOCCLK,
|
||||
double DCFClkDeepSleep,
|
||||
unsigned int DETBufferSizeY[],
|
||||
unsigned int DETBufferSizeC[],
|
||||
unsigned int SwathHeightY[],
|
||||
unsigned int SwathHeightC[],
|
||||
unsigned int LBBitPerPixel[],
|
||||
double SwathWidthY[],
|
||||
double SwathWidthC[],
|
||||
double HRatio[],
|
||||
double HRatioChroma[],
|
||||
unsigned int VTaps[],
|
||||
unsigned int VTapsChroma[],
|
||||
double VRatio[],
|
||||
double VRatioChroma[],
|
||||
unsigned int HTotal[],
|
||||
unsigned int VTotal[],
|
||||
unsigned int VActive[],
|
||||
double PixelClock[],
|
||||
unsigned int BlendingAndTiming[],
|
||||
unsigned int DPPPerSurface[],
|
||||
double BytePerPixelDETY[],
|
||||
double BytePerPixelDETC[],
|
||||
double DSTXAfterScaler[],
|
||||
double DSTYAfterScaler[],
|
||||
bool WritebackEnable[],
|
||||
enum source_format_class WritebackPixelFormat[],
|
||||
double WritebackDestinationWidth[],
|
||||
double WritebackDestinationHeight[],
|
||||
double WritebackSourceHeight[],
|
||||
bool UnboundedRequestEnabled,
|
||||
unsigned int CompressedBufferSizeInkByte,
|
||||
|
||||
/* Output */
|
||||
Watermarks *Watermark,
|
||||
enum clock_change_support *DRAMClockChangeSupport,
|
||||
double MaxActiveDRAMClockChangeLatencySupported[],
|
||||
unsigned int SubViewportLinesNeededInMALL[],
|
||||
@ -4299,136 +4256,136 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
unsigned int LBLatencyHidingSourceLinesY[DC__NUM_DPP__MAX];
|
||||
unsigned int LBLatencyHidingSourceLinesC[DC__NUM_DPP__MAX];
|
||||
|
||||
Watermark->UrgentWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency;
|
||||
Watermark->USRRetrainingWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency
|
||||
v->Watermark.UrgentWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency;
|
||||
v->Watermark.USRRetrainingWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency
|
||||
+ mmSOCParameters.USRRetrainingLatency + mmSOCParameters.SMNLatency;
|
||||
Watermark->DRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + Watermark->UrgentWatermark;
|
||||
Watermark->FCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + Watermark->UrgentWatermark;
|
||||
Watermark->StutterExitWatermark = mmSOCParameters.SRExitTime + mmSOCParameters.ExtraLatency
|
||||
v->Watermark.DRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + v->Watermark.UrgentWatermark;
|
||||
v->Watermark.FCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + v->Watermark.UrgentWatermark;
|
||||
v->Watermark.StutterExitWatermark = mmSOCParameters.SRExitTime + mmSOCParameters.ExtraLatency
|
||||
+ 10 / DCFClkDeepSleep;
|
||||
Watermark->StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitTime + mmSOCParameters.ExtraLatency
|
||||
v->Watermark.StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitTime + mmSOCParameters.ExtraLatency
|
||||
+ 10 / DCFClkDeepSleep;
|
||||
Watermark->Z8StutterExitWatermark = mmSOCParameters.SRExitZ8Time + mmSOCParameters.ExtraLatency
|
||||
v->Watermark.Z8StutterExitWatermark = mmSOCParameters.SRExitZ8Time + mmSOCParameters.ExtraLatency
|
||||
+ 10 / DCFClkDeepSleep;
|
||||
Watermark->Z8StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitZ8Time
|
||||
v->Watermark.Z8StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitZ8Time
|
||||
+ mmSOCParameters.ExtraLatency + 10 / DCFClkDeepSleep;
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: UrgentLatency = %f\n", __func__, mmSOCParameters.UrgentLatency);
|
||||
dml_print("DML::%s: ExtraLatency = %f\n", __func__, mmSOCParameters.ExtraLatency);
|
||||
dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, mmSOCParameters.DRAMClockChangeLatency);
|
||||
dml_print("DML::%s: UrgentWatermark = %f\n", __func__, Watermark->UrgentWatermark);
|
||||
dml_print("DML::%s: USRRetrainingWatermark = %f\n", __func__, Watermark->USRRetrainingWatermark);
|
||||
dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, Watermark->DRAMClockChangeWatermark);
|
||||
dml_print("DML::%s: FCLKChangeWatermark = %f\n", __func__, Watermark->FCLKChangeWatermark);
|
||||
dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, Watermark->StutterExitWatermark);
|
||||
dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, Watermark->StutterEnterPlusExitWatermark);
|
||||
dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, Watermark->Z8StutterExitWatermark);
|
||||
dml_print("DML::%s: UrgentWatermark = %f\n", __func__, v->Watermark.UrgentWatermark);
|
||||
dml_print("DML::%s: USRRetrainingWatermark = %f\n", __func__, v->Watermark.USRRetrainingWatermark);
|
||||
dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, v->Watermark.DRAMClockChangeWatermark);
|
||||
dml_print("DML::%s: FCLKChangeWatermark = %f\n", __func__, v->Watermark.FCLKChangeWatermark);
|
||||
dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, v->Watermark.StutterExitWatermark);
|
||||
dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, v->Watermark.StutterEnterPlusExitWatermark);
|
||||
dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, v->Watermark.Z8StutterExitWatermark);
|
||||
dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n",
|
||||
__func__, Watermark->Z8StutterEnterPlusExitWatermark);
|
||||
__func__, v->Watermark.Z8StutterEnterPlusExitWatermark);
|
||||
#endif
|
||||
|
||||
|
||||
TotalActiveWriteback = 0;
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
if (WritebackEnable[k] == true)
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
if (v->WritebackEnable[k] == true)
|
||||
TotalActiveWriteback = TotalActiveWriteback + 1;
|
||||
}
|
||||
|
||||
if (TotalActiveWriteback <= 1) {
|
||||
Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency;
|
||||
v->Watermark.WritebackUrgentWatermark = mmSOCParameters.WritebackLatency;
|
||||
} else {
|
||||
Watermark->WritebackUrgentWatermark = mmSOCParameters.WritebackLatency
|
||||
+ WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
v->Watermark.WritebackUrgentWatermark = mmSOCParameters.WritebackLatency
|
||||
+ v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
}
|
||||
if (USRRetrainingRequiredFinal)
|
||||
Watermark->WritebackUrgentWatermark = Watermark->WritebackUrgentWatermark
|
||||
if (v->USRRetrainingRequiredFinal)
|
||||
v->Watermark.WritebackUrgentWatermark = v->Watermark.WritebackUrgentWatermark
|
||||
+ mmSOCParameters.USRRetrainingLatency;
|
||||
|
||||
if (TotalActiveWriteback <= 1) {
|
||||
Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
|
||||
v->Watermark.WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
|
||||
+ mmSOCParameters.WritebackLatency;
|
||||
Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
|
||||
v->Watermark.WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
|
||||
+ mmSOCParameters.WritebackLatency;
|
||||
} else {
|
||||
Watermark->WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
|
||||
+ mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
Watermark->WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
|
||||
+ mmSOCParameters.WritebackLatency + WritebackChunkSize * 1024 / 32 / SOCCLK;
|
||||
v->Watermark.WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
|
||||
+ mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
|
||||
v->Watermark.WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
|
||||
+ mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024 / 32 / SOCCLK;
|
||||
}
|
||||
|
||||
if (USRRetrainingRequiredFinal)
|
||||
Watermark->WritebackDRAMClockChangeWatermark = Watermark->WritebackDRAMClockChangeWatermark
|
||||
if (v->USRRetrainingRequiredFinal)
|
||||
v->Watermark.WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark
|
||||
+ mmSOCParameters.USRRetrainingLatency;
|
||||
|
||||
if (USRRetrainingRequiredFinal)
|
||||
Watermark->WritebackFCLKChangeWatermark = Watermark->WritebackFCLKChangeWatermark
|
||||
if (v->USRRetrainingRequiredFinal)
|
||||
v->Watermark.WritebackFCLKChangeWatermark = v->Watermark.WritebackFCLKChangeWatermark
|
||||
+ mmSOCParameters.USRRetrainingLatency;
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: WritebackDRAMClockChangeWatermark = %f\n",
|
||||
__func__, Watermark->WritebackDRAMClockChangeWatermark);
|
||||
dml_print("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, Watermark->WritebackFCLKChangeWatermark);
|
||||
dml_print("DML::%s: WritebackUrgentWatermark = %f\n", __func__, Watermark->WritebackUrgentWatermark);
|
||||
dml_print("DML::%s: USRRetrainingRequiredFinal = %d\n", __func__, USRRetrainingRequiredFinal);
|
||||
__func__, v->Watermark.WritebackDRAMClockChangeWatermark);
|
||||
dml_print("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, v->Watermark.WritebackFCLKChangeWatermark);
|
||||
dml_print("DML::%s: WritebackUrgentWatermark = %f\n", __func__, v->Watermark.WritebackUrgentWatermark);
|
||||
dml_print("DML::%s: v->USRRetrainingRequiredFinal = %d\n", __func__, v->USRRetrainingRequiredFinal);
|
||||
dml_print("DML::%s: USRRetrainingLatency = %f\n", __func__, mmSOCParameters.USRRetrainingLatency);
|
||||
#endif
|
||||
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] +
|
||||
SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k]) / (HTotal[k] / PixelClock[k]);
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] +
|
||||
SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k]) / (v->HTotal[k] / v->PixelClock[k]);
|
||||
}
|
||||
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
|
||||
LBLatencyHidingSourceLinesY[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (VTaps[k] - 1);
|
||||
LBLatencyHidingSourceLinesC[k] = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTapsChroma[k] - 1);
|
||||
LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
|
||||
LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
|
||||
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: k=%d, MaxLineBufferLines = %d\n", __func__, k, MaxLineBufferLines);
|
||||
dml_print("DML::%s: k=%d, LineBufferSize = %d\n", __func__, k, LineBufferSize);
|
||||
dml_print("DML::%s: k=%d, LBBitPerPixel = %d\n", __func__, k, LBBitPerPixel[k]);
|
||||
dml_print("DML::%s: k=%d, HRatio = %f\n", __func__, k, HRatio[k]);
|
||||
dml_print("DML::%s: k=%d, VTaps = %d\n", __func__, k, VTaps[k]);
|
||||
dml_print("DML::%s: k=%d, v->MaxLineBufferLines = %d\n", __func__, k, v->MaxLineBufferLines);
|
||||
dml_print("DML::%s: k=%d, v->LineBufferSizeFinal = %d\n", __func__, k, v->LineBufferSizeFinal);
|
||||
dml_print("DML::%s: k=%d, v->LBBitPerPixel = %d\n", __func__, k, v->LBBitPerPixel[k]);
|
||||
dml_print("DML::%s: k=%d, v->HRatio = %f\n", __func__, k, v->HRatio[k]);
|
||||
dml_print("DML::%s: k=%d, v->vtaps = %d\n", __func__, k, v->vtaps[k]);
|
||||
#endif
|
||||
|
||||
EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / VRatio[k] * (HTotal[k] / PixelClock[k]);
|
||||
EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / VRatioChroma[k] * (HTotal[k] / PixelClock[k]);
|
||||
EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
|
||||
EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
|
||||
EffectiveDETBufferSizeY = DETBufferSizeY[k];
|
||||
|
||||
if (UnboundedRequestEnabled) {
|
||||
EffectiveDETBufferSizeY = EffectiveDETBufferSizeY
|
||||
+ CompressedBufferSizeInkByte * 1024
|
||||
* (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k])
|
||||
/ (HTotal[k] / PixelClock[k]) / TotalPixelBW;
|
||||
* (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k])
|
||||
/ (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
|
||||
}
|
||||
|
||||
LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
|
||||
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
|
||||
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
|
||||
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
|
||||
|
||||
ActiveClockChangeLatencyHidingY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY
|
||||
- (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k];
|
||||
- (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k];
|
||||
|
||||
if (NumberOfActiveSurfaces > 1) {
|
||||
if (v->NumberOfActiveSurfaces > 1) {
|
||||
ActiveClockChangeLatencyHidingY = ActiveClockChangeLatencyHidingY
|
||||
- (1 - 1 / NumberOfActiveSurfaces) * SwathHeightY[k] * HTotal[k]
|
||||
/ PixelClock[k] / VRatio[k];
|
||||
- (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
|
||||
/ v->PixelClock[k] / v->VRatio[k];
|
||||
}
|
||||
|
||||
if (BytePerPixelDETC[k] > 0) {
|
||||
LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
|
||||
LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]);
|
||||
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k])
|
||||
/ VRatioChroma[k];
|
||||
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k])
|
||||
/ v->VRatioChroma[k];
|
||||
ActiveClockChangeLatencyHidingC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC
|
||||
- (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k]
|
||||
/ PixelClock[k];
|
||||
if (NumberOfActiveSurfaces > 1) {
|
||||
- (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k]
|
||||
/ v->PixelClock[k];
|
||||
if (v->NumberOfActiveSurfaces > 1) {
|
||||
ActiveClockChangeLatencyHidingC = ActiveClockChangeLatencyHidingC
|
||||
- (1 - 1 / NumberOfActiveSurfaces) * SwathHeightC[k] * HTotal[k]
|
||||
/ PixelClock[k] / VRatioChroma[k];
|
||||
- (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightC[k] * v->HTotal[k]
|
||||
/ v->PixelClock[k] / v->VRatioChroma[k];
|
||||
}
|
||||
ActiveClockChangeLatencyHiding = dml_min(ActiveClockChangeLatencyHidingY,
|
||||
ActiveClockChangeLatencyHidingC);
|
||||
@ -4436,24 +4393,24 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
ActiveClockChangeLatencyHiding = ActiveClockChangeLatencyHidingY;
|
||||
}
|
||||
|
||||
ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark
|
||||
- Watermark->DRAMClockChangeWatermark;
|
||||
ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->UrgentWatermark
|
||||
- Watermark->FCLKChangeWatermark;
|
||||
USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - Watermark->USRRetrainingWatermark;
|
||||
ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark
|
||||
- v->Watermark.DRAMClockChangeWatermark;
|
||||
ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark
|
||||
- v->Watermark.FCLKChangeWatermark;
|
||||
USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.USRRetrainingWatermark;
|
||||
|
||||
if (WritebackEnable[k]) {
|
||||
WritebackLatencyHiding = WritebackInterfaceBufferSize * 1024
|
||||
/ (WritebackDestinationWidth[k] * WritebackDestinationHeight[k]
|
||||
/ (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4);
|
||||
if (WritebackPixelFormat[k] == dm_444_64)
|
||||
if (v->WritebackEnable[k]) {
|
||||
WritebackLatencyHiding = v->WritebackInterfaceBufferSize * 1024
|
||||
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
|
||||
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
|
||||
if (v->WritebackPixelFormat[k] == dm_444_64)
|
||||
WritebackLatencyHiding = WritebackLatencyHiding / 2;
|
||||
|
||||
WritebackDRAMClockChangeLatencyMargin = WritebackLatencyHiding
|
||||
- Watermark->WritebackDRAMClockChangeWatermark;
|
||||
- v->Watermark.WritebackDRAMClockChangeWatermark;
|
||||
|
||||
WritebackFCLKChangeLatencyMargin = WritebackLatencyHiding
|
||||
- Watermark->WritebackFCLKChangeWatermark;
|
||||
- v->Watermark.WritebackFCLKChangeWatermark;
|
||||
|
||||
ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMargin[k],
|
||||
WritebackFCLKChangeLatencyMargin);
|
||||
@ -4461,22 +4418,22 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
WritebackDRAMClockChangeLatencyMargin);
|
||||
}
|
||||
MaxActiveDRAMClockChangeLatencySupported[k] =
|
||||
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ?
|
||||
(v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ?
|
||||
0 :
|
||||
(ActiveDRAMClockChangeLatencyMargin[k]
|
||||
+ mmSOCParameters.DRAMClockChangeLatency);
|
||||
}
|
||||
|
||||
for (i = 0; i < NumberOfActiveSurfaces; ++i) {
|
||||
for (j = 0; j < NumberOfActiveSurfaces; ++j) {
|
||||
for (i = 0; i < v->NumberOfActiveSurfaces; ++i) {
|
||||
for (j = 0; j < v->NumberOfActiveSurfaces; ++j) {
|
||||
if (i == j ||
|
||||
(BlendingAndTiming[i] == i && BlendingAndTiming[j] == i) ||
|
||||
(BlendingAndTiming[j] == j && BlendingAndTiming[i] == j) ||
|
||||
(BlendingAndTiming[i] == BlendingAndTiming[j] && BlendingAndTiming[i] != i) ||
|
||||
(SynchronizeTimingsFinal && PixelClock[i] == PixelClock[j] &&
|
||||
HTotal[i] == HTotal[j] && VTotal[i] == VTotal[j] &&
|
||||
VActive[i] == VActive[j]) || (SynchronizeDRRDisplaysForUCLKPStateChangeFinal &&
|
||||
(DRRDisplay[i] || DRRDisplay[j]))) {
|
||||
(v->BlendingAndTiming[i] == i && v->BlendingAndTiming[j] == i) ||
|
||||
(v->BlendingAndTiming[j] == j && v->BlendingAndTiming[i] == j) ||
|
||||
(v->BlendingAndTiming[i] == v->BlendingAndTiming[j] && v->BlendingAndTiming[i] != i) ||
|
||||
(v->SynchronizeTimingsFinal && v->PixelClock[i] == v->PixelClock[j] &&
|
||||
v->HTotal[i] == v->HTotal[j] && v->VTotal[i] == v->VTotal[j] &&
|
||||
v->VActive[i] == v->VActive[j]) || (v->SynchronizeDRRDisplaysForUCLKPStateChangeFinal &&
|
||||
(v->DRRDisplay[i] || v->DRRDisplay[j]))) {
|
||||
SynchronizedSurfaces[i][j] = true;
|
||||
} else {
|
||||
SynchronizedSurfaces[i][j] = false;
|
||||
@ -4484,8 +4441,8 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
}
|
||||
}
|
||||
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
|
||||
(!FoundFirstSurfaceWithMinActiveFCLKChangeMargin ||
|
||||
ActiveFCLKChangeLatencyMargin[k] < MinActiveFCLKChangeMargin)) {
|
||||
FoundFirstSurfaceWithMinActiveFCLKChangeMargin = true;
|
||||
@ -4497,9 +4454,9 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
*MinActiveFCLKChangeLatencySupported = MinActiveFCLKChangeMargin + mmSOCParameters.FCLKChangeLatency;
|
||||
|
||||
SameTimingForFCLKChange = true;
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
if (!SynchronizedSurfaces[k][SurfaceWithMinActiveFCLKChangeMargin]) {
|
||||
if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
|
||||
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
|
||||
(SameTimingForFCLKChange ||
|
||||
ActiveFCLKChangeLatencyMargin[k] <
|
||||
SecondMinActiveFCLKChangeMarginOneDisplayInVBLank)) {
|
||||
@ -4519,17 +4476,17 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
}
|
||||
|
||||
*USRRetrainingSupport = true;
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
if ((UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
|
||||
(USRRetrainingLatencyMargin[k] < 0)) {
|
||||
*USRRetrainingSupport = false;
|
||||
}
|
||||
}
|
||||
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame &&
|
||||
UseMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport &&
|
||||
UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe &&
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
if (v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame &&
|
||||
v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport &&
|
||||
v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe &&
|
||||
ActiveDRAMClockChangeLatencyMargin[k] < 0) {
|
||||
if (PrefetchMode > 0) {
|
||||
DRAMClockChangeSupportNumber = 2;
|
||||
@ -4543,10 +4500,10 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
}
|
||||
}
|
||||
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
|
||||
DRAMClockChangeMethod = 1;
|
||||
else if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
|
||||
else if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
|
||||
DRAMClockChangeMethod = 2;
|
||||
}
|
||||
|
||||
@ -4573,16 +4530,16 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
|
||||
}
|
||||
|
||||
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
|
||||
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
|
||||
unsigned int dst_y_pstate;
|
||||
unsigned int src_y_pstate_l;
|
||||
unsigned int src_y_pstate_c;
|
||||
unsigned int src_y_ahead_l, src_y_ahead_c, sub_vp_lines_l, sub_vp_lines_c;
|
||||
|
||||
dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (HTotal[k] / PixelClock[k]), 1);
|
||||
src_y_pstate_l = dml_ceil(dst_y_pstate * VRatio[k], SwathHeightY[k]);
|
||||
dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1);
|
||||
src_y_pstate_l = dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]);
|
||||
src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k];
|
||||
sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + meta_row_height[k];
|
||||
sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + v->meta_row_height[k];
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: k=%d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
|
||||
@ -4593,21 +4550,21 @@ dml_print("DML::%s: k=%d, LBLatencyHidingSourceLinesY = %d\n", __func__, k, LBL
|
||||
dml_print("DML::%s: k=%d, dst_y_pstate = %d\n", __func__, k, dst_y_pstate);
|
||||
dml_print("DML::%s: k=%d, src_y_pstate_l = %d\n", __func__, k, src_y_pstate_l);
|
||||
dml_print("DML::%s: k=%d, src_y_ahead_l = %d\n", __func__, k, src_y_ahead_l);
|
||||
dml_print("DML::%s: k=%d, meta_row_height = %d\n", __func__, k, meta_row_height[k]);
|
||||
dml_print("DML::%s: k=%d, v->meta_row_height = %d\n", __func__, k, v->meta_row_height[k]);
|
||||
dml_print("DML::%s: k=%d, sub_vp_lines_l = %d\n", __func__, k, sub_vp_lines_l);
|
||||
#endif
|
||||
SubViewportLinesNeededInMALL[k] = sub_vp_lines_l;
|
||||
|
||||
if (BytePerPixelDETC[k] > 0) {
|
||||
src_y_pstate_c = dml_ceil(dst_y_pstate * VRatioChroma[k], SwathHeightC[k]);
|
||||
src_y_pstate_c = dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]);
|
||||
src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k];
|
||||
sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + meta_row_height_chroma[k];
|
||||
sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + v->meta_row_height_chroma[k];
|
||||
SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c);
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: k=%d, src_y_pstate_c = %d\n", __func__, k, src_y_pstate_c);
|
||||
dml_print("DML::%s: k=%d, src_y_ahead_c = %d\n", __func__, k, src_y_ahead_c);
|
||||
dml_print("DML::%s: k=%d, meta_row_height_chroma = %d\n", __func__, k, meta_row_height_chroma[k]);
|
||||
dml_print("DML::%s: k=%d, v->meta_row_height_chroma = %d\n", __func__, k, v->meta_row_height_chroma[k]);
|
||||
dml_print("DML::%s: k=%d, sub_vp_lines_c = %d\n", __func__, k, sub_vp_lines_c);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -30,6 +30,7 @@
|
||||
#include "os_types.h"
|
||||
#include "../dc_features.h"
|
||||
#include "../display_mode_structs.h"
|
||||
#include "dml/display_mode_vba.h"
|
||||
|
||||
unsigned int dml32_dscceComputeDelay(
|
||||
unsigned int bpc,
|
||||
@ -712,28 +713,14 @@ double dml32_CalculateExtraLatency(
|
||||
unsigned int HostVMMaxNonCachedPageTableLevels);
|
||||
|
||||
bool dml32_CalculatePrefetchSchedule(
|
||||
struct vba_vars_st *v,
|
||||
unsigned int k,
|
||||
double HostVMInefficiencyFactor,
|
||||
DmlPipe *myPipe,
|
||||
unsigned int DSCDelay,
|
||||
double DPPCLKDelaySubtotalPlusCNVCFormater,
|
||||
double DPPCLKDelaySCL,
|
||||
double DPPCLKDelaySCLLBOnly,
|
||||
double DPPCLKDelayCNVCCursor,
|
||||
double DISPCLKDelaySubtotal,
|
||||
unsigned int DPP_RECOUT_WIDTH,
|
||||
enum output_format_class OutputFormat,
|
||||
unsigned int MaxInterDCNTileRepeaters,
|
||||
unsigned int VStartup,
|
||||
unsigned int MaxVStartup,
|
||||
unsigned int GPUVMPageTableLevels,
|
||||
bool GPUVMEnable,
|
||||
bool HostVMEnable,
|
||||
unsigned int HostVMMaxNonCachedPageTableLevels,
|
||||
double HostVMMinPageSize,
|
||||
bool DynamicMetadataEnable,
|
||||
bool DynamicMetadataVMEnabled,
|
||||
int DynamicMetadataLinesBeforeActiveRequired,
|
||||
unsigned int DynamicMetadataTransmittedBytes,
|
||||
double UrgentLatency,
|
||||
double UrgentExtraLatency,
|
||||
double TCalc,
|
||||
@ -807,58 +794,28 @@ void dml32_CalculateFlipSchedule(
|
||||
bool *ImmediateFlipSupportedForPipe);
|
||||
|
||||
void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
|
||||
bool USRRetrainingRequiredFinal,
|
||||
enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[],
|
||||
struct vba_vars_st *v,
|
||||
unsigned int PrefetchMode,
|
||||
unsigned int NumberOfActiveSurfaces,
|
||||
unsigned int MaxLineBufferLines,
|
||||
unsigned int LineBufferSize,
|
||||
unsigned int WritebackInterfaceBufferSize,
|
||||
double DCFCLK,
|
||||
double ReturnBW,
|
||||
bool SynchronizeTimingsFinal,
|
||||
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
|
||||
bool DRRDisplay[],
|
||||
unsigned int dpte_group_bytes[],
|
||||
unsigned int meta_row_height[],
|
||||
unsigned int meta_row_height_chroma[],
|
||||
SOCParametersList mmSOCParameters,
|
||||
unsigned int WritebackChunkSize,
|
||||
double SOCCLK,
|
||||
double DCFClkDeepSleep,
|
||||
unsigned int DETBufferSizeY[],
|
||||
unsigned int DETBufferSizeC[],
|
||||
unsigned int SwathHeightY[],
|
||||
unsigned int SwathHeightC[],
|
||||
unsigned int LBBitPerPixel[],
|
||||
double SwathWidthY[],
|
||||
double SwathWidthC[],
|
||||
double HRatio[],
|
||||
double HRatioChroma[],
|
||||
unsigned int VTaps[],
|
||||
unsigned int VTapsChroma[],
|
||||
double VRatio[],
|
||||
double VRatioChroma[],
|
||||
unsigned int HTotal[],
|
||||
unsigned int VTotal[],
|
||||
unsigned int VActive[],
|
||||
double PixelClock[],
|
||||
unsigned int BlendingAndTiming[],
|
||||
unsigned int DPPPerSurface[],
|
||||
double BytePerPixelDETY[],
|
||||
double BytePerPixelDETC[],
|
||||
double DSTXAfterScaler[],
|
||||
double DSTYAfterScaler[],
|
||||
bool WritebackEnable[],
|
||||
enum source_format_class WritebackPixelFormat[],
|
||||
double WritebackDestinationWidth[],
|
||||
double WritebackDestinationHeight[],
|
||||
double WritebackSourceHeight[],
|
||||
bool UnboundedRequestEnabled,
|
||||
unsigned int CompressedBufferSizeInkByte,
|
||||
|
||||
/* Output */
|
||||
Watermarks *Watermark,
|
||||
enum clock_change_support *DRAMClockChangeSupport,
|
||||
double MaxActiveDRAMClockChangeLatencySupported[],
|
||||
unsigned int SubViewportLinesNeededInMALL[],
|
||||
|
||||
@ -35,6 +35,8 @@
|
||||
#include "dcn30/display_rq_dlg_calc_30.h"
|
||||
#include "dcn31/display_mode_vba_31.h"
|
||||
#include "dcn31/display_rq_dlg_calc_31.h"
|
||||
#include "dcn314/display_mode_vba_314.h"
|
||||
#include "dcn314/display_rq_dlg_calc_314.h"
|
||||
#include "dcn32/display_mode_vba_32.h"
|
||||
#include "dcn32/display_rq_dlg_calc_32.h"
|
||||
#include "dml_logger.h"
|
||||
@ -74,6 +76,13 @@ const struct dml_funcs dml31_funcs = {
|
||||
.rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg
|
||||
};
|
||||
|
||||
const struct dml_funcs dml314_funcs = {
|
||||
.validate = dml314_ModeSupportAndSystemConfigurationFull,
|
||||
.recalculate = dml314_recalculate,
|
||||
.rq_dlg_get_dlg_reg = dml314_rq_dlg_get_dlg_reg,
|
||||
.rq_dlg_get_rq_reg = dml314_rq_dlg_get_rq_reg
|
||||
};
|
||||
|
||||
const struct dml_funcs dml32_funcs = {
|
||||
.validate = dml32_ModeSupportAndSystemConfigurationFull,
|
||||
.recalculate = dml32_recalculate,
|
||||
@ -107,6 +116,9 @@ void dml_init_instance(struct display_mode_lib *lib,
|
||||
case DML_PROJECT_DCN31_FPGA:
|
||||
lib->funcs = dml31_funcs;
|
||||
break;
|
||||
case DML_PROJECT_DCN314:
|
||||
lib->funcs = dml314_funcs;
|
||||
break;
|
||||
case DML_PROJECT_DCN32:
|
||||
lib->funcs = dml32_funcs;
|
||||
break;
|
||||
|
||||
@ -41,6 +41,7 @@ enum dml_project {
|
||||
DML_PROJECT_DCN30,
|
||||
DML_PROJECT_DCN31,
|
||||
DML_PROJECT_DCN31_FPGA,
|
||||
DML_PROJECT_DCN314,
|
||||
DML_PROJECT_DCN32,
|
||||
};
|
||||
|
||||
|
||||
@ -651,10 +651,10 @@ struct vba_vars_st {
|
||||
|
||||
unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
|
||||
double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
|
||||
unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
|
||||
unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
|
||||
unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
|
||||
unsigned int MacroTileHeightY[DC__NUM_DPP__MAX];
|
||||
unsigned int MacroTileHeightC[DC__NUM_DPP__MAX];
|
||||
unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
|
||||
unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
|
||||
bool ImmediateFlipRequiredFinal;
|
||||
bool DCCProgrammingAssumesScanDirectionUnknownFinal;
|
||||
bool EnoughWritebackUnits;
|
||||
@ -800,8 +800,6 @@ struct vba_vars_st {
|
||||
double PSCL_FACTOR[DC__NUM_DPP__MAX];
|
||||
double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
|
||||
double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
|
||||
unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
|
||||
double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
|
||||
double AlignedYPitch[DC__NUM_DPP__MAX];
|
||||
double AlignedCPitch[DC__NUM_DPP__MAX];
|
||||
|
||||
@ -214,6 +214,7 @@ struct dummy_pstate_entry {
|
||||
struct clk_bw_params {
|
||||
unsigned int vram_type;
|
||||
unsigned int num_channels;
|
||||
unsigned int dram_channel_width_bytes;
|
||||
unsigned int dispclk_vco_khz;
|
||||
unsigned int dc_mode_softmax_memclk;
|
||||
struct clk_limit_table clk_table;
|
||||
|
||||
@ -1600,6 +1600,7 @@ static void interpolate_user_regamma(uint32_t hw_points_num,
|
||||
struct fixed31_32 lut2;
|
||||
struct fixed31_32 delta_lut;
|
||||
struct fixed31_32 delta_index;
|
||||
const struct fixed31_32 one = dc_fixpt_from_int(1);
|
||||
|
||||
i = 0;
|
||||
/* fixed_pt library has problems handling too small values */
|
||||
@ -1628,6 +1629,9 @@ static void interpolate_user_regamma(uint32_t hw_points_num,
|
||||
} else
|
||||
hw_x = coordinates_x[i].x;
|
||||
|
||||
if (dc_fixpt_le(one, hw_x))
|
||||
hw_x = one;
|
||||
|
||||
norm_x = dc_fixpt_mul(norm_factor, hw_x);
|
||||
index = dc_fixpt_floor(norm_x);
|
||||
if (index < 0 || index > 255)
|
||||
|
||||
@ -368,6 +368,17 @@ static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
|
||||
smu_baco->platform_support =
|
||||
(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
|
||||
false;
|
||||
|
||||
/*
|
||||
* Disable BACO entry/exit completely on below SKUs to
|
||||
* avoid hardware intermittent failures.
|
||||
*/
|
||||
if (((adev->pdev->device == 0x73A1) &&
|
||||
(adev->pdev->revision == 0x00)) ||
|
||||
((adev->pdev->device == 0x73BF) &&
|
||||
(adev->pdev->revision == 0xCF)))
|
||||
smu_baco->platform_support = false;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -581,11 +581,9 @@ static const struct psb_offset cdv_regmap[2] = {
|
||||
static int cdv_chip_setup(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||||
struct pci_dev *pdev = to_pci_dev(dev->dev);
|
||||
INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
|
||||
|
||||
if (pci_enable_msi(pdev))
|
||||
dev_warn(dev->dev, "Enabling MSI failed!\n");
|
||||
dev_priv->use_msi = true;
|
||||
dev_priv->regmap = cdv_regmap;
|
||||
gma_get_core_freq(dev);
|
||||
psb_intel_opregion_init(dev);
|
||||
|
||||
@ -112,12 +112,12 @@ static void psb_gem_free_object(struct drm_gem_object *obj)
|
||||
{
|
||||
struct psb_gem_object *pobj = to_psb_gem_object(obj);
|
||||
|
||||
drm_gem_object_release(obj);
|
||||
|
||||
/* Undo the mmap pin if we are destroying the object */
|
||||
if (pobj->mmapping)
|
||||
psb_gem_unpin(pobj);
|
||||
|
||||
drm_gem_object_release(obj);
|
||||
|
||||
WARN_ON(pobj->in_gart && !pobj->stolen);
|
||||
|
||||
release_resource(&pobj->resource);
|
||||
|
||||
@ -532,15 +532,18 @@ int gma_crtc_page_flip(struct drm_crtc *crtc,
|
||||
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
|
||||
|
||||
gma_crtc->page_flip_event = event;
|
||||
spin_unlock_irqrestore(&dev->event_lock, flags);
|
||||
|
||||
/* Call this locked if we want an event at vblank interrupt. */
|
||||
ret = crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y, old_fb);
|
||||
if (ret) {
|
||||
gma_crtc->page_flip_event = NULL;
|
||||
drm_crtc_vblank_put(crtc);
|
||||
spin_lock_irqsave(&dev->event_lock, flags);
|
||||
if (gma_crtc->page_flip_event) {
|
||||
gma_crtc->page_flip_event = NULL;
|
||||
drm_crtc_vblank_put(crtc);
|
||||
}
|
||||
spin_unlock_irqrestore(&dev->event_lock, flags);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&dev->event_lock, flags);
|
||||
} else {
|
||||
ret = crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y, old_fb);
|
||||
}
|
||||
|
||||
@ -501,12 +501,9 @@ static const struct psb_offset oaktrail_regmap[2] = {
|
||||
static int oaktrail_chip_setup(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||||
struct pci_dev *pdev = to_pci_dev(dev->dev);
|
||||
int ret;
|
||||
|
||||
if (pci_enable_msi(pdev))
|
||||
dev_warn(dev->dev, "Enabling MSI failed!\n");
|
||||
|
||||
dev_priv->use_msi = true;
|
||||
dev_priv->regmap = oaktrail_regmap;
|
||||
|
||||
ret = mid_chip_setup(dev);
|
||||
|
||||
@ -139,8 +139,6 @@ static void gma_suspend_pci(struct pci_dev *pdev)
|
||||
dev_priv->regs.saveBSM = bsm;
|
||||
pci_read_config_dword(pdev, 0xFC, &vbt);
|
||||
dev_priv->regs.saveVBT = vbt;
|
||||
pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr);
|
||||
pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data);
|
||||
|
||||
pci_disable_device(pdev);
|
||||
pci_set_power_state(pdev, PCI_D3hot);
|
||||
@ -168,9 +166,6 @@ static bool gma_resume_pci(struct pci_dev *pdev)
|
||||
pci_restore_state(pdev);
|
||||
pci_write_config_dword(pdev, 0x5c, dev_priv->regs.saveBSM);
|
||||
pci_write_config_dword(pdev, 0xFC, dev_priv->regs.saveVBT);
|
||||
/* restoring MSI address and data in PCIx space */
|
||||
pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr);
|
||||
pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data);
|
||||
ret = pci_enable_device(pdev);
|
||||
|
||||
if (ret != 0)
|
||||
@ -223,8 +218,7 @@ int gma_power_resume(struct device *_dev)
|
||||
mutex_lock(&power_mutex);
|
||||
gma_resume_pci(pdev);
|
||||
gma_resume_display(pdev);
|
||||
gma_irq_preinstall(dev);
|
||||
gma_irq_postinstall(dev);
|
||||
gma_irq_install(dev);
|
||||
mutex_unlock(&power_mutex);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -383,7 +383,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
|
||||
PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
gma_irq_install(dev, pdev->irq);
|
||||
gma_irq_install(dev);
|
||||
|
||||
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
|
||||
|
||||
|
||||
@ -490,6 +490,7 @@ struct drm_psb_private {
|
||||
int rpm_enabled;
|
||||
|
||||
/* MID specific */
|
||||
bool use_msi;
|
||||
bool has_gct;
|
||||
struct oaktrail_gct_data gct_data;
|
||||
|
||||
@ -499,10 +500,6 @@ struct drm_psb_private {
|
||||
/* Register state */
|
||||
struct psb_save_area regs;
|
||||
|
||||
/* MSI reg save */
|
||||
uint32_t msi_addr;
|
||||
uint32_t msi_data;
|
||||
|
||||
/* Hotplug handling */
|
||||
struct work_struct hotplug_work;
|
||||
|
||||
|
||||
@ -316,17 +316,24 @@ void gma_irq_postinstall(struct drm_device *dev)
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
int gma_irq_install(struct drm_device *dev, unsigned int irq)
|
||||
int gma_irq_install(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||||
struct pci_dev *pdev = to_pci_dev(dev->dev);
|
||||
int ret;
|
||||
|
||||
if (irq == IRQ_NOTCONNECTED)
|
||||
if (dev_priv->use_msi && pci_enable_msi(pdev)) {
|
||||
dev_warn(dev->dev, "Enabling MSI failed!\n");
|
||||
dev_priv->use_msi = false;
|
||||
}
|
||||
|
||||
if (pdev->irq == IRQ_NOTCONNECTED)
|
||||
return -ENOTCONN;
|
||||
|
||||
gma_irq_preinstall(dev);
|
||||
|
||||
/* PCI devices require shared interrupts. */
|
||||
ret = request_irq(irq, gma_irq_handler, IRQF_SHARED, dev->driver->name, dev);
|
||||
ret = request_irq(pdev->irq, gma_irq_handler, IRQF_SHARED, dev->driver->name, dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -369,6 +376,8 @@ void gma_irq_uninstall(struct drm_device *dev)
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
free_irq(pdev->irq, dev);
|
||||
if (dev_priv->use_msi)
|
||||
pci_disable_msi(pdev);
|
||||
}
|
||||
|
||||
int gma_crtc_enable_vblank(struct drm_crtc *crtc)
|
||||
|
||||
@ -17,7 +17,7 @@ struct drm_device;
|
||||
|
||||
void gma_irq_preinstall(struct drm_device *dev);
|
||||
void gma_irq_postinstall(struct drm_device *dev);
|
||||
int gma_irq_install(struct drm_device *dev, unsigned int irq);
|
||||
int gma_irq_install(struct drm_device *dev);
|
||||
void gma_irq_uninstall(struct drm_device *dev);
|
||||
|
||||
int gma_crtc_enable_vblank(struct drm_crtc *crtc);
|
||||
|
||||
@ -23,9 +23,6 @@
|
||||
#define DRIVER_MAJOR 1
|
||||
#define DRIVER_MINOR 0
|
||||
|
||||
#define PCI_VENDOR_ID_MICROSOFT 0x1414
|
||||
#define PCI_DEVICE_ID_HYPERV_VIDEO 0x5353
|
||||
|
||||
DEFINE_DRM_GEM_FOPS(hv_fops);
|
||||
|
||||
static struct drm_driver hyperv_driver = {
|
||||
@ -133,7 +130,6 @@ static int hyperv_vmbus_probe(struct hv_device *hdev,
|
||||
}
|
||||
|
||||
ret = hyperv_setup_vram(hv, hdev);
|
||||
|
||||
if (ret)
|
||||
goto err_vmbus_close;
|
||||
|
||||
@ -150,18 +146,20 @@ static int hyperv_vmbus_probe(struct hv_device *hdev,
|
||||
|
||||
ret = hyperv_mode_config_init(hv);
|
||||
if (ret)
|
||||
goto err_vmbus_close;
|
||||
goto err_free_mmio;
|
||||
|
||||
ret = drm_dev_register(dev, 0);
|
||||
if (ret) {
|
||||
drm_err(dev, "Failed to register drm driver.\n");
|
||||
goto err_vmbus_close;
|
||||
goto err_free_mmio;
|
||||
}
|
||||
|
||||
drm_fbdev_generic_setup(dev, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_mmio:
|
||||
vmbus_free_mmio(hv->mem->start, hv->fb_size);
|
||||
err_vmbus_close:
|
||||
vmbus_close(hdev->channel);
|
||||
err_hv_set_drv_data:
|
||||
|
||||
@ -1629,6 +1629,8 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
|
||||
/* FIXME: initialize from VBT */
|
||||
vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
|
||||
|
||||
vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
|
||||
|
||||
ret = intel_dsc_compute_params(crtc_state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -389,23 +389,13 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp)
|
||||
return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
|
||||
}
|
||||
|
||||
static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
|
||||
{
|
||||
u32 voltage;
|
||||
|
||||
voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & VOLTAGE_INFO_MASK;
|
||||
|
||||
return voltage == VOLTAGE_INFO_0_85V;
|
||||
}
|
||||
|
||||
static int icl_max_source_rate(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
||||
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
|
||||
|
||||
if (intel_phy_is_combo(dev_priv, phy) &&
|
||||
(is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
|
||||
if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
|
||||
return 540000;
|
||||
|
||||
return 810000;
|
||||
@ -413,23 +403,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
|
||||
|
||||
static int ehl_max_source_rate(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
||||
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
|
||||
|
||||
if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
|
||||
return 540000;
|
||||
|
||||
return 810000;
|
||||
}
|
||||
|
||||
static int dg1_max_source_rate(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
||||
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
||||
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
|
||||
|
||||
if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
|
||||
if (intel_dp_is_edp(intel_dp))
|
||||
return 540000;
|
||||
|
||||
return 810000;
|
||||
@ -491,7 +465,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
|
||||
max_rate = dg2_max_source_rate(intel_dp);
|
||||
else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
|
||||
IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
|
||||
max_rate = dg1_max_source_rate(intel_dp);
|
||||
max_rate = 810000;
|
||||
else if (IS_JSL_EHL(dev_priv))
|
||||
max_rate = ehl_max_source_rate(intel_dp);
|
||||
else
|
||||
@ -1395,6 +1369,7 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
|
||||
* DP_DSC_RC_BUF_SIZE for this.
|
||||
*/
|
||||
vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
|
||||
vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
|
||||
|
||||
/*
|
||||
* Slice Height of 8 works for all currently available panels. So start
|
||||
|
||||
@ -460,7 +460,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
|
||||
u8 i = 0;
|
||||
|
||||
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
|
||||
vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
|
||||
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
|
||||
pipe_config->dsc.slice_count);
|
||||
|
||||
|
||||
@ -1438,7 +1438,12 @@ void intel_guc_busyness_park(struct intel_gt *gt)
|
||||
if (!guc_submission_initialized(guc))
|
||||
return;
|
||||
|
||||
cancel_delayed_work(&guc->timestamp.work);
|
||||
/*
|
||||
* There is a race with suspend flow where the worker runs after suspend
|
||||
* and causes an unclaimed register access warning. Cancel the worker
|
||||
* synchronously here.
|
||||
*/
|
||||
cancel_delayed_work_sync(&guc->timestamp.work);
|
||||
|
||||
/*
|
||||
* Before parking, we should sample engine busyness stats if we need to.
|
||||
|
||||
@ -1857,14 +1857,14 @@
|
||||
|
||||
#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
|
||||
#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
|
||||
#define PROCHOT_MASK REG_BIT(1)
|
||||
#define THERMAL_LIMIT_MASK REG_BIT(2)
|
||||
#define RATL_MASK REG_BIT(6)
|
||||
#define VR_THERMALERT_MASK REG_BIT(7)
|
||||
#define VR_TDC_MASK REG_BIT(8)
|
||||
#define POWER_LIMIT_4_MASK REG_BIT(9)
|
||||
#define POWER_LIMIT_1_MASK REG_BIT(11)
|
||||
#define POWER_LIMIT_2_MASK REG_BIT(12)
|
||||
#define PROCHOT_MASK REG_BIT(0)
|
||||
#define THERMAL_LIMIT_MASK REG_BIT(1)
|
||||
#define RATL_MASK REG_BIT(5)
|
||||
#define VR_THERMALERT_MASK REG_BIT(6)
|
||||
#define VR_TDC_MASK REG_BIT(7)
|
||||
#define POWER_LIMIT_4_MASK REG_BIT(8)
|
||||
#define POWER_LIMIT_1_MASK REG_BIT(10)
|
||||
#define POWER_LIMIT_2_MASK REG_BIT(11)
|
||||
|
||||
#define CHV_CLK_CTL1 _MMIO(0x101100)
|
||||
#define VLV_CLK_CTL2 _MMIO(0x101104)
|
||||
|
||||
@ -1882,12 +1882,13 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
|
||||
enum dma_resv_usage usage;
|
||||
int idx;
|
||||
|
||||
obj->read_domains = 0;
|
||||
if (flags & EXEC_OBJECT_WRITE) {
|
||||
usage = DMA_RESV_USAGE_WRITE;
|
||||
obj->write_domain = I915_GEM_DOMAIN_RENDER;
|
||||
obj->read_domains = 0;
|
||||
} else {
|
||||
usage = DMA_RESV_USAGE_READ;
|
||||
obj->write_domain = 0;
|
||||
}
|
||||
|
||||
dma_fence_array_for_each(curr, idx, fence)
|
||||
|
||||
@ -170,7 +170,7 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
|
||||
|
||||
/* Enable OSD and BLK0, set max global alpha */
|
||||
priv->viu.osd1_ctrl_stat = OSD_ENABLE |
|
||||
(0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
|
||||
(0x100 << OSD_GLOBAL_ALPHA_SHIFT) |
|
||||
OSD_BLK0_ENABLE;
|
||||
|
||||
priv->viu.osd1_ctrl_stat2 = readl(priv->io_base +
|
||||
|
||||
@ -94,7 +94,7 @@ static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv,
|
||||
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));
|
||||
writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
|
||||
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));
|
||||
writel((m[11] & 0x1fff) << 16,
|
||||
writel((m[11] & 0x1fff),
|
||||
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22));
|
||||
|
||||
writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
|
||||
|
||||
@ -1295,7 +1295,8 @@ static const struct panel_desc innolux_n116bca_ea1 = {
|
||||
},
|
||||
.delay = {
|
||||
.hpd_absent = 200,
|
||||
.prepare_to_enable = 80,
|
||||
.enable = 80,
|
||||
.disable = 50,
|
||||
.unprepare = 500,
|
||||
},
|
||||
};
|
||||
|
||||
@ -283,8 +283,9 @@ static int cdn_dp_connector_get_modes(struct drm_connector *connector)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cdn_dp_connector_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
static enum drm_mode_status
|
||||
cdn_dp_connector_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct cdn_dp_device *dp = connector_to_dp(connector);
|
||||
struct drm_display_info *display_info = &dp->connector.display_info;
|
||||
|
||||
@ -1439,11 +1439,15 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id,
|
||||
die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
|
||||
die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
|
||||
FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
|
||||
dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
|
||||
dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
|
||||
break;
|
||||
case ROCKCHIP_VOP2_EP_EDP0:
|
||||
die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
|
||||
die |= RK3568_SYS_DSP_INFACE_EN_EDP |
|
||||
FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
|
||||
dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
|
||||
dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
|
||||
break;
|
||||
case ROCKCHIP_VOP2_EP_MIPI0:
|
||||
die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user