diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
index 8c2604b7238a..210732ade82e 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
@@ -10,6 +10,10 @@
 #define PM8550B_SID		7
 #endif
 
+#ifndef PM8550B_I_SID
+#define PM8550B_I_SID		8
+#endif
+
 /* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
 #define PM8550B_ADC5_GEN3_OFFSET_REF			(PM8550B_SID << 8 | 0x00)
 #define PM8550B_ADC5_GEN3_1P25VREF			(PM8550B_SID << 8 | 0x01)
@@ -94,4 +98,30 @@
 #define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG		(PM8550B_SID << 8 | 0x96)
 #define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR		(PM8550B_SID << 8 | 0x9d)
 
+/* Channels for second instance of PM8550B */
+#define PM8550B_I_ADC5_GEN3_OFFSET_REF			(PM8550B_I_SID << 8 | 0x00)
+#define PM8550B_I_ADC5_GEN3_1P25VREF			(PM8550B_I_SID << 8 | 0x01)
+#define PM8550B_I_ADC5_GEN3_VREF_VADC			(PM8550B_I_SID << 8 | 0x02)
+#define PM8550B_I_ADC5_GEN3_DIE_TEMP			(PM8550B_I_SID << 8 | 0x03)
+#define PM8550B_I_ADC5_GEN3_TEMP_ALARM_LITE		(PM8550B_I_SID << 8 | 0x18)
+
+#define PM8550B_I_ADC5_GEN3_CHG_TEMP			(PM8550B_I_SID << 8 | 0x10)
+#define PM8550B_I_ADC5_GEN3_IIN_FB			(PM8550B_I_SID << 8 | 0x17)
+#define PM8550B_I_ADC5_GEN3_ICHG_FB			(PM8550B_I_SID << 8 | 0xa1)
+
+/* 100k pull-up */
+#define PM8550B_I_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU	(PM8550B_I_SID << 8 | 0x44)
+#define PM8550B_I_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU		(PM8550B_I_SID << 8 | 0x45)
+#define PM8550B_I_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU	(PM8550B_I_SID << 8 | 0x46)
+#define PM8550B_I_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU		(PM8550B_I_SID << 8 | 0x47)
+#define PM8550B_I_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU		(PM8550B_I_SID << 8 | 0x48)
+#define PM8550B_I_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU		(PM8550B_I_SID << 8 | 0x49)
+#define PM8550B_I_ADC5_GEN3_AMUX1_GPIO1_100K_PU			(PM8550B_I_SID << 8 | 0x4a)
+#define PM8550B_I_ADC5_GEN3_AMUX2_GPIO5_100K_PU			(PM8550B_I_SID << 8 | 0x4b)
+#define PM8550B_I_ADC5_GEN3_AMUX3_GPIO6_100K_PU			(PM8550B_I_SID << 8 | 0x4c)
+#define PM8550B_I_ADC5_GEN3_AMUX4_GPIO12_100K_PU		(PM8550B_I_SID << 8 | 0x4d)
+
+#define PM8550B_I_ADC5_GEN3_VPH_PWR			(PM8550B_I_SID << 8 | 0x8e)
+#define PM8550B_I_ADC5_GEN3_VBAT_SNS_QBG		(PM8550B_I_SID << 8 | 0x8f)
+
 #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
index 8ba64fae8f21..5d068c8d2510 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
+++ b/include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
@@ -26,6 +26,10 @@
 #define PM8550VE_SID		5
 #endif
 
+#ifndef PM8550VE_D_SID
+#define PM8550VE_D_SID		3
+#endif
+
 /* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
 #define PM8550VS_C_ADC5_GEN3_OFFSET_REF			(PM8550VS_C_SID << 8 | 0x00)
 #define PM8550VS_C_ADC5_GEN3_1P25VREF			(PM8550VS_C_SID << 8 | 0x01)
@@ -52,4 +56,9 @@
 #define PM8550VE_ADC5_GEN3_VREF_VADC			(PM8550VE_SID << 8 | 0X02)
 #define PM8550VE_ADC5_GEN3_DIE_TEMP			(PM8550VE_SID << 8 | 0x03)
 
+#define PM8550VE_D_ADC5_GEN3_OFFSET_REF			(PM8550VE_D_SID << 8 | 0x00)
+#define PM8550VE_D_ADC5_GEN3_1P25VREF			(PM8550VE_D_SID << 8 | 0x01)
+#define PM8550VE_D_ADC5_GEN3_VREF_VADC			(PM8550VE_D_SID << 8 | 0X02)
+#define PM8550VE_D_ADC5_GEN3_DIE_TEMP			(PM8550VE_D_SID << 8 | 0x03)
+
 #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */