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drivers:iio:stm:imu:st_lsm6dsvx: align the ODRs with latest specs

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Align the odrs with those of the latest specifications.

Signed-off-by: Mario Tesi <mario.tesi@st.com>
Change-Id: I11efae9be3d5b86476c2ab5c4b46ecfbbc3a5dbd
This commit is contained in:
Mario Tesi 2022-12-20 16:22:37 +01:00 committed by mariotesi
parent 73f3b2a697
commit b314796715
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GPG Key ID: 0B6EF815710A402D
2 changed files with 20 additions and 19 deletions
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1
drivers/iio/stm/imu/st_lsm6dsvx/st_lsm6dsvx.h
View File

@ -67,6 +67,7 @@
#define ST_LSM6DSVX_REG_CTRL1_ADDR 0x10
#define ST_LSM6DSVX_REG_CTRL2_ADDR 0x11
#define ST_LSM6DSVX_ODR_MASK GENMASK(3, 0)
#define ST_LSM6DSVX_REG_CTRL3_ADDR 0x12
#define ST_LSM6DSVX_SW_RESET_MASK BIT(0)

38
drivers/iio/stm/imu/st_lsm6dsvx/st_lsm6dsvx_core.c
View File

@ -135,33 +135,33 @@ st_lsm6dsvx_odr_table[] = {
.size = 8,
.reg = {
.addr = ST_LSM6DSVX_REG_CTRL1_ADDR,
.mask = GENMASK(6, 0),
.mask = ST_LSM6DSVX_ODR_MASK,
},
/* odr val batch */
.odr_avl[1] = { 7, 0, 0x03, 0x02 },
.odr_avl[2] = { 15, 0, 0x03, 0x03 },
.odr_avl[3] = { 30, 0, 0x04, 0x04 },
.odr_avl[4] = { 60, 0, 0x05, 0x05 },
.odr_avl[5] = { 120, 0, 0x06, 0x06 },
.odr_avl[6] = { 240, 0, 0x07, 0x07 },
.odr_avl[7] = { 480, 0, 0x08, 0x08 },
.odr_avl[8] = { 960, 0, 0x09, 0x09 },
/* odr val batch */
.odr_avl[0] = { 7, 500000, 0x02, 0x02 },
.odr_avl[1] = { 15, 0, 0x03, 0x03 },
.odr_avl[2] = { 30, 0, 0x04, 0x04 },
.odr_avl[3] = { 60, 0, 0x05, 0x05 },
.odr_avl[4] = { 120, 0, 0x06, 0x06 },
.odr_avl[5] = { 240, 0, 0x07, 0x07 },
.odr_avl[6] = { 480, 0, 0x08, 0x08 },
.odr_avl[7] = { 960, 0, 0x09, 0x09 },
},
[ST_LSM6DSVX_ID_GYRO] = {
.size = 8,
.reg = {
.addr = ST_LSM6DSVX_REG_CTRL2_ADDR,
.mask = GENMASK(6, 0),
.mask = ST_LSM6DSVX_ODR_MASK,
},
/* G LP MODE 7 Hz batch 7 Hz */
.odr_avl[1] = { 7, 0, 0x52, 0x02 },
.odr_avl[2] = { 15, 0, 0x03, 0x03 },
.odr_avl[3] = { 30, 0, 0x04, 0x04 },
.odr_avl[4] = { 60, 0, 0x05, 0x05 },
.odr_avl[5] = { 120, 0, 0x06, 0x06 },
.odr_avl[6] = { 240, 0, 0x07, 0x07 },
.odr_avl[7] = { 480, 0, 0x08, 0x08 },
.odr_avl[8] = { 960, 0, 0x09, 0x09 },
.odr_avl[0] = { 7, 500000, 0x02, 0x02 },
.odr_avl[1] = { 15, 0, 0x03, 0x03 },
.odr_avl[2] = { 30, 0, 0x04, 0x04 },
.odr_avl[3] = { 60, 0, 0x05, 0x05 },
.odr_avl[4] = { 120, 0, 0x06, 0x06 },
.odr_avl[5] = { 240, 0, 0x07, 0x07 },
.odr_avl[6] = { 480, 0, 0x08, 0x08 },
.odr_avl[7] = { 960, 0, 0x09, 0x09 },
},
[ST_LSM6DSVX_ID_TEMP] = {
.size = 3,