drm/amd/display: Clean up errors & warnings in amdgpu_dm.c
commit 87279fdf5ee0ad1360765ef70389d1c4d0f81bb6 upstream.
Fix the following errors & warnings reported by checkpatch:
ERROR: space required before the open brace '{'
ERROR: space required before the open parenthesis '('
ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: else should follow close brace '}'
ERROR: open brace '{' following function definitions go on the next line
ERROR: code indent should use tabs where possible
WARNING: braces {} are not necessary for single statement blocks
WARNING: void function return statements are not generally useful
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[ Modified for missing
c5a31f178e35 ("drm/amd/display: move dp irq handler functions from dc_link_dp to link_dp_irq_handler")
which landed in 6.3]
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Srinivasan Shanmugam
Greg Kroah-Hartman
parent
c14702daf1
commit
b31143b0fb
@ -408,12 +408,12 @@ static void dm_pflip_high_irq(void *interrupt_params)
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spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
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if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
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DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
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amdgpu_crtc->pflip_status,
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AMDGPU_FLIP_SUBMITTED,
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amdgpu_crtc->crtc_id,
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amdgpu_crtc);
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if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
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DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
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amdgpu_crtc->pflip_status,
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AMDGPU_FLIP_SUBMITTED,
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amdgpu_crtc->crtc_id,
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amdgpu_crtc);
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spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
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return;
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}
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@ -861,7 +861,7 @@ static int dm_set_powergating_state(void *handle,
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}
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/* Prototypes of private functions */
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static int dm_early_init(void* handle);
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static int dm_early_init(void *handle);
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/* Allocate memory for FBC compressed data */
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static void amdgpu_dm_fbc_init(struct drm_connector *connector)
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@ -1260,7 +1260,7 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
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pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
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pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
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pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
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pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
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pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
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pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
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@ -1343,8 +1343,7 @@ static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
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DP_TEST_RESPONSE,
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&test_response.raw,
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sizeof(test_response));
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}
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else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
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} else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
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hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) &&
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dc_link_dp_allow_hpd_rx_irq(dc_link)) {
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dc_link_dp_handle_link_loss(dc_link);
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@ -1519,7 +1518,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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mutex_init(&adev->dm.audio_lock);
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spin_lock_init(&adev->dm.vblank_lock);
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if(amdgpu_dm_irq_init(adev)) {
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if (amdgpu_dm_irq_init(adev)) {
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DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
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goto error;
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}
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@ -1654,9 +1653,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
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adev->dm.dc->debug.disable_stutter = true;
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if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
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if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
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adev->dm.dc->debug.disable_dsc = true;
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}
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if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
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adev->dm.dc->debug.disable_clock_gate = true;
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@ -1877,8 +1875,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
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mutex_destroy(&adev->dm.audio_lock);
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mutex_destroy(&adev->dm.dc_lock);
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mutex_destroy(&adev->dm.dpia_aux_lock);
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return;
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}
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static int load_dmcu_fw(struct amdgpu_device *adev)
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@ -1887,7 +1883,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
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int r;
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const struct dmcu_firmware_header_v1_0 *hdr;
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switch(adev->asic_type) {
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switch (adev->asic_type) {
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#if defined(CONFIG_DRM_AMD_DC_SI)
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case CHIP_TAHITI:
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case CHIP_PITCAIRN:
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@ -2679,7 +2675,7 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state,
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struct dc_scaling_info scaling_infos[MAX_SURFACES];
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struct dc_flip_addrs flip_addrs[MAX_SURFACES];
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struct dc_stream_update stream_update;
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} * bundle;
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} *bundle;
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int k, m;
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bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
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@ -2709,8 +2705,6 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state,
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cleanup:
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kfree(bundle);
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return;
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}
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static int dm_resume(void *handle)
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@ -2924,8 +2918,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
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.set_powergating_state = dm_set_powergating_state,
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};
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const struct amdgpu_ip_block_version dm_ip_block =
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{
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const struct amdgpu_ip_block_version dm_ip_block = {
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.type = AMD_IP_BLOCK_TYPE_DCE,
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.major = 1,
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.minor = 0,
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@ -2982,9 +2975,12 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
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caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
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caps->aux_support = false;
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if (caps->ext_caps->bits.oled == 1 /*||
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caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
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caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
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if (caps->ext_caps->bits.oled == 1
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/*
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* ||
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* caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
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* caps->ext_caps->bits.hdr_aux_backlight_control == 1
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*/)
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caps->aux_support = true;
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if (amdgpu_backlight == 0)
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@ -3248,6 +3244,7 @@ static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
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process_count < max_process_count) {
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u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
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u8 retry;
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dret = 0;
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process_count++;
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@ -3449,7 +3446,7 @@ static void register_hpd_handlers(struct amdgpu_device *adev)
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aconnector = to_amdgpu_dm_connector(connector);
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dc_link = aconnector->dc_link;
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if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
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if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
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int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
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int_params.irq_source = dc_link->irq_source_hpd;
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@ -3458,7 +3455,7 @@ static void register_hpd_handlers(struct amdgpu_device *adev)
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(void *) aconnector);
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}
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if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
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if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
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/* Also register for DP short pulse (hpd_rx). */
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int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
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@ -3484,7 +3481,7 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev)
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struct dc_interrupt_params int_params = {0};
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int r;
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int i;
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unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
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unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
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int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
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int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
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@ -3498,11 +3495,12 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev)
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* Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
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* coming from DC hardware.
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* amdgpu_dm_irq_handler() will re-direct the interrupt to DC
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* for acknowledging and handling. */
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* for acknowledging and handling.
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*/
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/* Use VBLANK interrupt */
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for (i = 0; i < adev->mode_info.num_crtc; i++) {
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r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
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r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
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if (r) {
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DRM_ERROR("Failed to add crtc irq id!\n");
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return r;
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@ -3510,7 +3508,7 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev)
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int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
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int_params.irq_source =
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dc_interrupt_to_irq_source(dc, i+1 , 0);
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dc_interrupt_to_irq_source(dc, i + 1, 0);
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c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
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@ -3566,7 +3564,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
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struct dc_interrupt_params int_params = {0};
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int r;
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int i;
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unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
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unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
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if (adev->family >= AMDGPU_FAMILY_AI)
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client_id = SOC15_IH_CLIENTID_DCE;
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@ -3583,7 +3581,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
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* Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
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* coming from DC hardware.
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* amdgpu_dm_irq_handler() will re-direct the interrupt to DC
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* for acknowledging and handling. */
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* for acknowledging and handling.
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*/
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/* Use VBLANK interrupt */
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for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
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@ -4032,7 +4031,7 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
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}
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static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
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unsigned *min, unsigned *max)
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unsigned int *min, unsigned int *max)
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{
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if (!caps)
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return 0;
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@ -4052,7 +4051,7 @@ static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
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static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
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uint32_t brightness)
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{
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unsigned min, max;
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unsigned int min, max;
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if (!get_brightness_range(caps, &min, &max))
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return brightness;
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@ -4065,7 +4064,7 @@ static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *c
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static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
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uint32_t brightness)
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{
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unsigned min, max;
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unsigned int min, max;
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if (!get_brightness_range(caps, &min, &max))
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return brightness;
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@ -4546,7 +4545,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
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{
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drm_atomic_private_obj_fini(&dm->atomic_obj);
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return;
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}
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/******************************************************************************
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@ -5272,6 +5270,7 @@ static bool adjust_colour_depth_from_display_info(
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{
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enum dc_color_depth depth = timing_out->display_color_depth;
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int normalized_clk;
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do {
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normalized_clk = timing_out->pix_clk_100hz / 10;
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/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
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@ -5487,6 +5486,7 @@ create_fake_sink(struct amdgpu_dm_connector *aconnector)
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{
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struct dc_sink_init_data sink_init_data = { 0 };
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struct dc_sink *sink = NULL;
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sink_init_data.link = aconnector->dc_link;
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sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
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@ -5610,7 +5610,7 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
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return &aconnector->freesync_vid_base;
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/* Find the preferred mode */
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list_for_each_entry (m, list_head, head) {
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list_for_each_entry(m, list_head, head) {
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if (m->type & DRM_MODE_TYPE_PREFERRED) {
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m_pref = m;
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break;
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@ -5634,7 +5634,7 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
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* For some monitors, preferred mode is not the mode with highest
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* supported refresh rate.
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*/
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list_for_each_entry (m, list_head, head) {
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list_for_each_entry(m, list_head, head) {
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current_refresh = drm_mode_vrefresh(m);
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if (m->hdisplay == m_pref->hdisplay &&
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@ -5905,7 +5905,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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* This may not be an error, the use case is when we have no
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* usermode calls to reset and set mode upon hotplug. In this
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* case, we call set mode ourselves to restore the previous mode
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* and the modelist may not be filled in in time.
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* and the modelist may not be filled in time.
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*/
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DRM_DEBUG_DRIVER("No preferred mode found\n");
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} else {
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@ -5929,9 +5929,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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drm_mode_set_crtcinfo(&mode, 0);
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/*
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* If scaling is enabled and refresh rate didn't change
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* we copy the vic and polarities of the old timings
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*/
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* If scaling is enabled and refresh rate didn't change
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* we copy the vic and polarities of the old timings
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*/
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if (!scale || mode_refresh != preferred_refresh)
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fill_stream_properties_from_drm_display_mode(
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stream, &mode, &aconnector->base, con_state, NULL,
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@ -6593,6 +6593,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
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if (!state->duplicated) {
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int max_bpc = conn_state->max_requested_bpc;
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is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
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aconnector->force_yuv420_output;
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color_depth = convert_color_depth_from_display_info(connector,
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@ -6913,7 +6914,7 @@ static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
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{
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struct drm_display_mode *m;
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list_for_each_entry (m, &aconnector->base.probed_modes, head) {
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list_for_each_entry(m, &aconnector->base.probed_modes, head) {
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if (drm_mode_equal(m, mode))
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return true;
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}
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@ -7216,7 +7217,6 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
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link->priv = aconnector;
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DRM_DEBUG_DRIVER("%s()\n", __func__);
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i2c = create_i2c(link->ddc, link->link_index, &res);
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if (!i2c) {
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@ -7861,8 +7861,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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* DRI3/Present extension with defined target_msc.
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*/
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last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
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}
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else {
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} else {
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/* For variable refresh rate mode only:
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* Get vblank of last completed flip to avoid > 1 vrr
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* flips per video frame by use of throttling, but allow
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@ -8189,8 +8188,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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dc_resource_state_copy_construct_current(dm->dc, dc_state);
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}
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for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
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new_crtc_state, i) {
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
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new_crtc_state, i) {
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
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@ -8213,9 +8212,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
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drm_dbg_state(state->dev,
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"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
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"planes_changed:%d, mode_changed:%d,active_changed:%d,"
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"connectors_changed:%d\n",
|
||||
"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
|
||||
acrtc->crtc_id,
|
||||
new_crtc_state->enable,
|
||||
new_crtc_state->active,
|
||||
@ -8700,8 +8697,8 @@ static int do_aquire_global_lock(struct drm_device *dev,
|
||||
&commit->flip_done, 10*HZ);
|
||||
|
||||
if (ret == 0)
|
||||
DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
|
||||
"timed out\n", crtc->base.id, crtc->name);
|
||||
DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
|
||||
crtc->base.id, crtc->name);
|
||||
|
||||
drm_crtc_commit_put(commit);
|
||||
}
|
||||
@ -8786,7 +8783,8 @@ is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
|
||||
return false;
|
||||
}
|
||||
|
||||
static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
|
||||
static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
|
||||
{
|
||||
u64 num, den, res;
|
||||
struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
|
||||
|
||||
@ -8909,9 +8907,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
|
||||
goto skip_modeset;
|
||||
|
||||
drm_dbg_state(state->dev,
|
||||
"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
|
||||
"planes_changed:%d, mode_changed:%d,active_changed:%d,"
|
||||
"connectors_changed:%d\n",
|
||||
"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
|
||||
acrtc->crtc_id,
|
||||
new_crtc_state->enable,
|
||||
new_crtc_state->active,
|
||||
@ -8940,8 +8936,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
|
||||
old_crtc_state)) {
|
||||
new_crtc_state->mode_changed = false;
|
||||
DRM_DEBUG_DRIVER(
|
||||
"Mode change not required for front porch change, "
|
||||
"setting mode_changed to %d",
|
||||
"Mode change not required for front porch change, setting mode_changed to %d",
|
||||
new_crtc_state->mode_changed);
|
||||
|
||||
set_freesync_fixed_config(dm_new_crtc_state);
|
||||
@ -8953,9 +8948,8 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
|
||||
struct drm_display_mode *high_mode;
|
||||
|
||||
high_mode = get_highest_refresh_rate_mode(aconnector, false);
|
||||
if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
|
||||
if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
|
||||
set_freesync_fixed_config(dm_new_crtc_state);
|
||||
}
|
||||
}
|
||||
|
||||
ret = dm_atomic_get_state(state, &dm_state);
|
||||
@ -9123,6 +9117,7 @@ static bool should_reset_plane(struct drm_atomic_state *state,
|
||||
*/
|
||||
for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
|
||||
struct amdgpu_framebuffer *old_afb, *new_afb;
|
||||
|
||||
if (other->type == DRM_PLANE_TYPE_CURSOR)
|
||||
continue;
|
||||
|
||||
@ -9221,11 +9216,12 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
|
||||
}
|
||||
|
||||
/* Core DRM takes care of checking FB modifiers, so we only need to
|
||||
* check tiling flags when the FB doesn't have a modifier. */
|
||||
* check tiling flags when the FB doesn't have a modifier.
|
||||
*/
|
||||
if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
|
||||
if (adev->family < AMDGPU_FAMILY_AI) {
|
||||
linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
|
||||
AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
|
||||
AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
|
||||
AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
|
||||
} else {
|
||||
linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
|
||||
@ -9438,12 +9434,12 @@ static int dm_check_crtc_cursor(struct drm_atomic_state *state,
|
||||
/* On DCE and DCN there is no dedicated hardware cursor plane. We get a
|
||||
* cursor per pipe but it's going to inherit the scaling and
|
||||
* positioning from the underlying pipe. Check the cursor plane's
|
||||
* blending properties match the underlying planes'. */
|
||||
* blending properties match the underlying planes'.
|
||||
*/
|
||||
|
||||
new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
|
||||
if (!new_cursor_state || !new_cursor_state->fb) {
|
||||
if (!new_cursor_state || !new_cursor_state->fb)
|
||||
return 0;
|
||||
}
|
||||
|
||||
dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
|
||||
cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
|
||||
@ -9489,6 +9485,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm
|
||||
struct drm_connector_state *conn_state, *old_conn_state;
|
||||
struct amdgpu_dm_connector *aconnector = NULL;
|
||||
int i;
|
||||
|
||||
for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
|
||||
if (!conn_state->crtc)
|
||||
conn_state = old_conn_state;
|
||||
@ -9931,7 +9928,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
|
||||
}
|
||||
|
||||
/* Store the overall update type for use later in atomic check. */
|
||||
for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
|
||||
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
|
||||
struct dm_crtc_state *dm_new_crtc_state =
|
||||
to_dm_crtc_state(new_crtc_state);
|
||||
|
||||
@ -9953,7 +9950,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
|
||||
else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
|
||||
DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
|
||||
else
|
||||
DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
|
||||
DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
|
||||
|
||||
trace_amdgpu_dm_atomic_check_finish(state, ret);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user