Merge "pinctrl: qcom: Enable egpios selectively for auto targets"
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qctecmdr
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@ -688,6 +688,7 @@ enum sdmshrike_functions {
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msm_mux_cci_timer8,
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msm_mux_cci_timer9,
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msm_mux_dp_hot,
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msm_mux_egpio,
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msm_mux_qup0,
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msm_mux_gpio,
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msm_mux_cci_i2c,
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@ -1340,6 +1341,9 @@ static const char * const gpio_groups[] = {
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"gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186",
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"gpio186", "gpio187", "gpio187", "gpio188", "gpio188", "gpio189",
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};
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static const char * const egpio_groups[] = {
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"gpio169", "gpio172", "gpio173", "gpio174",
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};
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static const char * const cci_i2c_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio17", "gpio18", "gpio19",
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"gpio20", "gpio31", "gpio32", "gpio33", "gpio34", "gpio39", "gpio40",
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@ -1812,6 +1816,7 @@ static const struct msm_function sdmshrike_functions[] = {
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FUNCTION(cci_timer8),
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FUNCTION(cci_timer9),
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FUNCTION(dp_hot),
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FUNCTION(egpio),
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FUNCTION(qup0),
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FUNCTION(gpio),
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FUNCTION(cci_i2c),
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@ -2205,12 +2210,12 @@ static const struct msm_pingroup sdmshrike_groups[] = {
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NA, NA),
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[168] = PINGROUP(168, WEST, hs3_mi2s, NA, phase_flag25, NA, NA, NA, NA,
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NA, NA),
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[169] = PINGROUP(169, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[169] = PINGROUP(169, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, egpio),
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[170] = PINGROUP(170, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[171] = PINGROUP(171, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[172] = PINGROUP(172, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[173] = PINGROUP(173, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[174] = PINGROUP(174, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[172] = PINGROUP(172, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, egpio),
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[173] = PINGROUP(173, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, egpio),
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[174] = PINGROUP(174, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, egpio),
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[175] = PINGROUP(175, SOUTH, pci_e2, NA, NA, NA, NA, NA, NA, NA, NA),
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[176] = PINGROUP(176, SOUTH, pci_e2, cci_async, NA, NA, NA, NA, NA, NA,
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NA),
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@ -56,6 +56,8 @@
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base + SOUTH_PDC_OFFSET), \
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.pull_bit = 0, \
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.drv_bit = 6, \
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.egpio_enable = 12, \
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.egpio_present = 11, \
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.oe_bit = 9, \
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.in_bit = 0, \
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.out_bit = 1, \
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@ -547,6 +549,7 @@ enum sm6150_functions {
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msm_mux_emac_gcc0,
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msm_mux_rgmii_rxc,
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msm_mux_dp_hot,
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msm_mux_egpio,
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msm_mux_emac_gcc1,
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msm_mux_rgmii_rxd3,
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msm_mux_debug_hot,
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@ -601,6 +604,9 @@ static const char * const gpio_groups[] = {
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"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
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"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
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};
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static const char * const egpio_groups[] = {
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"gpio85", "gpio98",
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};
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static const char * const qdss_gpio6_groups[] = {
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"gpio0", "gpio30",
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};
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@ -1316,6 +1322,7 @@ static const struct msm_function sm6150_functions[] = {
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FUNCTION(emac_gcc0),
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FUNCTION(rgmii_rxc),
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FUNCTION(dp_hot),
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FUNCTION(egpio),
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FUNCTION(emac_gcc1),
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FUNCTION(rgmii_rxd3),
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FUNCTION(debug_hot),
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@ -1496,7 +1503,7 @@ static const struct msm_pingroup sm6150_groups[] = {
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NA, NA, NA),
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[84] = PINGROUP(84, SOUTH, NA, phase_flag12, NA, NA, NA, NA, NA, NA,
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NA),
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[85] = PINGROUP(85, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[85] = PINGROUP(85, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, egpio),
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[86] = PINGROUP(86, SOUTH, copy_gp, NA, NA, NA, NA, NA, NA, NA, NA),
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[87] = PINGROUP(87, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[88] = PINGROUP(88, WEST, NA, usb0_hs_ac, NA, NA, NA, NA, NA, NA, NA),
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@ -1520,7 +1527,7 @@ static const struct msm_pingroup sm6150_groups[] = {
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[97] = PINGROUP(97, WEST, rgmii_tx, mdp_vsync, ldo_en, qdss_cti, NA,
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NA, NA, NA, NA),
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[98] = PINGROUP(98, WEST, mdp_vsync, ldo_update, qdss_cti, NA, NA, NA,
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NA, NA, NA),
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NA, NA, egpio),
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[99] = PINGROUP(99, EAST, prng_rosc, NA, NA, NA, NA, NA, NA, NA, NA),
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[100] = PINGROUP(100, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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[101] = PINGROUP(101, WEST, emac_gcc0, NA, NA, NA, NA, NA, NA, NA, NA),
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@ -1584,6 +1591,7 @@ static struct msm_pinctrl_soc_data sm6150_pinctrl = {
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.ngroups = ARRAY_SIZE(sm6150_groups),
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.ngpios = 124,
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.dir_conn = sm6150_dir_conn,
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.egpio_func = 9,
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};
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static int sm6150_pinctrl_dirconn_list_probe(struct platform_device *pdev)
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@ -538,6 +538,7 @@ enum sm8150_functions {
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msm_mux_ddr_pxi2,
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msm_mux_ddr_pxi3,
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msm_mux_edp_hot,
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msm_mux_egpio,
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msm_mux_edp_lcd,
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msm_mux_emac_phy,
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msm_mux_emac_pps,
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@ -1019,6 +1020,10 @@ static const char * const gpio_groups[] = {
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"gpio171", "gpio172", "gpio173", "gpio174",
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};
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static const char * const egpio_groups[] = {
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"gpio169", "gpio172", "gpio173", "gpio174",
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};
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static const char * const qup6_groups[] = {
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"gpio4", "gpio5", "gpio6", "gpio7",
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};
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@ -1273,6 +1278,7 @@ static const struct msm_function sm8150_functions[] = {
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FUNCTION(qspi_clk),
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FUNCTION(qspi_cs),
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FUNCTION(qua_mi2s),
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FUNCTION(egpio),
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FUNCTION(qup0),
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FUNCTION(qup1),
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FUNCTION(qup2),
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@ -1501,12 +1507,12 @@ static const struct msm_pingroup sm8150_groups[] = {
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[166] = PINGROUP(166, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
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[167] = PINGROUP(167, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
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[168] = PINGROUP(168, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
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[169] = PINGROUP(169, NORTH, _, _, _, _, _, _, _, _, _),
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[169] = PINGROUP(169, NORTH, _, _, _, _, _, _, _, _, egpio),
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[170] = PINGROUP(170, NORTH, _, _, _, _, _, _, _, _, _),
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[171] = PINGROUP(171, NORTH, _, _, _, _, _, _, _, _, _),
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[172] = PINGROUP(172, NORTH, _, _, _, _, _, _, _, _, _),
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[173] = PINGROUP(173, NORTH, _, _, _, _, _, _, _, _, _),
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[174] = PINGROUP(174, NORTH, _, _, _, _, _, _, _, _, _),
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[172] = PINGROUP(172, NORTH, _, _, _, _, _, _, _, _, egpio),
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[173] = PINGROUP(173, NORTH, _, _, _, _, _, _, _, _, egpio),
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[174] = PINGROUP(174, NORTH, _, _, _, _, _, _, _, _, egpio),
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[175] = UFS_RESET(ufs_reset, 0xB6000),
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[176] = SDC_QDSD_PINGROUP(sdc2_clk, 0xB2000, 14, 6),
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[177] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xB2000, 11, 3),
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