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phy: ufs-qcom: Update UFS PHY setting for pineapple

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Update the ufs phy setting as per the ufs phy guidelines
version 12.

Change-Id: I6f8933f6302594af1032c6d5b929b6735040015e
Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
This commit is contained in:
Ziqi Chen 2023-03-09 17:54:23 +08:00 committed by Bao D. Nguyen
parent c54a729dd7
commit ace4c0ccf2
1 changed files with 102 additions and 22 deletions
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124
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-pineapple.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef UFS_QCOM_PHY_QMP_V4_H_
@ -29,12 +29,15 @@
#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x30)
#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x18C)
#define QSERDES_COM_CMN_IPTRIM COM_OFF(0x100)
#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x110)
#define QSERDES_COM_CMN_CONFIG_1 COM_OFF(0x174)
#define QSERDES_COM_HSCLK_SEL_1 COM_OFF(0x3C)
#define QSERDES_COM_HSCLK_HS_SWITCH_SEL_1 COM_OFF(0x9C)
#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0x120)
#define QSERDES_COM_PLL_IVCO COM_OFF(0xF4)
#define QSERDES_COM_PLL_IVCO_MODE1 COM_OFF(0xF8)
#define QSERDES_COM_CMN_IETRIM COM_OFF(0xFC)
#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x148)
#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0x88)
#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x70)
@ -55,13 +58,16 @@
#define QSERDES_TX0_TX_FR_DCC_CTRL TX_OFF(0, 0x108)
#define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x7C)
#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX TX_OFF(0, 0x30)
#define QSERDES_TX0_RES_CODE_LANE_OFFSET_RX TX_OFF(0, 0x34)
#define QSERDES_RX0_UCDR_SO_SATURATION RX_OFF(0, 0x28)
#define QSERDES_RX0_UCDR_PI_CTRL1 RX_OFF(0, 0x58)
#define QSERDES_RX0_RX_TERM_BW_CTRL0 RX_OFF(0, 0xC4)
#define QSERDES_RX0_RX_MODE_RATE_0_1_B0 RX_OFF(0, 0x208)
#define QSERDES_RX0_RX_MODE_RATE_0_1_B1 RX_OFF(0, 0x20C)
#define QSERDES_RX0_RX_MODE_RATE_0_1_B2 RX_OFF(0, 0x210)
#define QSERDES_RX0_RX_MODE_RATE_0_1_B3 RX_OFF(0, 0x214)
#define QSERDES_RX0_RX_MODE_RATE_0_1_B4 RX_OFF(0, 0x218)
#define QSERDES_RX0_RX_MODE_RATE_0_1_B6 RX_OFF(0, 0x220)
#define QSERDES_RX0_RX_MODE_RATE2_B3 RX_OFF(0, 0x238)
#define QSERDES_RX0_RX_MODE_RATE2_B6 RX_OFF(0, 0x244)
@ -69,19 +75,41 @@
#define QSERDES_RX0_RX_MODE_RATE3_B4 RX_OFF(0, 0x260)
#define QSERDES_RX0_RX_MODE_RATE3_B5 RX_OFF(0, 0x264)
#define QSERDES_RX0_RX_MODE_RATE3_B8 RX_OFF(0, 0x270)
#define QSERDES_RX0_RX_MODE_RATE4_B0 RX_OFF(0, 0x274)
#define QSERDES_RX0_RX_MODE_RATE4_B1 RX_OFF(0, 0x278)
#define QSERDES_RX0_RX_MODE_RATE4_B2 RX_OFF(0, 0x27C)
#define QSERDES_RX0_RX_MODE_RATE4_B3 RX_OFF(0, 0x280)
#define QSERDES_RX0_RX_MODE_RATE4_B6 RX_OFF(0, 0x28C)
#define QSERDES_RX0_RX_MODE_RATE4_B4 RX_OFF(0, 0x284)
#define QSERDES_RX0_DLL0_FTUNE_CTRL RX_OFF(0, 0x2F8)
#define QSERDES_RX0_RX_INTERFACE_MODE RX_OFF(0, 0x1E0)
#define QSERDES_RX0_UCDR_FO_GAIN_RATE2 RX_OFF(0, 0xD4)
#define QSERDES_RX0_UCDR_FO_GAIN_RATE4 RX_OFF(0, 0xDC)
#define QSERDES_RX0_UCDR_SO_GAIN_RATE4 RX_OFF(0, 0xF0)
#define QSERDES_RX0_UCDR_PI_CONTROLS RX_OFF(0, 0xF4)
#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_RATE4 RX_OFF(0, 0x54)
#define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_RATE4 RX_OFF(0, 0x10)
#define QSERDES_RX0_UCDR_FASTLOCK_SO_GAIN_RATE4 RX_OFF(0, 0x24)
#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 RX_OFF(0, 0x1BC)
#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL3 RX_OFF(0, 0x1C4)
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(0, 0x1AC)
#define QSERDES_RX0_VGA_CAL_MAN_VAL RX_OFF(0, 0x178)
#define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_RATE4 RX_OFF(1, 0x10)
#define QSERDES_RX1_UCDR_FASTLOCK_SO_GAIN_RATE4 RX_OFF(1, 0x24)
#define QSERDES_RX1_UCDR_SO_SATURATION RX_OFF(1, 0x28)
#define QSERDES_RX1_UCDR_SO_GAIN_RATE4 RX_OFF(1, 0xF0)
#define QSERDES_RX1_UCDR_PI_CTRL1 RX_OFF(1, 0x58)
#define QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_RATE4 RX_OFF(1, 0x54)
#define QSERDES_RX1_RX_TERM_BW_CTRL0 RX_OFF(1, 0xC4)
#define QSERDES_RX1_UCDR_PI_CONTROLS RX_OFF(1, 0xF4)
#define QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1 RX_OFF(1, 0x1BC)
#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(1, 0x1AC)
#define QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL3 RX_OFF(1, 0x1C4)
#define QSERDES_RX1_RX_MODE_RATE_0_1_B0 RX_OFF(1, 0x208)
#define QSERDES_RX1_RX_MODE_RATE_0_1_B2 RX_OFF(1, 0x210)
#define QSERDES_RX1_RX_MODE_RATE_0_1_B1 RX_OFF(1, 0x20C)
#define QSERDES_RX1_RX_MODE_RATE_0_1_B3 RX_OFF(1, 0x214)
#define QSERDES_RX1_RX_MODE_RATE_0_1_B4 RX_OFF(1, 0x218)
#define QSERDES_RX1_RX_MODE_RATE_0_1_B6 RX_OFF(1, 0x220)
#define QSERDES_RX1_RX_MODE_RATE2_B3 RX_OFF(1, 0x238)
#define QSERDES_RX1_RX_MODE_RATE2_B6 RX_OFF(1, 0x244)
@ -89,13 +117,18 @@
#define QSERDES_RX1_RX_MODE_RATE3_B4 RX_OFF(1, 0x260)
#define QSERDES_RX1_RX_MODE_RATE3_B5 RX_OFF(1, 0x264)
#define QSERDES_RX1_RX_MODE_RATE3_B8 RX_OFF(1, 0x270)
#define QSERDES_RX1_RX_MODE_RATE4_B0 RX_OFF(1, 0x274)
#define QSERDES_RX1_RX_MODE_RATE4_B1 RX_OFF(1, 0x278)
#define QSERDES_RX1_RX_MODE_RATE4_B2 RX_OFF(1, 0x27C)
#define QSERDES_RX1_RX_MODE_RATE4_B3 RX_OFF(1, 0x280)
#define QSERDES_RX1_RX_MODE_RATE4_B6 RX_OFF(1, 0x28C)
#define QSERDES_RX1_RX_MODE_RATE4_B4 RX_OFF(1, 0x284)
#define QSERDES_RX1_DLL0_FTUNE_CTRL RX_OFF(1, 0x2F8)
#define QSERDES_RX1_RX_INTERFACE_MODE RX_OFF(1, 0x1E0)
#define QSERDES_RX1_UCDR_FO_GAIN_RATE2 RX_OFF(1, 0xD4)
#define QSERDES_RX1_UCDR_FO_GAIN_RATE4 RX_OFF(1, 0xDC)
#define QSERDES_RX1_VGA_CAL_MAN_VAL RX_OFF(1, 0x178)
#define QSERDES_TX1_RES_CODE_LANE_OFFSET_RX TX_OFF(1, 0x34)
#define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x7C)
#define QSERDES_TX1_TX_FR_DCC_CTRL TX_OFF(1, 0x108)
#define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX TX_OFF(1, 0x30)
@ -107,6 +140,8 @@
#define UFS_PHY_TX_HSGEAR_CAPABILITY PHY_OFF(0x74)
#define UFS_PHY_RX_HSGEAR_CAPABILITY PHY_OFF(0xBC)
#define UFS_PHY_RX_HS_G5_SYNC_LENGTH_CAPABILITY PHY_OFF(0x12C)
#define UFS_PHY_RX_HSG5_SYNC_WAIT_TIME PHY_OFF(0x220)
#define UFS_PHY_PHY_START PHY_OFF(0x0)
#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x1A8)
@ -136,31 +171,47 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g5[] = {
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL_1, 0x11),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x1F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO_MODE1, 0x1F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_IETRIM, 0x0A),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_IPTRIM, 0x17),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x41),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0A),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x18),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x14),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0x7F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x06),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x4C),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0A),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x18),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x14),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x99),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x05),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_RX, 0x0E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN_RATE2, 0x0C),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN_RATE4, 0x0F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_VGA_CAL_MAN_VAL, 0x0E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN_RATE4, 0x0C),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN_RATE4, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B0, 0xC2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B1, 0xC2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_VGA_CAL_MAN_VAL, 0x3E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B0, 0xCE),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B1, 0xCE),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B2, 0x18),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B3, 0x1A),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B4, 0x0F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE_0_1_B6, 0x60),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE2_B3, 0x9E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE2_B6, 0x60),
@ -168,21 +219,41 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g5[] = {
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B4, 0x0E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B5, 0x36),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE3_B8, 0x02),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B0, 0x24),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B1, 0x24),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B2, 0x20),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B3, 0xB9),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B6, 0xFF),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_RATE4_B4, 0x4F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION, 0x1F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CTRL1, 0x94),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW_CTRL0, 0xFA),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x05),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE2, 0x0C),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE4, 0x0F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_VGA_CAL_MAN_VAL, 0x0E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_DLL0_FTUNE_CTRL, 0x30),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B0, 0xC2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B1, 0xC2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x01),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x07),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_RX, 0x0E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE2, 0x0C),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN_RATE4, 0x0C),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN_RATE4, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0x7),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL3, 0x0E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x2),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1C),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_VGA_CAL_MAN_VAL, 0x3E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x0F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B0, 0xCE),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B1, 0xCE),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B2, 0x18),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B3, 0x1A),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B4, 0x0F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE_0_1_B6, 0x60),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE2_B3, 0x9E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE2_B6, 0x60),
@ -190,12 +261,18 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g5[] = {
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B4, 0x0E),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B5, 0x36),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE3_B8, 0x02),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B0, 0x24),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B1, 0x24),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B2, 0x20),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B3, 0xB9),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B6, 0xFF),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_RATE4_B4, 0x4F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION, 0x1F),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CTRL1, 0x94),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW_CTRL0, 0xFA),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_DLL0_FTUNE_CTRL, 0x30),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x00),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PCS_CTRL1, 0xC0),
@ -203,7 +280,10 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g5[] = {
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x05),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x05),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0F),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x69),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x68),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4D),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSG5_SYNC_WAIT_TIME, 0x9E),
};
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_g4[] = {
@ -216,7 +296,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {
};
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44),
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_PCS_CTRL1, 0xC1),
};