powerpc/radix: Move some functions into #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
[ Upstream commit 4a9dd8f292efd614f0a18452e6474fe19ae17b47 ]
With skiboot_defconfig, Clang reports:
CC arch/powerpc/mm/book3s64/radix_tlb.o
arch/powerpc/mm/book3s64/radix_tlb.c:419:20: error: unused function '_tlbie_pid_lpid' [-Werror,-Wunused-function]
static inline void _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
^
arch/powerpc/mm/book3s64/radix_tlb.c:663:20: error: unused function '_tlbie_va_range_lpid' [-Werror,-Wunused-function]
static inline void _tlbie_va_range_lpid(unsigned long start, unsigned long end,
^
This is because those functions are only called from functions
enclosed in a #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
Move below functions inside that #ifdef
* __tlbie_pid_lpid(unsigned long pid,
* __tlbie_va_lpid(unsigned long va, unsigned long pid,
* fixup_tlbie_pid_lpid(unsigned long pid, unsigned long lpid)
* _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
* fixup_tlbie_va_range_lpid(unsigned long va,
* __tlbie_va_range_lpid(unsigned long start, unsigned long end,
* _tlbie_va_range_lpid(unsigned long start, unsigned long end,
Fixes: f0c6fbbb90 ("KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202307260802.Mjr99P5O-lkp@intel.com/
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/3d72efd39f986ee939d068af69fdce28bd600766.1691568093.git.christophe.leroy@csgroup.eu
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Christophe Leroy
Greg Kroah-Hartman
parent
dd9241fc4b
commit
aae5a866d3
@ -127,21 +127,6 @@ static __always_inline void __tlbie_pid(unsigned long pid, unsigned long ric)
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static __always_inline void __tlbie_pid_lpid(unsigned long pid,
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unsigned long lpid,
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unsigned long ric)
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{
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unsigned long rb, rs, prs, r;
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rb = PPC_BIT(53); /* IS = 1 */
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rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
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prs = 1; /* process scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static __always_inline void __tlbie_lpid(unsigned long lpid, unsigned long ric)
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{
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unsigned long rb,rs,prs,r;
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@ -202,23 +187,6 @@ static __always_inline void __tlbie_va(unsigned long va, unsigned long pid,
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static __always_inline void __tlbie_va_lpid(unsigned long va, unsigned long pid,
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unsigned long lpid,
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unsigned long ap, unsigned long ric)
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{
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unsigned long rb, rs, prs, r;
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rb = va & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
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prs = 1; /* process scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static __always_inline void __tlbie_lpid_va(unsigned long va, unsigned long lpid,
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unsigned long ap, unsigned long ric)
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{
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@ -264,22 +232,6 @@ static inline void fixup_tlbie_va_range(unsigned long va, unsigned long pid,
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}
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}
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static inline void fixup_tlbie_va_range_lpid(unsigned long va,
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unsigned long pid,
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unsigned long lpid,
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unsigned long ap)
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{
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
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asm volatile("ptesync" : : : "memory");
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__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
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}
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
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asm volatile("ptesync" : : : "memory");
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__tlbie_va_lpid(va, pid, lpid, ap, RIC_FLUSH_TLB);
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}
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}
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static inline void fixup_tlbie_pid(unsigned long pid)
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{
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/*
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@ -299,26 +251,6 @@ static inline void fixup_tlbie_pid(unsigned long pid)
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}
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}
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static inline void fixup_tlbie_pid_lpid(unsigned long pid, unsigned long lpid)
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{
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/*
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* We can use any address for the invalidation, pick one which is
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* probably unused as an optimisation.
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*/
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unsigned long va = ((1UL << 52) - 1);
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
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asm volatile("ptesync" : : : "memory");
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__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
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}
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
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asm volatile("ptesync" : : : "memory");
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__tlbie_va_lpid(va, pid, lpid, mmu_get_ap(MMU_PAGE_64K),
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RIC_FLUSH_TLB);
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}
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}
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static inline void fixup_tlbie_lpid_va(unsigned long va, unsigned long lpid,
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unsigned long ap)
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{
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@ -416,31 +348,6 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
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unsigned long ric)
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{
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asm volatile("ptesync" : : : "memory");
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/*
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* Workaround the fact that the "ric" argument to __tlbie_pid
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* must be a compile-time contraint to match the "i" constraint
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* in the asm statement.
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*/
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switch (ric) {
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case RIC_FLUSH_TLB:
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__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_TLB);
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fixup_tlbie_pid_lpid(pid, lpid);
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break;
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case RIC_FLUSH_PWC:
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__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
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break;
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case RIC_FLUSH_ALL:
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default:
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__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_ALL);
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fixup_tlbie_pid_lpid(pid, lpid);
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}
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asm volatile("eieio; tlbsync; ptesync" : : : "memory");
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}
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struct tlbiel_pid {
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unsigned long pid;
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unsigned long ric;
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@ -566,20 +473,6 @@ static inline void __tlbie_va_range(unsigned long start, unsigned long end,
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fixup_tlbie_va_range(addr - page_size, pid, ap);
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}
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static inline void __tlbie_va_range_lpid(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long lpid,
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unsigned long page_size,
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unsigned long psize)
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{
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unsigned long addr;
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unsigned long ap = mmu_get_ap(psize);
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for (addr = start; addr < end; addr += page_size)
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__tlbie_va_lpid(addr, pid, lpid, ap, RIC_FLUSH_TLB);
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fixup_tlbie_va_range_lpid(addr - page_size, pid, lpid, ap);
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}
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static __always_inline void _tlbie_va(unsigned long va, unsigned long pid,
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unsigned long psize, unsigned long ric)
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{
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@ -660,18 +553,6 @@ static inline void _tlbie_va_range(unsigned long start, unsigned long end,
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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static inline void _tlbie_va_range_lpid(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long lpid,
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unsigned long page_size,
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unsigned long psize, bool also_pwc)
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{
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asm volatile("ptesync" : : : "memory");
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if (also_pwc)
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__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
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__tlbie_va_range_lpid(start, end, pid, lpid, page_size, psize);
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asm volatile("eieio; tlbsync; ptesync" : : : "memory");
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}
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static inline void _tlbiel_va_range_multicast(struct mm_struct *mm,
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unsigned long start, unsigned long end,
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unsigned long pid, unsigned long page_size,
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@ -1476,6 +1357,127 @@ void radix__flush_tlb_all(void)
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}
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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static __always_inline void __tlbie_pid_lpid(unsigned long pid,
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unsigned long lpid,
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unsigned long ric)
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{
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unsigned long rb, rs, prs, r;
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rb = PPC_BIT(53); /* IS = 1 */
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rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
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prs = 1; /* process scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static __always_inline void __tlbie_va_lpid(unsigned long va, unsigned long pid,
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unsigned long lpid,
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unsigned long ap, unsigned long ric)
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{
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unsigned long rb, rs, prs, r;
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rb = va & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
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prs = 1; /* process scoped */
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r = 1; /* radix format */
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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trace_tlbie(0, 0, rb, rs, ric, prs, r);
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}
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static inline void fixup_tlbie_pid_lpid(unsigned long pid, unsigned long lpid)
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{
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/*
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* We can use any address for the invalidation, pick one which is
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* probably unused as an optimisation.
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*/
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unsigned long va = ((1UL << 52) - 1);
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
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asm volatile("ptesync" : : : "memory");
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__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
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}
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
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asm volatile("ptesync" : : : "memory");
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__tlbie_va_lpid(va, pid, lpid, mmu_get_ap(MMU_PAGE_64K),
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RIC_FLUSH_TLB);
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}
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}
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static inline void _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
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unsigned long ric)
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{
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asm volatile("ptesync" : : : "memory");
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/*
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* Workaround the fact that the "ric" argument to __tlbie_pid
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* must be a compile-time contraint to match the "i" constraint
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* in the asm statement.
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*/
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switch (ric) {
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case RIC_FLUSH_TLB:
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__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_TLB);
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fixup_tlbie_pid_lpid(pid, lpid);
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break;
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case RIC_FLUSH_PWC:
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__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
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break;
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case RIC_FLUSH_ALL:
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default:
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__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_ALL);
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fixup_tlbie_pid_lpid(pid, lpid);
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}
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asm volatile("eieio; tlbsync; ptesync" : : : "memory");
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}
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static inline void fixup_tlbie_va_range_lpid(unsigned long va,
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unsigned long pid,
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unsigned long lpid,
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unsigned long ap)
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{
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
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asm volatile("ptesync" : : : "memory");
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__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
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}
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if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
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asm volatile("ptesync" : : : "memory");
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__tlbie_va_lpid(va, pid, lpid, ap, RIC_FLUSH_TLB);
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}
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}
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static inline void __tlbie_va_range_lpid(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long lpid,
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unsigned long page_size,
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unsigned long psize)
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{
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unsigned long addr;
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unsigned long ap = mmu_get_ap(psize);
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for (addr = start; addr < end; addr += page_size)
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__tlbie_va_lpid(addr, pid, lpid, ap, RIC_FLUSH_TLB);
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fixup_tlbie_va_range_lpid(addr - page_size, pid, lpid, ap);
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}
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static inline void _tlbie_va_range_lpid(unsigned long start, unsigned long end,
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unsigned long pid, unsigned long lpid,
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unsigned long page_size,
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unsigned long psize, bool also_pwc)
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{
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asm volatile("ptesync" : : : "memory");
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if (also_pwc)
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__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
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__tlbie_va_range_lpid(start, end, pid, lpid, page_size, psize);
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asm volatile("eieio; tlbsync; ptesync" : : : "memory");
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}
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/*
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* Performs process-scoped invalidations for a given LPID
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* as part of H_RPT_INVALIDATE hcall.
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