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drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr()

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[ Upstream commit 3313c23f3eab698bc6b904520ee608fc0f7b03d0 ]

Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.

In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.

Fixes: 7b37523fb1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util")
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/572009/
Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-2-6da6cd1bf118@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jessica Zhang 2023-12-13 13:30:18 -08:00 committed by Greg Kroah-Hartman
parent 08d7e291af
commit aa3e61cf89
8 changed files with 22 additions and 33 deletions
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4
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat * Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com> * Author: Rob Clark <robdclark@gmail.com>
@ -124,7 +124,7 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
continue; continue;
/* Calculate MISR over 1 frame */ /* Calculate MISR over 1 frame */
m->hw_lm->ops.setup_misr(m->hw_lm, true, 1); m->hw_lm->ops.setup_misr(m->hw_lm);
} }
} }

4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
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@ -2,7 +2,7 @@
/* /*
* Copyright (C) 2013 Red Hat * Copyright (C) 2013 Red Hat
* Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* *
* Author: Rob Clark <robdclark@gmail.com> * Author: Rob Clark <robdclark@gmail.com>
*/ */
@ -257,7 +257,7 @@ void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
continue; continue;
phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1); phys->hw_intf->ops.setup_misr(phys->hw_intf);
} }
} }

6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/ */
@ -322,9 +322,9 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
return DPU_REG_READ(c, INTF_LINE_COUNT); return DPU_REG_READ(c, INTF_LINE_COUNT);
} }
static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)
{ {
dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1); dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1);
} }
static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)

4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/ */
@ -80,7 +80,7 @@ struct dpu_hw_intf_ops {
void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
bool enable, bool enable,
const enum dpu_pingpong pp); const enum dpu_pingpong pp);
void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count); void (*setup_misr)(struct dpu_hw_intf *intf);
int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value); int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
}; };

6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/ */
@ -99,9 +99,9 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
} }
} }
static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count) static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
{ {
dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0); dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
} }
static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/ */
@ -57,7 +58,7 @@ struct dpu_hw_lm_ops {
/** /**
* setup_misr: Enable/disable MISR * setup_misr: Enable/disable MISR
*/ */
void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count); void (*setup_misr)(struct dpu_hw_mixer *ctx);
/** /**
* collect_misr: Read MISR signature * collect_misr: Read MISR signature

15
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/ */
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@ -454,9 +454,7 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
* note: Aside from encoders, input_sel should be set to 0x0 by default * note: Aside from encoders, input_sel should be set to 0x0 by default
*/ */
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_ctrl_offset, u32 misr_ctrl_offset, u8 input_sel)
bool enable, u32 frame_count,
u8 input_sel)
{ {
u32 config = 0; u32 config = 0;
@ -465,16 +463,9 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
/* Clear old MISR value (in case it's read before a new value is calculated)*/ /* Clear old MISR value (in case it's read before a new value is calculated)*/
wmb(); wmb();
if (enable) { config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
config = (frame_count & MISR_FRAME_COUNT_MASK) |
MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
((input_sel & 0xF) << 24); ((input_sel & 0xF) << 24);
DPU_REG_WRITE(c, misr_ctrl_offset, config); DPU_REG_WRITE(c, misr_ctrl_offset, config);
} else {
DPU_REG_WRITE(c, misr_ctrl_offset, 0);
}
} }
int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,

9
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/ */
@ -13,7 +13,7 @@
#include "dpu_hw_catalog.h" #include "dpu_hw_catalog.h"
#define REG_MASK(n) ((BIT(n)) - 1) #define REG_MASK(n) ((BIT(n)) - 1)
#define MISR_FRAME_COUNT_MASK 0xFF #define MISR_FRAME_COUNT 0x1
#define MISR_CTRL_ENABLE BIT(8) #define MISR_CTRL_ENABLE BIT(8)
#define MISR_CTRL_STATUS BIT(9) #define MISR_CTRL_STATUS BIT(9)
#define MISR_CTRL_STATUS_CLEAR BIT(10) #define MISR_CTRL_STATUS_CLEAR BIT(10)
@ -350,10 +350,7 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
u32 total_fl); u32 total_fl);
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_ctrl_offset, u32 misr_ctrl_offset, u8 input_sel);
bool enable,
u32 frame_count,
u8 input_sel);
int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_ctrl_offset, u32 misr_ctrl_offset,