android/android_kernel_samsung_sm8650
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Linux 5.14-rc1

Browse Source 
-----BEGIN PGP SIGNATURE-----
 
 iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAmDra6weHHRvcnZhbGRz
 QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGNh8H/0gNlQ6rJAp/nvkm
 KXug/d5wBW1qep9Ier9AgKHCv+uXTTFYXKTXG9xPsTGWqlBFzviPk+Z3BVY4G9QE
 yG7N60zhqxpb9mxLdlYX4wB8Lt/BOSvngqX2H5JWbTYl3eI9kD4jJoDt7Aw8c4ef
 nr+VOhrc0HONHF4GBcnBM8837RCBtXNiipXmLLKYwp2WnwV47LyO0st30W/MNeO/
 ERYfIKGM9mA8BYFVb6RGmOmwVXe7z1nDk3rCwgmVk+O+JrKa3RAAe7f5UygaMr6h
 AJGA6G7rLOdCiLsGhCqqwXozcqy7JiJgd4eiJpRfySEBwLRZAEpJOTIyaGFekBpC
 8IxN91c=
 =Jmir
 -----END PGP SIGNATURE-----

Merge tag 'v5.14-rc1' into android-mainline

Linux 5.14-rc1

Change-Id: I9765cd4581f6683a6fca3580667017fff9cbaa2b
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Lee Jones 2021-07-13 10:01:14 +01:00
commit a8b636db7d
1849 changed files with 59082 additions and 24004 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
Documentation/ABI/testing/sysfs-fs-f2fs
View File

@ -203,7 +203,34 @@ Description: Shows total written kbytes issued to disk.
What: /sys/fs/f2fs/<disk>/features
Date: July 2017
Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
Description: Shows all enabled features in current device.
Description: <deprecated: should use /sys/fs/f2fs/<disk>/feature_list/
Shows all enabled features in current device.
Supported features:
encryption, blkzoned, extra_attr, projquota, inode_checksum,
flexible_inline_xattr, quota_ino, inode_crtime, lost_found,
verity, sb_checksum, casefold, readonly, compression, pin_file.
What: /sys/fs/f2fs/<disk>/feature_list/
Date: June 2021
Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
Description: Expand /sys/fs/f2fs/<disk>/features to meet sysfs rule.
Supported on-disk features:
encryption, block_zoned (aka blkzoned), extra_attr,
project_quota (aka projquota), inode_checksum,
flexible_inline_xattr, quota_ino, inode_crtime, lost_found,
verity, sb_checksum, casefold, readonly, compression.
Note that, pin_file is moved into /sys/fs/f2fs/features/.
What: /sys/fs/f2fs/features/
Date: July 2017
Contact: "Jaegeuk Kim" <jaegeuk@kernel.org>
Description: Shows all enabled kernel features.
Supported features:
encryption, block_zoned, extra_attr, project_quota,
inode_checksum, flexible_inline_xattr, quota_ino,
inode_crtime, lost_found, verity, sb_checksum,
casefold, readonly, compression, test_dummy_encryption_v2,
atomic_write, pin_file, encrypted_casefold.
What: /sys/fs/f2fs/<disk>/inject_rate
Date: May 2016
@ -438,3 +465,31 @@ Description: Show the count of inode newly enabled for compression since mount.
Note that when the compression is disabled for the files, this count
doesn't decrease. If you write "0" here, you can initialize
compr_new_inode to "0".
What: /sys/fs/f2fs/<disk>/atgc_candidate_ratio
Date: May 2021
Contact: "Chao Yu" <yuchao0@huawei.com>
Description: When ATGC is on, it controls candidate ratio in order to limit total
number of potential victim in all candidates, the value should be in
range of [0, 100], by default it was initialized as 20(%).
What: /sys/fs/f2fs/<disk>/atgc_candidate_count
Date: May 2021
Contact: "Chao Yu" <yuchao0@huawei.com>
Description: When ATGC is on, it controls candidate count in order to limit total
number of potential victim in all candidates, by default it was
initialized as 10 (sections).
What: /sys/fs/f2fs/<disk>/atgc_age_weight
Date: May 2021
Contact: "Chao Yu" <yuchao0@huawei.com>
Description: When ATGC is on, it controls age weight to balance weight proportion
in between aging and valid blocks, the value should be in range of
[0, 100], by default it was initialized as 60(%).
What: /sys/fs/f2fs/<disk>/atgc_age_threshold
Date: May 2021
Contact: "Chao Yu" <yuchao0@huawei.com>
Description: When ATGC is on, it controls age threshold to bypass GCing young
candidates whose age is not beyond the threshold, by default it was
initialized as 604800 seconds (equals to 7 days).

2
Documentation/PCI/pci-error-recovery.rst
View File

@ -295,7 +295,7 @@ and let the driver restart normal I/O processing.
A driver can still return a critical failure for this function if
it can't get the device operational after reset. If the platform
previously tried a soft reset, it might now try a hard reset (power
cycle) and then call slot_reset() again. It the device still can't
cycle) and then call slot_reset() again. If the device still can't
be recovered, there is nothing more that can be done; the platform
will typically report a "permanent failure" in such a case. The
device will be considered "dead" in this case.

11
Documentation/core-api/printk-formats.rst
View File

@ -125,6 +125,17 @@ used when printing stack backtraces. The specifier takes into
consideration the effect of compiler optimisations which may occur
when tail-calls are used and marked with the noreturn GCC attribute.
If the pointer is within a module, the module name and optionally build ID is
printed after the symbol name with an extra ``b`` appended to the end of the
specifier.
::
%pS versatile_init+0x0/0x110 [module_name]
%pSb versatile_init+0x0/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
%pSRb versatile_init+0x9/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
(with __builtin_extract_return_addr() translation)
%pBb prev_fn_of_versatile_init+0x88/0x88 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
Probed Pointers from BPF / tracing
----------------------------------

6
Documentation/cpu-freq/cpu-drivers.rst
View File

@ -58,9 +58,6 @@ And optionally
.driver_data - cpufreq driver specific data.
.resolve_freq - Returns the most appropriate frequency for a target
frequency. Doesn't change the frequency though.
.get_intermediate and target_intermediate - Used to switch to stable
frequency while changing CPU frequency.
@ -71,9 +68,6 @@ And optionally
.exit - A pointer to a per-policy cleanup function called during
CPU_POST_DEAD phase of cpu hotplug process.
.stop_cpu - A pointer to a per-policy stop function called during
CPU_DOWN_PREPARE phase of cpu hotplug process.
.suspend - A pointer to a per-policy suspend function which is called
with interrupts disabled and _after_ the governor is stopped for the
policy.

1
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@ -167,6 +167,7 @@ properties:
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items:
- enum:
- bananapi,bpi-m5
- hardkernel,odroid-c4
- hardkernel,odroid-hc4
- khadas,vim3l

1
Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
View File

@ -18,6 +18,7 @@ properties:
- description: BCM2711 based Boards
items:
- enum:
- raspberrypi,400
- raspberrypi,4-model-b
- const: brcm,bcm2711

7
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -257,6 +257,13 @@ properties:
where voltage is in V, frequency is in MHz.
performance-domains:
maxItems: 1
description:
List of phandles and performance domain specifiers, as defined by
bindings of the performance domain provider. See also
dvfs/performance-domain.yaml.
power-domains:
description:
List of phandles and PM domain specifiers, as defined by bindings of the

13
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -197,6 +197,7 @@ properties:
- boundary,imx6q-nitrogen6x
- compulab,cm-fx6 # CompuLab CM-FX6
- dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board
- ds,imx6q-sbc # Da Sheng COM-9XX Modules
- embest,imx6q-marsboard # Embest MarS Board i.MX6Dual
- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
@ -400,6 +401,17 @@ properties:
- const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM
- const: fsl,imx6dl
- description: i.MX6DL based congatec QMX6 Boards
items:
- enum:
- ge,imx6dl-b105v2 # General Electric B105v2
- ge,imx6dl-b105pv2 # General Electric B105Pv2
- ge,imx6dl-b125v2 # General Electric B125v2
- ge,imx6dl-b125pv2 # General Electric B125Pv2
- ge,imx6dl-b155v2 # General Electric B155v2
- const: congatec,qmx6
- const: fsl,imx6dl
- description: i.MX6DL based DFI FS700-M60-6DL Board
items:
- const: dfi,fs700-m60-6dl
@ -685,6 +697,7 @@ properties:
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm

1
Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
View File

@ -17,6 +17,7 @@ properties:
- items:
- enum:
- linksys,nslu2
- welltech,epbx100
- const: intel,ixp42x
- items:
- enum:

29
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@ -122,6 +122,10 @@ properties:
- enum:
- mediatek,mt8195-evb
- const: mediatek,mt8195
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
items:
- const: google,burnet
- const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
@ -133,9 +137,19 @@ properties:
items:
- const: google,damu
- const: mediatek,mt8183
- description: Google Juniper (Acer Chromebook Spin 311)
- description: Google Fennel (Lenovo IdeaPad 3 Chromebook)
items:
- const: google,juniper-sku16
- enum:
- google,fennel-sku0
- google,fennel-sku1
- google,fennel-sku6
- const: google,fennel
- const: mediatek,mt8183
- description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
items:
- enum:
- google,juniper-sku16
- google,juniper-sku17
- const: google,juniper
- const: mediatek,mt8183
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
@ -144,6 +158,10 @@ properties:
- const: google,kakadu-rev2
- const: google,kakadu
- const: mediatek,mt8183
- description: Google Kappa (HP Chromebook 11a)
items:
- const: google,kappa
- const: mediatek,mt8183
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
@ -153,6 +171,13 @@ properties:
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
- description: Google Willow (Acer Chromebook 311 C722/C722T)
items:
- enum:
- google,willow-sku0
- google,willow-sku1
- const: google,willow
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8183-pumpkin

1
Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
View File

@ -25,6 +25,7 @@ PROPERTIES
"qcom,saw2"
A more specific value could be one of:
"qcom,apq8064-saw2-v1.1-cpu"
"qcom,msm8226-saw2-v2.1-cpu"
"qcom,msm8974-saw2-v2.1-cpu"
"qcom,apq8084-saw2-v2.1-cpu"

14
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -36,17 +36,20 @@ description: |
msm8992
msm8994
msm8996
sa8155p
sc7180
sc7280
sdm630
sdm660
sdm845
sdx55
sm8150
sm8250
sm8350
The 'board' element must be one of the following strings:
adp
cdp
cp01-c1
dragonboard
@ -178,6 +181,7 @@ properties:
- items:
- enum:
- qcom,sc7280-idp
- google,senor
- const: qcom,sc7280
- items:
@ -198,6 +202,16 @@ properties:
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
- items:
- enum:
- qcom,sa8155p-adp
- const: qcom,sa8155p
- items:
- enum:
- qcom,sm8150-mtp
- const: qcom,sm8150
- items:
- enum:
- qcom,qrb5165-rb5

18
Documentation/devicetree/bindings/arm/renesas.yaml
View File

@ -302,6 +302,24 @@ properties:
- renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
- const: renesas,r9a06g032
- description: RZ/G2UL (R9A07G043)
items:
- enum:
- renesas,r9a07g043u11 # RZ/G2UL Type-1
- renesas,r9a07g043u12 # RZ/G2UL Type-2
- const: renesas,r9a07g043
- description: RZ/G2{L,LC} (R9A07G044)
items:
- enum:
- renesas,smarc-evk # SMARC EVK
- enum:
- renesas,r9a07g044c1 # Single Cortex-A55 RZ/G2LC
- renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC
- renesas,r9a07g044l1 # Single Cortex-A55 RZ/G2L
- renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
- const: renesas,r9a07g044
additionalProperties: true
...

5
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -600,6 +600,11 @@ properties:
- const: zkmagic,a95x-z2
- const: rockchip,rk3318
- description: Rockchip RK3568 Evaluation board
items:
- const: rockchip,rk3568-evb1-v10
- const: rockchip,rk3568
additionalProperties: true
...

16
Documentation/devicetree/bindings/arm/rockchip/pmu.txt
View File

@ -1,16 +0,0 @@
Rockchip power-management-unit:
-------------------------------
The pmu is used to turn off and on different power domains of the SoCs
This includes the power to the CPU cores.
Required node properties:
- compatible value : = "rockchip,rk3066-pmu";
- reg : physical base address and the size of the registers window
Example:
pmu@20004000 {
compatible = "rockchip,rk3066-pmu";
reg = <0x20004000 0x100>;
};

55
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml Normal file
View File

@ -0,0 +1,55 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip Power Management Unit (PMU)
maintainers:
- Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |
The PMU is used to turn on and off different power domains of the SoCs.
This includes the power to the CPU cores.
select:
properties:
compatible:
contains:
enum:
- rockchip,px30-pmu
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3399-pmu
required:
- compatible
properties:
compatible:
items:
- enum:
- rockchip,px30-pmu
- rockchip,rk3066-pmu
- rockchip,rk3288-pmu
- rockchip,rk3399-pmu
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: true
examples:
- |
pmu@20004000 {
compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
reg = <0x20004000 0x100>;
};

11
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@ -224,6 +224,12 @@ properties:
- const: empire-electronix,m712
- const: allwinner,sun5i-a13
- description: Forlinx OKA40i-C Development board
items:
- const: forlinx,oka40i-c
- const: forlinx,feta40i-c
- const: allwinner,sun8i-r40
- description: FriendlyARM NanoPi A64
items:
- const: friendlyarm,nanopi-a64
@ -269,6 +275,11 @@ properties:
- const: friendlyarm,nanopi-r1
- const: allwinner,sun8i-h3
- description: FriendlyARM NanoPi R1S H5
items:
- const: friendlyarm,nanopi-r1s-h5
- const: allwinner,sun50i-h5
- description: FriendlyARM ZeroPi
items:
- const: friendlyarm,zeropi

35
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
View File

@ -301,6 +301,33 @@ patternProperties:
additionalProperties: false
core-domain:
type: object
description: |
The vast majority of hardware blocks of Tegra SoC belong to a
Core power domain, which has a dedicated voltage rail that powers
the blocks.
properties:
operating-points-v2:
description:
Should contain level, voltages and opp-supported-hw property.
The supported-hw is a bitfield indicating SoC speedo or process
ID mask.
"#power-domain-cells":
const: 0
required:
- operating-points-v2
- "#power-domain-cells"
additionalProperties: false
core-supply:
description:
Phandle to voltage regulator connected to the SoC Core power rail.
required:
- compatible
- reg
@ -325,6 +352,7 @@ examples:
tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x7000e400 0x400>;
core-supply = <&regulator>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
@ -338,17 +366,24 @@ examples:
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
pd_core: core-domain {
operating-points-v2 = <&core_opp_table>;
#power-domain-cells = <0>;
};
powergates {
pd_audio: aud {
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
resets = <&tegra_car 198>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};

313
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
View File

@ -1,313 +0,0 @@
Broadcom iProc Family Clocks
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The iProc clock controller manages clocks that are common to the iProc family.
An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
comprises of several leaf clocks
Required properties for a PLL and its leaf clocks:
- compatible:
Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
Cygnus has a compatible string of "brcm,cygnus-genpll"
- #clock-cells:
Have a value of <1> since there are more than 1 leaf clock of a given PLL
- reg:
Define the base and range of the I/O address space that contain the iProc
clock control registers required for the PLL
- clocks:
The input parent clock phandle for the PLL. For most iProc PLLs, this is an
onboard crystal with a fixed rate
- clock-output-names:
An ordered list of strings defining the names of the clocks
Example:
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
genpll: genpll {
#clock-cells = <1>;
compatible = "brcm,cygnus-genpll";
reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
clocks = <&osc>;
clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
"enet_sw", "audio_125", "can";
};
Required properties for ASIU clocks:
ASIU clocks are a special case. These clocks are derived directly from the
reference clock of the onboard crystal
- compatible:
Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
- #clock-cells:
Have a value of <1> since there are more than 1 ASIU clocks
- reg:
Define the base and range of the I/O address space that contain the iProc
clock control registers required for ASIU clocks
- clocks:
The input parent clock phandle for the ASIU clock, i.e., the onboard
crystal
- clock-output-names:
An ordered list of strings defining the names of the ASIU clocks
Example:
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
asiu_clks: asiu_clks {
#clock-cells = <1>;
compatible = "brcm,cygnus-asiu-clk";
reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
clocks = <&osc>;
clock-output-names = "keypad", "adc/touch", "pwm";
};
Cygnus
------
PLL and leaf clock compatible strings for Cygnus are:
"brcm,cygnus-armpll"
"brcm,cygnus-genpll"
"brcm,cygnus-lcpll0"
"brcm,cygnus-mipipll"
"brcm,cygnus-asiu-clk"
"brcm,cygnus-audiopll"
The following table defines the set of PLL/clock index and ID for Cygnus.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-cygnus.h"
Clock Source (Parent) Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
armpll crystal N/A N/A
keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
genpll crystal 0 BCM_CYGNUS_GENPLL
axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
mipipll crystal 0 BCM_CYGNUS_MIPIPLL
ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
Hurricane 2
------
PLL and leaf clock compatible strings for Hurricane 2 are:
"brcm,hr2-armpll"
The following table defines the set of PLL/clock for Hurricane 2:
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
armpll crystal N/A N/A
Northstar and Northstar Plus
------
PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
"brcm,nsp-armpll"
"brcm,nsp-genpll"
"brcm,nsp-lcpll0"
The following table defines the set of PLL/clock index and ID for Northstar and
Northstar Plus. These clock IDs are defined in:
"include/dt-bindings/clock/bcm-nsp.h"
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
armpll crystal N/A N/A
genpll crystal 0 BCM_NSP_GENPLL
phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
lcpll0 crystal 0 BCM_NSP_LCPLL0
pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
Northstar 2
-----------
PLL and leaf clock compatible strings for Northstar 2 are:
"brcm,ns2-genpll-scr"
"brcm,ns2-genpll-sw"
"brcm,ns2-lcpll-ddr"
"brcm,ns2-lcpll-ports"
The following table defines the set of PLL/clock index and ID for Northstar 2.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-ns2.h"
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
genpll_sw crystal 0 BCM_NS2_GENPLL_SW
rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
BCM63138
--------
PLL and leaf clock compatible strings for BCM63138 are:
"brcm,bcm63138-armpll"
Stingray
-----------
PLL and leaf clock compatible strings for Stingray are:
"brcm,sr-genpll0"
"brcm,sr-genpll1"
"brcm,sr-genpll2"
"brcm,sr-genpll3"
"brcm,sr-genpll4"
"brcm,sr-genpll5"
"brcm,sr-genpll6"
"brcm,sr-lcpll0"
"brcm,sr-lcpll1"
"brcm,sr-lcpll-pcie"
The following table defines the set of PLL/clock index and ID for Stingray.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-sr.h"
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
crmu_ref25m crystal N/A N/A
genpll0 crystal 0 BCM_SR_GENPLL0
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
genpll1 crystal 0 BCM_SR_GENPLL1
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
genpll2 crystal 0 BCM_SR_GENPLL2
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
genpll3 crystal 0 BCM_SR_GENPLL3
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
genpll4 crystal 0 BCM_SR_GENPLL4
clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
genpll5 crystal 0 BCM_SR_GENPLL5
clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
genpll6 crystal 0 BCM_SR_GENPLL6
clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
lcpll0 crystal 0 BCM_SR_LCPLL0
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
lcpll1 crystal 0 BCM_SR_LCPLL1
clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK

395
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.yaml Normal file
View File

@ -0,0 +1,395 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom iProc Family Clocks
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
description: |
The iProc clock controller manages clocks that are common to the iProc family.
An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
comprises of several leaf clocks
ASIU clocks are a special case. These clocks are derived directly from the
reference clock of the onboard crystal.
properties:
compatible:
enum:
- brcm,bcm63138-armpll
- brcm,cygnus-armpll
- brcm,cygnus-genpll
- brcm,cygnus-lcpll0
- brcm,cygnus-mipipll
- brcm,cygnus-asiu-clk
- brcm,cygnus-audiopll
- brcm,hr2-armpll
- brcm,nsp-armpll
- brcm,nsp-genpll
- brcm,nsp-lcpll0
- brcm,ns2-genpll-scr
- brcm,ns2-genpll-sw
- brcm,ns2-lcpll-ddr
- brcm,ns2-lcpll-ports
- brcm,sr-genpll0
- brcm,sr-genpll1
- brcm,sr-genpll2
- brcm,sr-genpll3
- brcm,sr-genpll4
- brcm,sr-genpll5
- brcm,sr-genpll6
- brcm,sr-lcpll0
- brcm,sr-lcpll1
- brcm,sr-lcpll-pcie
reg:
minItems: 1
maxItems: 3
items:
- description: base register
- description: power register
- description: ASIU or split status register
clocks:
description: The input parent clock phandle for the PLL / ASIU clock. For
most iProc PLLs, this is an onboard crystal with a fixed rate.
maxItems: 1
'#clock-cells':
const: 1
clock-output-names:
minItems: 1
maxItems: 45
allOf:
- if:
properties:
compatible:
contains:
enum:
- brcm,cygnus-armpll
- brcm,cygnus-genpll
- brcm,cygnus-lcpll0
- brcm,cygnus-mipipll
- brcm,cygnus-asiu-clk
- brcm,cygnus-audiopll
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Cygnus.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-cygnus.h"
Clock Source (Parent) Index ID
----- --------------- ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
genpll crystal 0 BCM_CYGNUS_GENPLL
axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
mipipll crystal 0 BCM_CYGNUS_MIPIPLL
ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
- if:
properties:
compatible:
contains:
enum:
- brcm,hr2-armpll
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock for Hurricane 2:
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
- if:
properties:
compatible:
contains:
enum:
- brcm,nsp-armpll
- brcm,nsp-genpll
- brcm,nsp-lcpll0
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Northstar and
Northstar Plus. These clock IDs are defined in:
"include/dt-bindings/clock/bcm-nsp.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
armpll crystal N/A N/A
genpll crystal 0 BCM_NSP_GENPLL
phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
lcpll0 crystal 0 BCM_NSP_LCPLL0
pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
- if:
properties:
compatible:
contains:
enum:
- brcm,ns2-genpll-scr
- brcm,ns2-genpll-sw
- brcm,ns2-lcpll-ddr
- brcm,ns2-lcpll-ports
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Northstar 2.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-ns2.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
genpll_sw crystal 0 BCM_NS2_GENPLL_SW
rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
- if:
properties:
compatible:
contains:
enum:
- brcm,sr-genpll0
- brcm,sr-genpll1
- brcm,sr-genpll2
- brcm,sr-genpll3
- brcm,sr-genpll4
- brcm,sr-genpll5
- brcm,sr-genpll6
- brcm,sr-lcpll0
- brcm,sr-lcpll1
- brcm,sr-lcpll-pcie
then:
properties:
clock-output-names:
description: |
The following table defines the set of PLL/clock index and ID for Stingray.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-sr.h"
Clock Source Index ID
----- ------ ----- --
crystal N/A N/A N/A
crmu_ref25m crystal N/A N/A
genpll0 crystal 0 BCM_SR_GENPLL0
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
genpll1 crystal 0 BCM_SR_GENPLL1
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
genpll2 crystal 0 BCM_SR_GENPLL2
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
genpll3 crystal 0 BCM_SR_GENPLL3
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
genpll4 crystal 0 BCM_SR_GENPLL4
clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
genpll5 crystal 0 BCM_SR_GENPLL5
clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
genpll6 crystal 0 BCM_SR_GENPLL6
clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
lcpll0 crystal 0 BCM_SR_LCPLL0
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
lcpll1 crystal 0 BCM_SR_LCPLL1
clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
- if:
properties:
compatible:
contains:
const: brcm,cygnus-genpll
then:
properties:
clock-output-names:
items:
- const: genpll
- const: axi21
- const: 250mhz
- const: ihost_sys
- const: enet_sw
- const: audio_125
- const: can
- if:
properties:
compatible:
contains:
const: brcm,nsp-lcpll0
then:
properties:
clock-output-names:
items:
- const: lcpll0
- const: pcie_phy
- const: sdio
- const: ddr_phy
- if:
properties:
compatible:
contains:
const: brcm,nsp-genpll
then:
properties:
clock-output-names:
items:
- const: genpll
- const: phy
- const: ethernetclk
- const: usbclk
- const: iprocfast
- const: sata1
- const: sata2
required:
- reg
- clocks
- '#clock-cells'
- clock-output-names
additionalProperties: false
examples:
- |
osc1: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
genpll@301d000 {
#clock-cells = <1>;
compatible = "brcm,cygnus-genpll";
reg = <0x301d000 0x2c>, <0x301c020 0x4>;
clocks = <&os1c>;
clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
"enet_sw", "audio_125", "can";
};
- |
osc2: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
asiu_clks@301d048 {
#clock-cells = <1>;
compatible = "brcm,cygnus-asiu-clk";
reg = <0x301d048 0xc>, <0x180aa024 0x4>;
clocks = <&osc2>;
clock-output-names = "keypad", "adc/touch", "pwm";
};

63
Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
View File

@ -1,63 +0,0 @@
NVIDIA Tegra114 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra114-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra114-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra114-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA114_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
osc: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <12000000>;
};
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k> <&osc>;
};
};

107
Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
View File

@ -1,107 +0,0 @@
NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in the header files
<dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
(for Tegra124-specific clocks).
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
- nvidia,external-memory-controller : phandle of the EMC driver.
The node should contain a "emc-timings" subnode for each supported RAM type (see
field RAM_CODE in register PMC_STRAPPING_OPT_A).
Required properties for "emc-timings" nodes :
- nvidia,ram-code : Should contain the value of RAM_CODE this timing set
is used for.
Each "emc-timings" node should contain a "timing" subnode for every supported
EMC clock rate.
Required properties for "timing" nodes :
- clock-frequency : Should contain the memory clock rate to which this timing
relates.
- nvidia,parent-clock-frequency : Should contain the rate at which the current
parent of the EMC clock should be running at this timing.
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- emc-parent : the clock that should be the parent of the EMC clock at this
timing.
Example SoC include file:
/ {
tegra_car: clock@60006000 {
compatible = "nvidia,tegra124-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
nvidia,external-memory-controller = <&emc>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA124_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
osc: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <112400000>;
};
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k> <&osc>;
};
clock@60006000 {
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
timing-20400000 {
clock-frequency = <20400000>;
nvidia,parent-clock-frequency = <408000000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
clock-names = "emc-parent";
};
};
};
};

115
Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml Normal file
View File

@ -0,0 +1,115 @@
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Clock and Reset Controller
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The Clock and Reset (CAR) is the HW module responsible for muxing and gating
Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
CLKGEN provides the registers to program the PLLs. It controls most of
the clock source programming and most of the clock dividers.
CLKGEN input signals include the external clock for the reference frequency
(12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
RSTGEN provides the registers needed to control resetting of each block in
the Tegra system.
properties:
compatible:
const: nvidia,tegra124-car
reg:
maxItems: 1
'#clock-cells':
const: 1
"#reset-cells":
const: 1
nvidia,external-memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the external memory controller node
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
this timing set is used for
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
external memory clock rate in Hz
minimum: 1000000
maximum: 1000000000
nvidia,parent-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description:
rate of parent clock in Hz
minimum: 1000000
maximum: 1000000000
clocks:
items:
- description: parent clock of EMC
clock-names:
items:
- const: emc-parent
required:
- clock-frequency
- nvidia,parent-clock-frequency
- clocks
- clock-names
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- '#clock-cells'
- "#reset-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
car: clock-controller@60006000 {
compatible = "nvidia,tegra124-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb-controller@c5004000 {
compatible = "nvidia,tegra20-ehci";
reg = <0xc5004000 0x4000>;
clocks = <&car TEGRA124_CLK_USB2>;
resets = <&car TEGRA124_CLK_USB2>;
};

63
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
View File

@ -1,63 +0,0 @@
NVIDIA Tegra20 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra20-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra20-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra20-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA20_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
osc: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <12000000>;
};
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k> <&osc>;
};
};

69
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml Normal file
View File

@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Clock and Reset Controller
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The Clock and Reset (CAR) is the HW module responsible for muxing and gating
Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
CLKGEN provides the registers to program the PLLs. It controls most of
the clock source programming and most of the clock dividers.
CLKGEN input signals include the external clock for the reference frequency
(12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
RSTGEN provides the registers needed to control resetting of each block in
the Tegra system.
properties:
compatible:
enum:
- nvidia,tegra20-car
- nvidia,tegra30-car
- nvidia,tegra114-car
- nvidia,tegra210-car
reg:
maxItems: 1
'#clock-cells':
const: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- '#clock-cells'
- "#reset-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
car: clock-controller@60006000 {
compatible = "nvidia,tegra20-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb-controller@c5004000 {
compatible = "nvidia,tegra20-ehci";
reg = <0xc5004000 0x4000>;
clocks = <&car TEGRA20_CLK_USB2>;
resets = <&car TEGRA20_CLK_USB2>;
};

56
Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt
View File

@ -1,56 +0,0 @@
NVIDIA Tegra210 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra210-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra210-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra210-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA210_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k>;
};
};

63
Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
View File

@ -1,63 +0,0 @@
NVIDIA Tegra30 Clock And Reset Controller
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
for muxing and gating Tegra's clocks, and setting their rates.
Required properties :
- compatible : Should be "nvidia,tegra30-car"
- reg : Should contain CAR registers location and length
- clocks : Should contain phandle and clock specifiers for two clocks:
the 32 KHz "32k_in", and the board-specific oscillator "osc".
- #clock-cells : Should be 1.
In clock consumers, this cell represents the clock ID exposed by the
CAR. The assignments may be found in header file
<dt-bindings/clock/tegra30-car.h>.
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
Example SoC include file:
/ {
tegra_car: clock {
compatible = "nvidia,tegra30-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
usb@c5004000 {
clocks = <&tegra_car TEGRA30_CLK_USB2>;
};
};
Example board file:
/ {
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
osc: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <12000000>;
};
clk_32k: clock@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
&tegra_car {
clocks = <&clk_32k> <&osc>;
};
};

8
Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
View File

@ -202,11 +202,11 @@ Example 2 (MT8173 SoC):
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA57SEL>,
clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_b>;
@ -214,11 +214,11 @@ Example 2 (MT8173 SoC):
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&infracfg CLK_INFRA_CA57SEL>,
clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_b>;

74
Documentation/devicetree/bindings/dvfs/performance-domain.yaml Normal file
View File

@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic performance domains
maintainers:
- Sudeep Holla <sudeep.holla@arm.com>
description: |+
This binding is intended for performance management of groups of devices or
CPUs that run in the same performance domain. Performance domains must not
be confused with power domains. A performance domain is defined by a set
of devices that always have to run at the same performance level. For a given
performance domain, there is a single point of control that affects all the
devices in the domain, making it impossible to set the performance level of
an individual device in the domain independently from other devices in
that domain. For example, a set of CPUs that share a voltage domain, and
have a common frequency control, is said to be in the same performance
domain.
This device tree binding can be used to bind performance domain consumer
devices with their performance domains provided by performance domain
providers. A performance domain provider can be represented by any node in
the device tree and can provide one or more performance domains. A consumer
node can refer to the provider by a phandle and a set of phandle arguments
(so called performance domain specifiers) of length specified by the
\#performance-domain-cells property in the performance domain provider node.
select: true
properties:
"#performance-domain-cells":
description:
Number of cells in a performance domain specifier. Typically 0 for nodes
representing a single performance domain and 1 for nodes providing
multiple performance domains (e.g. performance controllers), but can be
any value as specified by device tree binding documentation of particular
provider.
enum: [ 0, 1 ]
performance-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 1
description:
A phandle and performance domain specifier as defined by bindings of the
performance controller/provider specified by phandle.
additionalProperties: true
examples:
- |
performance: performance-controller@12340000 {
compatible = "qcom,cpufreq-hw";
reg = <0x12340000 0x1000>;
#performance-domain-cells = <1>;
};
// The node above defines a performance controller that is a performance
// domain provider and expects one cell as its phandle argument.
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
performance-domains = <&performance 1>;
};
};

1
Documentation/devicetree/bindings/firmware/qcom,scm.txt
View File

@ -12,6 +12,7 @@ Required properties:
* "qcom,scm-ipq4019"
* "qcom,scm-ipq806x"
* "qcom,scm-ipq8074"
* "qcom,scm-mdm9607"
* "qcom,scm-msm8660"
* "qcom,scm-msm8916"
* "qcom,scm-msm8960"

48
Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml Normal file
View File

@ -0,0 +1,48 @@
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwlock/allwinner,sun6i-a31-hwspinlock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SUN6I hardware spinlock driver for Allwinner sun6i compatible SoCs
maintainers:
- Wilken Gottwalt <wilken.gottwalt@posteo.net>
description:
The hardware unit provides semaphores between the ARM cores and the embedded
companion core on the SoC.
properties:
compatible:
const: allwinner,sun6i-a31-hwspinlock
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- clocks
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
hwlock@1c18000 {
compatible = "allwinner,sun6i-a31-hwspinlock";
reg = <0x01c18000 0x1000>;
clocks = <&ccu CLK_BUS_SPINLOCK>;
resets = <&ccu RST_BUS_SPINLOCK>;
};
...

2
Documentation/devicetree/bindings/i2c/i2c-at91.txt
View File

@ -73,7 +73,7 @@ i2c0: i2c@f8034600 {
pinctrl-0 = <&pinctrl_i2c0>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
wm8731: wm8731@1a {
compatible = "wm8731";

11
Documentation/devicetree/bindings/iommu/arm,smmu.yaml
View File

@ -54,8 +54,14 @@ properties:
- const: arm,mmu-500
- description: NVIDIA SoCs that program two ARM MMU-500s identically
items:
- description: NVIDIA SoCs that require memory controller interaction
and may program multiple ARM MMU-500s identically with the memory
controller interleaving translations between multiple instances
for improved performance.
items:
- enum:
- nvidia,tegra194-smmu
- const: nvidia,tegra194-smmu
- const: nvidia,tegra186-smmu
- const: nvidia,smmu-500
- items:
- const: arm,mmu-500
@ -165,10 +171,11 @@ allOf:
contains:
enum:
- nvidia,tegra194-smmu
- nvidia,tegra186-smmu
then:
properties:
reg:
minItems: 2
minItems: 1
maxItems: 2
else:
properties:

4
Documentation/devicetree/bindings/net/stm32-dwmac.yaml
View File

@ -52,10 +52,11 @@ properties:
- description: MAC RX clock
- description: For MPU family, used for power mode
- description: For MPU family, used for PHY without quartz
- description: PTP clock
clock-names:
minItems: 3
maxItems: 5
maxItems: 6
contains:
enum:
- stmmaceth
@ -63,6 +64,7 @@ properties:
- mac-clk-rx
- ethstp
- eth-ck
- ptp_ref
st,syscon:
$ref: "/schemas/types.yaml#/definitions/phandle-array"

3
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
View File

@ -38,6 +38,9 @@ Optional properties:
The regulator will be enabled when initializing the PCIe host and
disabled either as part of the init process or when shutting down the
host.
- vph-supply: Should specify the regulator in charge of VPH one of the three
PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage
supplies.
Additional required properties for imx6sx-pcie:
- clock names: Must include the following additional entries:

100
Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml Normal file
View File

@ -0,0 +1,100 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx PCI controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: PCI host controller found in the Intel IXP4xx SoC series.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
properties:
compatible:
items:
- enum:
- intel,ixp42x-pci
- intel,ixp43x-pci
description: The two supported variants are ixp42x and ixp43x,
though more variants may exist.
reg:
items:
- description: IXP4xx-specific registers
interrupts:
items:
- description: Main PCI interrupt
- description: PCI DMA interrupt 1
- description: PCI DMA interrupt 2
ranges:
maxItems: 2
description: Typically one memory range of 64MB and one IO
space range of 64KB.
dma-ranges:
maxItems: 1
description: The DMA range tells the PCI host which addresses
the RAM is at. It can map only 64MB so if the RAM is bigger
than 64MB the DMA access has to be restricted to these
addresses.
"#interrupt-cells": true
interrupt-map: true
interrupt-map-mask:
items:
- const: 0xf800
- const: 0
- const: 0
- const: 7
required:
- compatible
- reg
- dma-ranges
- "#interrupt-cells"
- interrupt-map
- interrupt-map-mask
unevaluatedProperties: false
examples:
- |
pci@c0000000 {
compatible = "intel,ixp43x-pci";
reg = <0xc0000000 0x1000>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges =
<0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
<0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
dma-ranges =
<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
<0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
<0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
<0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
<0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
<0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
<0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
<0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
<0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
<0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
<0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
<0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
<0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */
};

12
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
View File

@ -42,22 +42,22 @@ Required properties (child nodes):
Examples:
cpm_comphy: phy@120000 {
CP11X_LABEL(comphy): phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cpm_syscon0>;
clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
<&CP110_LABEL(clk) 1 18>;
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
<&CP11X_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
cpm_comphy0: phy@0 {
CP11X_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cpm_comphy1: phy@1 {
CP11X_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};

11
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
View File

@ -30,9 +30,6 @@ properties:
"#clock-cells":
const: 0
"#phy-cells":
const: 0
clocks:
maxItems: 1
@ -120,7 +117,6 @@ required:
- reg
- clock-output-names
- "#clock-cells"
- "#phy-cells"
- host-port
- otg-port
@ -131,26 +127,25 @@ examples:
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
u2phy0: usb2-phy@e450 {
u2phy0: usb2phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
clocks = <&cru SCLK_USB2PHY0_REF>;
clock-names = "phyclk";
clock-output-names = "clk_usbphy0_480m";
#clock-cells = <0>;
#phy-cells = <0>;
u2phy0_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "linestate";
#phy-cells = <0>;
};
u2phy0_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "otg-bvalid", "otg-id", "linestate";
#phy-cells = <0>;
};
};

13
Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
View File

@ -25,7 +25,9 @@ properties:
compatible:
enum:
- fsl,imx7d-gpc
- fsl,imx8mn-gpc
- fsl,imx8mq-gpc
- fsl,imx8mm-gpc
reg:
maxItems: 1
@ -54,6 +56,7 @@ properties:
Power domain index. Valid values are defined in
include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
maxItems: 1
clocks:
@ -66,6 +69,16 @@ properties:
power-supply: true
resets:
description: |
A number of phandles to resets that need to be asserted during
power-up sequencing of the domain. The resets belong to devices
located inside the power domain, which need to be held in reset
across the power-up sequence. So no means to specify what each
reset is in a generic power-domain binding.
minItems: 1
maxItems: 4
required:
- '#power-domain-cells'
- reg

2
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
View File

@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- qcom,mdm9607-rpmpd
- qcom,msm8916-rpmpd
- qcom,msm8939-rpmpd
- qcom,msm8976-rpmpd
@ -26,6 +27,7 @@ properties:
- qcom,sdm660-rpmpd
- qcom,sc7180-rpmhpd
- qcom,sc7280-rpmhpd
- qcom,sc8180x-rpmhpd
- qcom,sdm845-rpmhpd
- qcom,sdx55-rpmhpd
- qcom,sm8150-rpmhpd

63
Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml Normal file
View File

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas RZ/G2L System Controller (SYSC)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The RZ/G2L System Controller (SYSC) performs system control of the LSI and
supports following functions,
- External terminal state capture function
- 34-bit address space access function
- Low power consumption control
- WDT stop control
properties:
compatible:
enum:
- renesas,r9a07g044-sysc # RZ/G2{L,LC}
reg:
maxItems: 1
interrupts:
items:
- description: CA55/CM33 Sleep/Software Standby Mode request interrupt
- description: CA55 Software Standby Mode release request interrupt
- description: CM33 Software Standby Mode release request interrupt
- description: CA55 ACE Asynchronous Bridge Master/Slave interface deny request interrupt
interrupt-names:
items:
- const: lpm_int
- const: ca55stbydone_int
- const: cm33stbyr_int
- const: ca55_deny
required:
- compatible
- reg
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g044-sysc";
reg = <0x11020000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int",
"ca55_deny";
};

248
Documentation/devicetree/bindings/power/rockchip,power-controller.yaml Normal file
View File

@ -0,0 +1,248 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip Power Domains
maintainers:
- Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |
Rockchip processors include support for multiple power domains
which can be powered up/down by software based on different
application scenarios to save power.
Power domains contained within power-controller node are
generic power domain providers documented in
Documentation/devicetree/bindings/power/power-domain.yaml.
IP cores belonging to a power domain should contain a
"power-domains" property that is a phandle for the
power domain node representing the domain.
properties:
$nodename:
const: power-controller
compatible:
enum:
- rockchip,px30-power-controller
- rockchip,rk3036-power-controller
- rockchip,rk3066-power-controller
- rockchip,rk3128-power-controller
- rockchip,rk3188-power-controller
- rockchip,rk3228-power-controller
- rockchip,rk3288-power-controller
- rockchip,rk3328-power-controller
- rockchip,rk3366-power-controller
- rockchip,rk3368-power-controller
- rockchip,rk3399-power-controller
- rockchip,rk3568-power-controller
"#power-domain-cells":
const: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
required:
- compatible
- "#power-domain-cells"
additionalProperties: false
patternProperties:
"^power-domain@[0-9a-f]+$":
$ref: "#/$defs/pd-node"
unevaluatedProperties: false
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^power-domain@[0-9a-f]+$":
$ref: "#/$defs/pd-node"
unevaluatedProperties: false
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^power-domain@[0-9a-f]+$":
$ref: "#/$defs/pd-node"
unevaluatedProperties: false
properties:
"#power-domain-cells":
const: 0
$defs:
pd-node:
type: object
description: |
Represents the power domains within the power controller node.
properties:
reg:
maxItems: 1
description: |
Power domain index. Valid values are defined in
"include/dt-bindings/power/px30-power.h"
"include/dt-bindings/power/rk3036-power.h"
"include/dt-bindings/power/rk3066-power.h"
"include/dt-bindings/power/rk3128-power.h"
"include/dt-bindings/power/rk3188-power.h"
"include/dt-bindings/power/rk3228-power.h"
"include/dt-bindings/power/rk3288-power.h"
"include/dt-bindings/power/rk3328-power.h"
"include/dt-bindings/power/rk3366-power.h"
"include/dt-bindings/power/rk3368-power.h"
"include/dt-bindings/power/rk3399-power.h"
"include/dt-bindings/power/rk3568-power.h"
clocks:
minItems: 1
maxItems: 30
description: |
A number of phandles to clocks that need to be enabled
while power domain switches state.
pm_qos:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
A number of phandles to qos blocks which need to be saved and restored
while power domain switches state.
"#power-domain-cells":
enum: [0, 1]
description:
Must be 0 for nodes representing a single PM domain and 1 for nodes
providing multiple PM domains.
required:
- reg
- "#power-domain-cells"
examples:
- |
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/power/rk3399-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
qos_hdcp: qos@ffa90000 {
compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa90000 0x0 0x20>;
};
qos_iep: qos@ffa98000 {
compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffa98000 0x0 0x20>;
};
qos_rga_r: qos@ffab0000 {
compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffab0000 0x0 0x20>;
};
qos_rga_w: qos@ffab0080 {
compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffab0080 0x0 0x20>;
};
qos_video_m0: qos@ffab8000 {
compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffab8000 0x0 0x20>;
};
qos_video_m1_r: qos@ffac0000 {
compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffac0000 0x0 0x20>;
};
qos_video_m1_w: qos@ffac0080 {
compatible = "rockchip,rk3399-qos", "syscon";
reg = <0x0 0xffac0080 0x0 0x20>;
};
power-management@ff310000 {
compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff310000 0x0 0x1000>;
power-controller {
compatible = "rockchip,rk3399-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* These power domains are grouped by VD_CENTER */
power-domain@RK3399_PD_IEP {
reg = <RK3399_PD_IEP>;
clocks = <&cru ACLK_IEP>,
<&cru HCLK_IEP>;
pm_qos = <&qos_iep>;
#power-domain-cells = <0>;
};
power-domain@RK3399_PD_RGA {
reg = <RK3399_PD_RGA>;
clocks = <&cru ACLK_RGA>,
<&cru HCLK_RGA>;
pm_qos = <&qos_rga_r>,
<&qos_rga_w>;
#power-domain-cells = <0>;
};
power-domain@RK3399_PD_VCODEC {
reg = <RK3399_PD_VCODEC>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video_m0>;
#power-domain-cells = <0>;
};
power-domain@RK3399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
<&cru HCLK_VDU>;
pm_qos = <&qos_video_m1_r>,
<&qos_video_m1_w>;
#power-domain-cells = <0>;
};
power-domain@RK3399_PD_VIO {
reg = <RK3399_PD_VIO>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3399_PD_HDCP {
reg = <RK3399_PD_HDCP>;
clocks = <&cru ACLK_HDCP>,
<&cru HCLK_HDCP>,
<&cru PCLK_HDCP>;
pm_qos = <&qos_hdcp>;
#power-domain-cells = <0>;
};
};
};
};
};

91
Documentation/devicetree/bindings/power/supply/charger-manager.txt
View File

@ -1,91 +0,0 @@
charger-manager bindings
~~~~~~~~~~~~~~~~~~~~~~~~
Required properties :
- compatible : "charger-manager"
- <>-supply : for regulator consumer, named according to cm-regulator-name
- cm-chargers : name of chargers
- cm-fuel-gauge : name of battery fuel gauge
- subnode <regulator> :
- cm-regulator-name : name of charger regulator
- subnode <cable> :
- cm-cable-name : name of charger cable - one of USB, USB-HOST,
SDP, DCP, CDP, ACA, FAST-CHARGER, SLOW-CHARGER, WPT,
PD, DOCK, JIG, or MECHANICAL
- cm-cable-extcon : name of extcon dev
(optional) - cm-cable-min : minimum current of cable
(optional) - cm-cable-max : maximum current of cable
Optional properties :
- cm-name : charger manager's name (default : "battery")
- cm-poll-mode : polling mode - 0 for disabled, 1 for always, 2 for when
external power is connected, or 3 for when charging. If not present,
then polling is disabled
- cm-poll-interval : polling interval (in ms)
- cm-battery-stat : battery status - 0 for battery always present, 1 for no
battery, 2 to check presence via fuel gauge, or 3 to check presence
via charger
- cm-fullbatt-vchkdrop-volt : voltage drop (in uV) before restarting charging
- cm-fullbatt-voltage : voltage (in uV) of full battery
- cm-fullbatt-soc : state of charge to consider as full battery
- cm-fullbatt-capacity : capcity (in uAh) to consider as full battery
- cm-thermal-zone : name of external thermometer's thermal zone
- cm-battery-* : threshold battery temperature for charging
-cold : critical cold temperature of battery for charging
-cold-in-minus : flag that cold temperature is in minus degrees
-hot : critical hot temperature of battery for charging
-temp-diff : temperature difference to allow recharging
- cm-dis/charging-max = limits of charging duration
Deprecated properties:
- cm-num-chargers
- cm-fullbatt-vchkdrop-ms
Example :
charger-manager@0 {
compatible = "charger-manager";
chg-reg-supply = <&charger_regulator>;
cm-name = "battery";
/* Always polling ON : 30s */
cm-poll-mode = <1>;
cm-poll-interval = <30000>;
cm-fullbatt-vchkdrop-volt = <150000>;
cm-fullbatt-soc = <100>;
cm-battery-stat = <3>;
cm-chargers = "charger0", "charger1", "charger2";
cm-fuel-gauge = "fuelgauge0";
cm-thermal-zone = "thermal_zone.1"
/* in deci centigrade */
cm-battery-cold = <50>;
cm-battery-cold-in-minus;
cm-battery-hot = <800>;
cm-battery-temp-diff = <100>;
/* Allow charging for 5hr */
cm-charging-max = <18000000>;
/* Allow discharging for 2hr */
cm-discharging-max = <7200000>;
regulator@0 {
cm-regulator-name = "chg-reg";
cable@0 {
cm-cable-name = "USB";
cm-cable-extcon = "extcon-dev.0";
cm-cable-min = <475000>;
cm-cable-max = <500000>;
};
cable@1 {
cm-cable-name = "SDP";
cm-cable-extcon = "extcon-dev.0";
cm-cable-min = <650000>;
cm-cable-max = <675000>;
};
};
};

215
Documentation/devicetree/bindings/power/supply/charger-manager.yaml Normal file
View File

@ -0,0 +1,215 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/supply/charger-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Charger Manager
maintainers:
- Sebastian Reichel <sre@kernel.org>
description: |
Binding for the legacy charger manager driver.
Please do not use for new products.
properties:
compatible:
const: charger-manager
cm-chargers:
description: name of chargers
$ref: /schemas/types.yaml#/definitions/string-array
cm-num-chargers:
$ref: /schemas/types.yaml#/definitions/uint32
deprecated: true
cm-fuel-gauge:
description: name of battery fuel gauge
$ref: /schemas/types.yaml#/definitions/string
cm-name:
description: name of the charger manager
default: battery
$ref: /schemas/types.yaml#/definitions/string
cm-poll-mode:
description: polling mode
default: 0
enum:
- 0 # disabled
- 1 # always
- 2 # when external power is connected
- 3 # when charging
cm-poll-interval:
description: polling interval (in ms)
$ref: /schemas/types.yaml#/definitions/uint32
cm-battery-stat:
description: battery status
enum:
- 0 # battery always present
- 1 # no battery
- 2 # check presence via fuel gauge
- 3 # check presence via charger
cm-fullbatt-vchkdrop-volt:
description: voltage drop before restarting charging in uV
$ref: /schemas/types.yaml#/definitions/uint32
cm-fullbatt-vchkdrop-ms:
deprecated: true
cm-fullbatt-voltage:
description: voltage of full battery in uV
$ref: /schemas/types.yaml#/definitions/uint32
cm-fullbatt-soc:
description: state of charge to consider as full battery in %
$ref: /schemas/types.yaml#/definitions/uint32
cm-fullbatt-capacity:
description: capcity to consider as full battery in uAh
$ref: /schemas/types.yaml#/definitions/uint32
cm-thermal-zone:
description: name of external thermometer's thermal zone
$ref: /schemas/types.yaml#/definitions/string
cm-discharging-max:
description: limits of discharging duration in ms
$ref: /schemas/types.yaml#/definitions/uint32
cm-charging-max:
description: limits of charging duration in ms
$ref: /schemas/types.yaml#/definitions/uint32
cm-battery-cold:
description: critical cold temperature of battery for charging in deci-degree celsius
$ref: /schemas/types.yaml#/definitions/uint32
cm-battery-cold-in-minus:
description: if set cm-battery-cold temperature is in minus degrees
type: boolean
cm-battery-hot:
description: critical hot temperature of battery for charging in deci-degree celsius
$ref: /schemas/types.yaml#/definitions/uint32
cm-battery-temp-diff:
description: temperature difference to allow recharging in deci-degree celsius
$ref: /schemas/types.yaml#/definitions/uint32
patternProperties:
"-supply$":
description: regulator consumer, named according to cm-regulator-name
$ref: /schemas/types.yaml#/definitions/phandle
"^regulator[@-][0-9]$":
type: object
properties:
cm-regulator-name:
description: name of charger regulator
$ref: /schemas/types.yaml#/definitions/string
required:
- cm-regulator-name
additionalProperties: false
patternProperties:
"^cable[@-][0-9]$":
type: object
properties:
cm-cable-name:
description: name of charger cable
enum:
- USB
- USB-HOST
- SDP
- DCP
- CDP
- ACA
- FAST-CHARGER
- SLOW-CHARGER
- WPT
- PD
- DOCK
- JIG
- MECHANICAL
cm-cable-extcon:
description: name of extcon dev
$ref: /schemas/types.yaml#/definitions/string
cm-cable-min:
description: minimum current of cable in uA
$ref: /schemas/types.yaml#/definitions/uint32
cm-cable-max:
description: maximum current of cable in uA
$ref: /schemas/types.yaml#/definitions/uint32
required:
- cm-cable-name
- cm-cable-extcon
additionalProperties: false
required:
- compatible
- cm-chargers
- cm-fuel-gauge
additionalProperties: false
examples:
- |
charger-manager {
compatible = "charger-manager";
chg-reg-supply = <&charger_regulator>;
cm-name = "battery";
/* Always polling ON : 30s */
cm-poll-mode = <1>;
cm-poll-interval = <30000>;
cm-fullbatt-vchkdrop-volt = <150000>;
cm-fullbatt-soc = <100>;
cm-battery-stat = <3>;
cm-chargers = "charger0", "charger1", "charger2";
cm-fuel-gauge = "fuelgauge0";
cm-thermal-zone = "thermal_zone.1";
/* in deci centigrade */
cm-battery-cold = <50>;
cm-battery-cold-in-minus;
cm-battery-hot = <800>;
cm-battery-temp-diff = <100>;
/* Allow charging for 5hr */
cm-charging-max = <18000000>;
/* Allow discharging for 2hr */
cm-discharging-max = <7200000>;
regulator-0 {
cm-regulator-name = "chg-reg";
cable-0 {
cm-cable-name = "USB";
cm-cable-extcon = "extcon-dev.0";
cm-cable-min = <475000>;
cm-cable-max = <500000>;
};
cable-1 {
cm-cable-name = "SDP";
cm-cable-extcon = "extcon-dev.0";
cm-cable-min = <650000>;
cm-cable-max = <675000>;
};
};
};

2
Documentation/devicetree/bindings/power/supply/maxim,max17040.yaml
View File

@ -89,7 +89,7 @@ examples:
reg = <0x36>;
maxim,alert-low-soc-level = <10>;
interrupt-parent = <&gpio7>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};

54
Documentation/devicetree/bindings/power/supply/richtek,rt5033-battery.yaml Normal file
View File

@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/power/supply/richtek,rt5033-battery.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Richtek RT5033 PMIC Fuel Gauge
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
allOf:
- $ref: power-supply.yaml#
properties:
compatible:
const: richtek,rt5033-battery
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
battery@35 {
compatible = "richtek,rt5033-battery";
reg = <0x35>;
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
battery@35 {
compatible = "richtek,rt5033-battery";
reg = <0x35>;
interrupt-parent = <&msmgpio>;
interrupts = <121 IRQ_TYPE_EDGE_FALLING>;
};
};

3
Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
View File

@ -24,6 +24,9 @@ properties:
- items:
- const: allwinner,sun8i-a83t-pwm
- const: allwinner,sun8i-h3-pwm
- items:
- const: allwinner,sun8i-v3s-pwm
- const: allwinner,sun7i-a20-pwm
- items:
- const: allwinner,sun50i-a64-pwm
- const: allwinner,sun5i-a13-pwm

51
Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
View File

@ -1,51 +0,0 @@
TI SOC ECAP based APWM controller
Required properties:
- compatible: Must be "ti,<soc>-ecap".
for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap";
for am654 - compatible = "ti,am654-ecap", "ti,am3352-ecap";
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
the cells format. The PWM channel index ranges from 0 to 4. The only third
cell flag supported by this binding is PWM_POLARITY_INVERTED.
- reg: physical base address and size of the registers map.
Optional properties:
- clocks: Handle to the ECAP's functional clock.
- clock-names: Must be set to "fck".
Example:
ecap0: ecap@48300100 { /* ECAP on am33xx */
compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
};
ecap0: ecap@48300100 { /* ECAP on am4372 */
compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
ti,hwmods = "ecap0";
clocks = <&l4ls_gclk>;
clock-names = "fck";
};
ecap0: ecap@1f06000 { /* ECAP on da850 */
compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x1f06000 0x80>;
};
ecap0: ecap@4843e100 {
compatible = "ti,dra746-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x4843e100 0x80>;
clocks = <&l4_root_clk_div>;
clock-names = "fck";
};

64
Documentation/devicetree/bindings/pwm/pwm-tiecap.yaml Normal file
View File

@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm-tiecap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI SOC ECAP based APWM controller
maintainers:
- Vignesh R <vigneshr@ti.com>
allOf:
- $ref: pwm.yaml#
properties:
compatible:
oneOf:
- const: ti,am3352-ecap
- items:
- enum:
- ti,da850-ecap
- ti,am4372-ecap
- ti,dra746-ecap
- ti,k2g-ecap
- ti,am654-ecap
- ti,am64-ecap
- const: ti,am3352-ecap
reg:
maxItems: 1
"#pwm-cells":
const: 3
description: |
See pwm.yaml in this directory for a description of the cells format.
The only third cell flag supported by this binding is PWM_POLARITY_INVERTED.
clock-names:
const: fck
clocks:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- "#pwm-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
ecap0: pwm@48300100 { /* ECAP on am33xx */
compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
};

50
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
View File

@ -1,50 +0,0 @@
TI SOC EHRPWM based PWM controller
Required properties:
- compatible: Must be "ti,<soc>-ehrpwm".
for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
for am654 - compatible = "ti,am654-ehrpwm", "ti-am3352-ehrpwm";
for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
the cells format. The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED.
- reg: physical base address and size of the registers map.
Optional properties:
- clocks: Handle to the PWM's time-base and functional clock.
- clock-names: Must be set to "tbclk" and "fck".
Example:
ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x100>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
};
ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */
compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
ti,hwmods = "ehrpwm0";
};
ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */
compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x1f00000 0x2000>;
};
ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */
compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x4843e200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
clock-names = "tbclk", "fck";
};

65
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.yaml Normal file
View File

@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm-tiehrpwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI SOC EHRPWM based PWM controller
maintainers:
- Vignesh R <vigneshr@ti.com>
allOf:
- $ref: pwm.yaml#
properties:
compatible:
oneOf:
- const: ti,am3352-ehrpwm
- items:
- enum:
- ti,da850-ehrpwm
- ti,am4372-ehrpwm
- ti,dra746-ehrpwm
- ti,am654-ehrpwm
- ti,am64-epwm
- const: ti,am3352-ehrpwm
reg:
maxItems: 1
"#pwm-cells":
const: 3
description: |
See pwm.yaml in this directory for a description of the cells format.
The only third cell flag supported by this binding is PWM_POLARITY_INVERTED.
clock-names:
items:
- const: tbclk
- const: fck
clocks:
maxItems: 2
power-domains:
maxItems: 1
required:
- compatible
- reg
- "#pwm-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
compatible = "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x100>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
};

12
Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml
View File

@ -17,7 +17,11 @@ properties:
enum:
- fsl,imx8mq-cm4
- fsl,imx8mm-cm4
- fsl,imx8mn-cm7
- fsl,imx8mp-cm7
- fsl,imx8ulp-cm33
- fsl,imx7d-cm4
- fsl,imx7ulp-cm4
- fsl,imx6sx-cm4
clocks:
@ -49,10 +53,14 @@ properties:
minItems: 1
maxItems: 32
fsl,auto-boot:
$ref: /schemas/types.yaml#/definitions/flag
description:
Indicate whether need to load the default firmware and start the remote
processor automatically.
required:
- compatible
- clocks
- syscon
additionalProperties: false

228
Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
View File

@ -1,228 +0,0 @@
Qualcomm ADSP Peripheral Image Loader
This document defines the binding for a component that loads and boots firmware
on the Qualcomm ADSP Hexagon core.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,msm8974-adsp-pil"
"qcom,msm8996-adsp-pil"
"qcom,msm8996-slpi-pil"
"qcom,msm8998-adsp-pas"
"qcom,msm8998-slpi-pas"
"qcom,qcs404-adsp-pas"
"qcom,qcs404-cdsp-pas"
"qcom,qcs404-wcss-pas"
"qcom,sc7180-mpss-pas"
"qcom,sdm845-adsp-pas"
"qcom,sdm845-cdsp-pas"
"qcom,sdx55-mpss-pas"
"qcom,sm8150-adsp-pas"
"qcom,sm8150-cdsp-pas"
"qcom,sm8150-mpss-pas"
"qcom,sm8150-slpi-pas"
"qcom,sm8250-adsp-pas"
"qcom,sm8250-cdsp-pas"
"qcom,sm8250-slpi-pas"
"qcom,sm8350-adsp-pas"
"qcom,sm8350-cdsp-pas"
"qcom,sm8350-slpi-pas"
"qcom,sm8350-mpss-pas"
- interrupts-extended:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the interrupts that match interrupt-names
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: The interrupts needed depends on the compatible
string:
qcom,msm8974-adsp-pil:
qcom,msm8996-adsp-pil:
qcom,msm8996-slpi-pil:
qcom,msm8998-adsp-pas:
qcom,msm8998-slpi-pas:
qcom,qcs404-adsp-pas:
qcom,qcs404-cdsp-pas:
qcom,sdm845-adsp-pas:
qcom,sdm845-cdsp-pas:
qcom,sm8150-adsp-pas:
qcom,sm8150-cdsp-pas:
qcom,sm8150-slpi-pas:
qcom,sm8250-adsp-pas:
qcom,sm8250-cdsp-pas:
qcom,sm8250-slpi-pas:
qcom,sm8350-adsp-pas:
qcom,sm8350-cdsp-pas:
qcom,sm8350-slpi-pas:
must be "wdog", "fatal", "ready", "handover", "stop-ack"
qcom,qcs404-wcss-pas:
qcom,sc7180-mpss-pas:
qcom,sdx55-mpss-pas:
qcom,sm8150-mpss-pas:
qcom,sm8350-mpss-pas:
must be "wdog", "fatal", "ready", "handover", "stop-ack",
"shutdown-ack"
- firmware-name:
Usage: optional
Value type: <string>
Definition: must list the relative firmware image path for the
Hexagon Core.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the xo clock and optionally aggre2 clock to be
held on behalf of the booting Hexagon core
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "xo" and optionally include "aggre2"
- cx-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulator to be held on behalf of the
booting Hexagon core
- px-supply:
Usage: required
Value type: <phandle>
Definition: reference to the px regulator to be held on behalf of the
booting Hexagon core
- power-domains:
Usage: required
Value type: <phandle>
Definition: reference to power-domains that match the power-domain-names
- power-domain-names:
Usage: required
Value type: <stringlist>
Definition: The power-domains needed depend on the compatible string:
qcom,msm8974-adsp-pil:
qcom,msm8996-adsp-pil:
qcom,msm8998-adsp-pas:
must be "cx"
qcom,msm8996-slpi-pil:
must be "ss_cx"
qcom,msm8998-slpi-pas:
must be "ssc_cx"
qcom,qcs404-adsp-pas:
must be "lpi_cx"
qcom,qcs404-cdsp-pas:
qcom,qcs404-wcss-pas:
must be "mx"
qcom,sdm845-adsp-pas:
qcom,sdm845-cdsp-pas:
qcom,sm8150-adsp-pas:
qcom,sm8150-cdsp-pas:
qcom,sm8250-cdsp-pas:
qcom,sm8350-cdsp-pas:
must be "cx", "load_state"
qcom,sc7180-mpss-pas:
qcom,sm8150-mpss-pas:
qcom,sm8350-mpss-pas:
must be "cx", "load_state", "mss"
qcom,sdx55-mpss-pas:
must be "cx", "mss"
qcom,sm8250-adsp-pas:
qcom,sm8350-adsp-pas:
qcom,sm8150-slpi-pas:
qcom,sm8250-slpi-pas:
qcom,sm8350-slpi-pas:
must be "lcx", "lmx", "load_state"
- memory-region:
Usage: required
Value type: <phandle>
Definition: reference to the reserved-memory for the ADSP
- qcom,smem-states:
Usage: required
Value type: <phandle>
Definition: reference to the smem state for requesting the ADSP to
shut down
- qcom,smem-state-names:
Usage: required
Value type: <stringlist>
Definition: must be "stop"
= SUBNODES
The adsp node may have an subnode named either "smd-edge" or "glink-edge" that
describes the communication edge, channels and devices related to the ADSP.
See ../soc/qcom/qcom,smd.txt and ../soc/qcom/qcom,glink.txt for details on how
to describe these.
= EXAMPLE
The following example describes the resources needed to boot control the
ADSP, as it is found on MSM8974 boards.
adsp {
compatible = "qcom,msm8974-adsp-pil";
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
clocks = <&rpmcc RPM_CXO_CLK>;
clock-names = "xo";
cx-supply = <&pm8841_s2>;
memory-region = <&adsp_region>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
smd-edge {
interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 8>;
qcom,smd-edge = <1>;
};
};
The following example describes the resources needed to boot control the
SLPI, as it is found on MSM8996 boards.
slpi {
compatible = "qcom,msm8996-slpi-pil";
interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
clocks = <&rpmcc MSM8996_RPM_SMD_XO_CLK_SRC>,
<&rpmcc MSM8996_RPM_SMD_AGGR2_NOC_CLK>;
clock-names = "xo", "aggre2";
cx-supply = <&pm8994_l26>;
px-supply = <&pm8994_lvs2>;
memory-region = <&slpi_region>;
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
};

547
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml Normal file
View File

@ -0,0 +1,547 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,adsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm ADSP Peripheral Image Loader binding
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
This document defines the binding for a component that loads and boots
firmware on the Qualcomm ADSP Hexagon core.
properties:
compatible:
enum:
- qcom,msm8974-adsp-pil
- qcom,msm8996-adsp-pil
- qcom,msm8996-slpi-pil
- qcom,msm8998-adsp-pas
- qcom,msm8998-slpi-pas
- qcom,qcs404-adsp-pas
- qcom,qcs404-cdsp-pas
- qcom,qcs404-wcss-pas
- qcom,sc7180-mpss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
- qcom,sdm845-adsp-pas
- qcom,sdm845-cdsp-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
- qcom,sm8150-mpss-pas
- qcom,sm8150-slpi-pas
- qcom,sm8250-adsp-pas
- qcom,sm8250-cdsp-pas
- qcom,sm8250-slpi-pas
- qcom,sm8350-adsp-pas
- qcom,sm8350-cdsp-pas
- qcom,sm8350-slpi-pas
- qcom,sm8350-mpss-pas
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 8
clock-names:
minItems: 1
maxItems: 8
interrupts:
minItems: 5
maxItems: 6
interrupt-names:
minItems: 5
maxItems: 6
resets:
minItems: 1
maxItems: 3
reset-names:
minItems: 1
maxItems: 3
cx-supply:
description: Phandle to the CX regulator
px-supply:
description: Phandle to the PX regulator
power-domains:
minItems: 1
maxItems: 3
power-domain-names:
minItems: 1
maxItems: 3
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description: Firmware name for the Hexagon core
memory-region:
maxItems: 1
description: Reference to the reserved-memory for the Hexagon core
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: States used by the AP to signal the Hexagon core
items:
- description: Stop the modem
qcom,smem-state-names:
$ref: /schemas/types.yaml#/definitions/string-array
description: The names of the state bits used for SMP2P output
items:
- const: stop
qcom,halt-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Phandle reference to a syscon representing TCSR followed by the
three offsets within syscon for q6, modem and nc halt registers.
smd-edge:
type: object
description:
Qualcomm Shared Memory subnode which represents communication edge,
channels and devices related to the ADSP.
glink-edge:
type: object
description:
Qualcomm G-Link subnode which represents communication edge, channels
and devices related to the ADSP.
required:
- compatible
- clocks
- clock-names
- interrupts
- interrupt-names
- memory-region
- qcom,smem-states
- qcom,smem-state-names
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8974-adsp-pil
- qcom,msm8996-adsp-pil
- qcom,msm8996-slpi-pil
- qcom,msm8998-adsp-pas
- qcom,qcs404-adsp-pas
- qcom,qcs404-wcss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sc8180x-mpss-pas
- qcom,sdm845-adsp-pas
- qcom,sdm845-cdsp-pas
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
- qcom,sm8150-mpss-pas
- qcom,sm8150-slpi-pas
- qcom,sm8250-adsp-pas
- qcom,sm8250-cdsp-pas
- qcom,sm8250-slpi-pas
- qcom,sm8350-adsp-pas
- qcom,sm8350-cdsp-pas
- qcom,sm8350-slpi-pas
- qcom,sm8350-mpss-pas
then:
properties:
clocks:
items:
- description: XO clock
clock-names:
items:
- const: xo
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8998-slpi-pas
then:
properties:
clocks:
items:
- description: XO clock
- description: AGGRE2 clock
clock-names:
items:
- const: xo
- const: aggre2
- if:
properties:
compatible:
contains:
enum:
- qcom,qcs404-cdsp-pas
then:
properties:
clocks:
items:
- description: XO clock
- description: SWAY clock
- description: TBU clock
- description: BIMC clock
- description: AHB AON clock
- description: Q6SS SLAVE clock
- description: Q6SS MASTER clock
- description: Q6 AXIM clock
clock-names:
items:
- const: xo
- const: sway
- const: tbu
- const: bimc
- const: ahb_aon
- const: q6ss_slave
- const: q6ss_master
- const: q6_axim
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7180-mpss-pas
then:
properties:
clocks:
items:
- description: XO clock
- description: IFACE clock
- description: BUS clock
- description: NAC clock
- description: SNOC AXI clock
- description: MNOC AXI clock
clock-names:
items:
- const: xo
- const: iface
- const: bus
- const: nav
- const: snoc_axi
- const: mnoc_axi
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8974-adsp-pil
- qcom,msm8996-adsp-pil
- qcom,msm8996-slpi-pil
- qcom,msm8998-adsp-pas
- qcom,msm8998-slpi-pas
- qcom,qcs404-adsp-pas
- qcom,qcs404-cdsp-pas
- qcom,qcs404-wcss-pas
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sdm845-adsp-pas
- qcom,sdm845-cdsp-pas
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
- qcom,sm8150-slpi-pas
- qcom,sm8250-adsp-pas
- qcom,sm8250-cdsp-pas
- qcom,sm8250-slpi-pas
- qcom,sm8350-adsp-pas
- qcom,sm8350-cdsp-pas
- qcom,sm8350-slpi-pas
then:
properties:
interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7180-mpss-pas
- qcom,sc8180x-mpss-pas
- qcom,sdx55-mpss-pas
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
then:
properties:
interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
- description: Shutdown acknowledge interrupt
interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- const: shutdown-ack
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8974-adsp-pil
then:
required:
- cx-supply
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-adsp-pil
- qcom,msm8998-adsp-pas
then:
properties:
power-domains:
items:
- description: CX power domain
power-domain-names:
items:
- const: cx
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8996-slpi-pil
- qcom,msm8998-slpi-pas
then:
properties:
power-domains:
items:
- description: SSC-CX power domain
power-domain-names:
items:
- const: ssc_cx
required:
- px-supply
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7180-mpss-pas
then:
properties:
power-domains:
items:
- description: Load State power domain
- description: CX power domain
- description: MX power domain
- description: MSS power domain
power-domain-names:
items:
- const: load_state
- const: cx
- const: mx
- const: mss
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8150-adsp-pas
- qcom,sm8150-cdsp-pas
then:
properties:
power-domains:
items:
- description: Load State power domain
- description: CX power domain
power-domain-names:
items:
- const: load_state
- const: cx
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas
then:
properties:
power-domains:
items:
- description: Load State power domain
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: load_state
- const: cx
- const: mss
- if:
properties:
compatible:
contains:
enum:
- qcom,sdx55-mpss-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MSS power domain
power-domain-names:
items:
- const: cx
- const: mss
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8180x-adsp-pas
- qcom,sc8180x-cdsp-pas
- qcom,sm8150-slpi-pas
- qcom,sm8250-adsp-pas
- qcom,sm8250-slpi-pas
- qcom,sm8350-adsp-pas
- qcom,sm8350-slpi-pas
then:
properties:
power-domains:
items:
- description: Load State power domain
- description: LCX power domain
- description: LMX power domain
power-domain-names:
items:
- const: load_state
- const: lcx
- const: lmx
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8350-cdsp-pas
then:
properties:
power-domains:
items:
- description: Load State power domain
- description: CX power domain
- description: MXC power domain
power-domain-names:
items:
- const: load_state
- const: cx
- const: mxc
- if:
properties:
compatible:
contains:
enum:
- qcom,qcs404-cdsp-pas
then:
properties:
resets:
items:
- description: CDSP restart
reset-names:
items:
- const: restart
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7180-mpss-pas
then:
properties:
resets:
items:
- description: MSS restart
- description: PDC reset
reset-names:
items:
- const: mss_restart
- const: pdc_reset
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/irq.h>
adsp {
compatible = "qcom,msm8974-adsp-pil";
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
clocks = <&rpmcc RPM_CXO_CLK>;
clock-names = "xo";
cx-supply = <&pm8841_s2>;
memory-region = <&adsp_region>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
smd-edge {
interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 8>;
qcom,smd-edge = <1>;
};
};

31
Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml
View File

@ -14,8 +14,12 @@ description: |
processor subsystems/clusters (R5FSS). The dual core cluster can be used
either in a LockStep mode providing safety/fault tolerance features or in a
Split mode providing two individual compute cores for doubling the compute
capacity. These are used together with other processors present on the SoC
to achieve various system level goals.
capacity on most SoCs. These are used together with other processors present
on the SoC to achieve various system level goals.
AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
called "Single-CPU" mode, where only Core0 is used, but with ability to use
Core1's TCMs as well.
Each Dual-Core R5F sub-system is represented as a single DTS node
representing the cluster, with a pair of child DT nodes representing
@ -33,6 +37,7 @@ properties:
- ti,am654-r5fss
- ti,j721e-r5fss
- ti,j7200-r5fss
- ti,am64-r5fss
power-domains:
description: |
@ -56,11 +61,12 @@ properties:
ti,cluster-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Configuration Mode for the Dual R5F cores within the R5F cluster.
Should be either a value of 1 (LockStep mode) or 0 (Split mode),
default is LockStep mode if omitted.
Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
most SoCs (AM65x, J721E, J7200), default is LockStep mode if omitted;
and should be either a value of 0 (Split mode) or 2 (Single-CPU mode)
on AM64x SoCs, default is Split mode if omitted.
# R5F Processor Child Nodes:
# ==========================
@ -97,6 +103,7 @@ patternProperties:
- ti,am654-r5f
- ti,j721e-r5f
- ti,j7200-r5f
- ti,am64-r5f
reg:
items:
@ -198,6 +205,20 @@ patternProperties:
unevaluatedProperties: false
if:
properties:
compatible:
enum:
- ti,am64-r5fss
then:
properties:
ti,cluster-mode:
enum: [0, 2]
else:
properties:
ti,cluster-mode:
enum: [0, 1]
required:
- compatible
- power-domains

5
Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml
View File

@ -36,6 +36,9 @@ properties:
enum:
- ti,am3356-pru # for AM335x SoC family (AM3356+ SoCs only)
- ti,am4376-pru # for AM437x SoC family (AM4376+ SoCs only)
- ti,am642-pru # for PRUs in K3 AM64x SoC family
- ti,am642-rtu # for RTUs in K3 AM64x SoC family
- ti,am642-tx-pru # for Tx_PRUs in K3 AM64x SoC family
- ti,am5728-pru # for AM57xx SoC family
- ti,k2g-pru # for 66AK2G SoC family
- ti,am654-pru # for PRUs in K3 AM65x SoC family
@ -68,6 +71,7 @@ if:
enum:
- ti,am654-rtu
- ti,j721e-rtu
- ti,am642-rtu
then:
properties:
$nodename:
@ -79,6 +83,7 @@ else:
enum:
- ti,am654-tx-pru
- ti,j721e-tx-pru
- ti,am642-tx-pru
then:
properties:
$nodename:

58
Documentation/devicetree/bindings/reset/microchip,rst.yaml Normal file
View File

@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip Sparx5 Switch Reset Controller
maintainers:
- Steen Hegelund <steen.hegelund@microchip.com>
- Lars Povlsen <lars.povlsen@microchip.com>
description: |
The Microchip Sparx5 Switch provides reset control and implements the following
functions
- One Time Switch Core Reset (Soft Reset)
properties:
$nodename:
pattern: "^reset-controller@[0-9a-f]+$"
compatible:
const: microchip,sparx5-switch-reset
reg:
items:
- description: global control block registers
reg-names:
items:
- const: gcb
"#reset-cells":
const: 1
cpu-syscon:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: syscon used to access CPU reset
required:
- compatible
- reg
- reg-names
- "#reset-cells"
- cpu-syscon
additionalProperties: false
examples:
- |
reset: reset-controller@11010008 {
compatible = "microchip,sparx5-switch-reset";
reg = <0x11010008 0x4>;
reg-names = "gcb";
#reset-cells = <1>;
cpu-syscon = <&cpu_ctrl>;
};

36
Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml Normal file
View File

@ -0,0 +1,36 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/intel,ixp46x-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP46x RNG bindings
description: |
The Intel IXP46x has a random number generator at a fixed physical
location in memory. Each read is guaranteed to provide a unique
32 bit random number.
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
compatible:
const: intel,ixp46x-rng
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
rng@70002100 {
compatible = "intel,ixp46x-rng";
reg = <0x70002100 4>;
};

22
Documentation/devicetree/bindings/rtc/epson,rx8900.txt
View File

@ -1,22 +0,0 @@
Real Time Clock driver for:
- Epson RX8900
- Micro Crystal rv8803
Required properties:
- compatible: should be: "microcrystal,rv8803" or "epson,rx8900"
- reg : the I2C address of the device for I2C
Optional properties:
- epson,vdet-disable : boolean, if present will disable voltage detector.
Should be set if no backup battery is used.
- trickle-diode-disable : boolean, if present will disable internal trickle
charger diode
Example:
rtc: rtc@32 {
compatible = "epson,rx8900"
reg = <0x32>;
epson,vdet-disable;
trickle-diode-disable;
};

49
Documentation/devicetree/bindings/rtc/epson,rx8900.yaml Normal file
View File

@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/epson,rx8900.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: EPSON RX8900 / Microcrystal RV8803 Real-Time Clock DT bindings
maintainers:
- Marek Vasut <marex@denx.de>
allOf:
- $ref: rtc.yaml#
properties:
compatible:
enum:
- epson,rx8900
- microcrystal,rv8803
reg:
maxItems: 1
epson,vdet-disable:
type: boolean
description: |
Disable voltage detector. Should be set if no backup battery is used.
trickle-diode-disable: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
epson,vdet-disable;
trickle-diode-disable;
};
};

28
Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
View File

@ -1,28 +0,0 @@
* Faraday Technology FTRTC010 Real Time Clock
This RTC appears in for example the Storlink Gemini family of
SoCs.
Required properties:
- compatible : Should be one of:
"faraday,ftrtc010"
"cortina,gemini-rtc", "faraday,ftrtc010"
Optional properties:
- clocks: when present should contain clock references to the
PCLK and EXTCLK clocks. Faraday calls the later CLK1HZ and
says the clock should be 1 Hz, but implementers actually seem
to choose different clocks here, like Cortina who chose
32768 Hz (a typical low-power clock).
- clock-names: should name the clocks "PCLK" and "EXTCLK"
respectively.
Examples:
rtc@45000000 {
compatible = "cortina,gemini-rtc";
reg = <0x45000000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&foo 0>, <&foo 1>;
clock-names = "PCLK", "EXTCLK";
};

59
Documentation/devicetree/bindings/rtc/faraday,ftrtc010.yaml Normal file
View File

@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/faraday,ftrtc010.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday Technology FTRTC010 Real Time Clock
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
This RTC appears in for example the Storlink Gemini family of SoCs.
properties:
compatible:
oneOf:
- const: faraday,ftrtc010
- items:
- const: cortina,gemini-rtc
- const: faraday,ftrtc010
resets:
maxItems: 1
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
items:
- description: PCLK clocks
- description: EXTCLK clocks. Faraday calls it CLK1HZ and says the clock
should be 1 Hz, but implementers actually seem to choose different
clocks here, like Cortina who chose 32768 Hz (a typical low-power clock).
clock-names:
items:
- const: "PCLK"
- const: "EXTCLK"
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
rtc@45000000 {
compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
reg = <0x45000000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&foo 0>, <&foo 1>;
clock-names = "PCLK", "EXTCLK";
};

9
Documentation/devicetree/bindings/rtc/rtc-m41t80.txt
View File

@ -21,10 +21,19 @@ Optional properties:
clock name
- wakeup-source: Enables wake up of host system on alarm
Optional child node:
- clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
Example:
rtc@68 {
compatible = "st,m41t80";
reg = <0x68>;
interrupt-parent = <&UIC0>;
interrupts = <0x9 0x8>;
clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};

49
Documentation/devicetree/bindings/rtc/ti,bq32000.yaml Normal file
View File

@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/ti,bq32000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI BQ32000 I2C Serial Real-Time Clock
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
allOf:
- $ref: rtc.yaml#
properties:
compatible:
const: ti,bq32000
reg:
const: 0x68
interrupts:
maxItems: 1
start-year: true
trickle-resistor-ohms:
enum: [ 1120, 20180 ]
trickle-diode-disable: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
bq32000: rtc@68 {
compatible = "ti,bq32000";
reg = <0x68>;
trickle-resistor-ohms = <1120>;
};
};

18
Documentation/devicetree/bindings/rtc/ti,bq32k.txt
View File

@ -1,18 +0,0 @@
* TI BQ32000 I2C Serial Real-Time Clock
Required properties:
- compatible: Should contain "ti,bq32000".
- reg: I2C address for chip
Optional properties:
- trickle-resistor-ohms : Selected resistor for trickle charger
Values usable are 1120 and 20180
Should be given if trickle charger should be enabled
- trickle-diode-disable : Do not use internal trickle charger diode
Should be given if internal trickle charger diode should be disabled
Example:
bq32000: rtc@68 {
compatible = "ti,bq32000";
trickle-resistor-ohms = <1120>;
reg = <0x68>;
};

1
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
View File

@ -27,6 +27,7 @@ Required properties in pwrap device node.
"mediatek,mt8135-pwrap" for MT8135 SoCs
"mediatek,mt8173-pwrap" for MT8173 SoCs
"mediatek,mt8183-pwrap" for MT8183 SoCs
"mediatek,mt8195-pwrap" for MT8195 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs
- interrupts: IRQ for pwrap in SOC
- reg-names: Must include the following entries:

2
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
View File

@ -32,12 +32,14 @@ properties:
enum:
- qcom,rpm-apq8084
- qcom,rpm-ipq6018
- qcom,rpm-msm8226
- qcom,rpm-msm8916
- qcom,rpm-msm8974
- qcom,rpm-msm8976
- qcom,rpm-msm8996
- qcom,rpm-msm8998
- qcom,rpm-sdm660
- qcom,rpm-sm6125
- qcom,rpm-qcs404
qcom,smd-channels:

61
Documentation/devicetree/bindings/soc/rockchip/grf.txt
View File

@ -1,61 +0,0 @@
* Rockchip General Register Files (GRF)
The general register file will be used to do static set by software, which
is composed of many registers for system control.
From RK3368 SoCs, the GRF is divided into two sections,
- GRF, used for general non-secure system,
- SGRF, used for general secure system,
- PMUGRF, used for always on system
On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
ON RK3308 SoC, the GRF is divided into four sections:
- GRF, used for general non-secure system,
- SGRF, used for general secure system,
- DETECTGRF, used for audio codec system,
- COREGRF, used for pvtm,
Required Properties:
- compatible: GRF should be one of the following:
- "rockchip,px30-grf", "syscon": for px30
- "rockchip,rk3036-grf", "syscon": for rk3036
- "rockchip,rk3066-grf", "syscon": for rk3066
- "rockchip,rk3188-grf", "syscon": for rk3188
- "rockchip,rk3228-grf", "syscon": for rk3228
- "rockchip,rk3288-grf", "syscon": for rk3288
- "rockchip,rk3308-grf", "syscon": for rk3308
- "rockchip,rk3328-grf", "syscon": for rk3328
- "rockchip,rk3368-grf", "syscon": for rk3368
- "rockchip,rk3399-grf", "syscon": for rk3399
- "rockchip,rv1108-grf", "syscon": for rv1108
- compatible: DETECTGRF should be one of the following:
- "rockchip,rk3308-detect-grf", "syscon": for rk3308
- compatilbe: COREGRF should be one of the following:
- "rockchip,rk3308-core-grf", "syscon": for rk3308
- compatible: PMUGRF should be one of the following:
- "rockchip,px30-pmugrf", "syscon": for px30
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
- compatible: SGRF should be one of the following:
- "rockchip,rk3288-sgrf", "syscon": for rk3288
- compatible: USB2PHYGRF should be one of the following:
- "rockchip,px30-usb2phy-grf", "syscon": for px30
- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
- compatible: USBGRF should be one of the following:
- "rockchip,rv1108-usbgrf", "syscon": for rv1108
- reg: physical base address of the controller and length of memory mapped
region.
Example: GRF and PMUGRF of RK3399 SoCs
pmugrf: syscon@ff320000 {
compatible = "rockchip,rk3399-pmugrf", "syscon";
reg = <0x0 0xff320000 0x0 0x1000>;
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon";
reg = <0x0 0xff770000 0x0 0x10000>;
};

261
Documentation/devicetree/bindings/soc/rockchip/grf.yaml Normal file
View File

@ -0,0 +1,261 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip General Register Files (GRF)
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
oneOf:
- items:
- enum:
- rockchip,rk3288-sgrf
- rockchip,rv1108-pmugrf
- rockchip,rv1108-usbgrf
- const: syscon
- items:
- enum:
- rockchip,px30-grf
- rockchip,px30-pmugrf
- rockchip,px30-usb2phy-grf
- rockchip,rk3036-grf
- rockchip,rk3066-grf
- rockchip,rk3188-grf
- rockchip,rk3228-grf
- rockchip,rk3288-grf
- rockchip,rk3308-core-grf
- rockchip,rk3308-detect-grf
- rockchip,rk3308-grf
- rockchip,rk3308-usb2phy-grf
- rockchip,rk3328-grf
- rockchip,rk3328-usb2phy-grf
- rockchip,rk3368-grf
- rockchip,rk3368-pmugrf
- rockchip,rk3399-grf
- rockchip,rk3399-pmugrf
- rockchip,rk3568-grf
- rockchip,rk3568-pmugrf
- rockchip,rv1108-grf
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
required:
- compatible
- reg
additionalProperties:
type: object
allOf:
- if:
properties:
compatible:
contains:
const: rockchip,px30-grf
then:
properties:
lvds:
description:
Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
- if:
properties:
compatible:
contains:
const: rockchip,rk3288-grf
then:
properties:
edp-phy:
description:
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3066-grf
- rockchip,rk3188-grf
- rockchip,rk3288-grf
then:
properties:
usbphy:
type: object
$ref: "/schemas/phy/rockchip-usb-phy.yaml#"
unevaluatedProperties: false
- if:
properties:
compatible:
contains:
const: rockchip,rk3328-grf
then:
properties:
gpio:
type: object
$ref: "/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#"
unevaluatedProperties: false
power-controller:
type: object
$ref: "/schemas/power/rockchip,power-controller.yaml#"
unevaluatedProperties: false
- if:
properties:
compatible:
contains:
const: rockchip,rk3399-grf
then:
properties:
mipi-dphy-rx0:
type: object
$ref: "/schemas/phy/rockchip-mipi-dphy-rx0.yaml#"
unevaluatedProperties: false
pcie-phy:
description:
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
patternProperties:
"phy@[0-9a-f]+$":
description:
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
- if:
properties:
compatible:
contains:
enum:
- rockchip,px30-pmugrf
- rockchip,rk3036-grf
- rockchip,rk3308-grf
- rockchip,rk3368-pmugrf
then:
properties:
reboot-mode:
type: object
$ref: "/schemas/power/reset/syscon-reboot-mode.yaml#"
unevaluatedProperties: false
- if:
properties:
compatible:
contains:
enum:
- rockchip,px30-usb2phy-grf
- rockchip,rk3228-grf
- rockchip,rk3308-usb2phy-grf
- rockchip,rk3328-usb2phy-grf
- rockchip,rk3399-grf
- rockchip,rv1108-grf
then:
required:
- "#address-cells"
- "#size-cells"
patternProperties:
"usb2phy@[0-9a-f]+$":
type: object
$ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#"
unevaluatedProperties: false
- if:
properties:
compatible:
contains:
enum:
- rockchip,px30-pmugrf
- rockchip,px30-grf
- rockchip,rk3228-grf
- rockchip,rk3288-grf
- rockchip,rk3328-grf
- rockchip,rk3368-pmugrf
- rockchip,rk3368-grf
- rockchip,rk3399-pmugrf
- rockchip,rk3399-grf
then:
properties:
io-domains:
description:
Documentation/devicetree/bindings/power/rockchip-io-domain.txt
examples:
- |
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/rk3399-power.h>
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
reg = <0xff770000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
mipi_dphy_rx0: mipi-dphy-rx0 {
compatible = "rockchip,rk3399-mipi-dphy-rx0";
clocks = <&cru SCLK_MIPIDPHY_REF>,
<&cru SCLK_DPHY_RX0_CFG>,
<&cru PCLK_VIO_GRF>;
clock-names = "dphy-ref", "dphy-cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
#phy-cells = <0>;
};
u2phy0: usb2phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
clocks = <&cru SCLK_USB2PHY0_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "clk_usbphy0_480m";
u2phy0_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "linestate";
};
u2phy0_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
};
};
};

136
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
View File

@ -1,136 +0,0 @@
* Rockchip Power Domains
Rockchip processors include support for multiple power domains which can be
powered up/down by software based on different application scenes to save power.
Required properties for power domain controller:
- compatible: Should be one of the following.
"rockchip,px30-power-controller" - for PX30 SoCs.
"rockchip,rk3036-power-controller" - for RK3036 SoCs.
"rockchip,rk3066-power-controller" - for RK3066 SoCs.
"rockchip,rk3128-power-controller" - for RK3128 SoCs.
"rockchip,rk3188-power-controller" - for RK3188 SoCs.
"rockchip,rk3228-power-controller" - for RK3228 SoCs.
"rockchip,rk3288-power-controller" - for RK3288 SoCs.
"rockchip,rk3328-power-controller" - for RK3328 SoCs.
"rockchip,rk3366-power-controller" - for RK3366 SoCs.
"rockchip,rk3368-power-controller" - for RK3368 SoCs.
"rockchip,rk3399-power-controller" - for RK3399 SoCs.
- #power-domain-cells: Number of cells in a power-domain specifier.
Should be 1 for multiple PM domains.
- #address-cells: Should be 1.
- #size-cells: Should be 0.
Required properties for power domain sub nodes:
- reg: index of the power domain, should use macros in:
"include/dt-bindings/power/px30-power.h" - for PX30 type power domain.
"include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain.
"include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain.
"include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain.
"include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain.
"include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain.
"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
"include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain.
"include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain.
"include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
"include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
- clocks (optional): phandles to clocks which need to be enabled while power domain
switches state.
- pm_qos (optional): phandles to qos blocks which need to be saved and restored
while power domain switches state.
Qos Example:
qos_gpu: qos_gpu@ffaf0000 {
compatible ="syscon";
reg = <0x0 0xffaf0000 0x0 0x20>;
};
Example:
power: power-controller {
compatible = "rockchip,rk3288-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
pd_gpu {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
};
};
power: power-controller {
compatible = "rockchip,rk3368-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
pd_gpu_1 {
reg = <RK3368_PD_GPU_1>;
clocks = <&cru ACLK_GPU_CFG>;
};
};
Example 2:
power: power-controller {
compatible = "rockchip,rk3399-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
pd_vio {
#address-cells = <1>;
#size-cells = <0>;
reg = <RK3399_PD_VIO>;
pd_vo {
#address-cells = <1>;
#size-cells = <0>;
reg = <RK3399_PD_VO>;
pd_vopb {
reg = <RK3399_PD_VOPB>;
};
pd_vopl {
reg = <RK3399_PD_VOPL>;
};
};
};
};
Node of a device using power domains must have a power-domains property,
containing a phandle to the power device node and an index specifying which
power domain to use.
The index should use macros in:
"include/dt-bindings/power/px30-power.h" - for px30 type power domain.
"include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain.
"include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain.
"include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain.
"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
"include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain.
"include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain.
"include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
"include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
Example of the node using power domain:
node {
/* ... */
power-domains = <&power RK3288_PD_GPU>;
/* ... */
};
node {
/* ... */
power-domains = <&power RK3368_PD_GPU_1>;
/* ... */
};
node {
/* ... */
power-domains = <&power RK3399_PD_VOPB>;
/* ... */
};

3
Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
View File

@ -20,6 +20,9 @@ properties:
- const: allwinner,sun6i-a31-i2s
- const: allwinner,sun8i-a83t-i2s
- const: allwinner,sun8i-h3-i2s
- items:
- const: allwinner,sun8i-v3-i2s
- const: allwinner,sun8i-h3-i2s
- const: allwinner,sun50i-a64-codec-i2s
- items:
- const: allwinner,sun50i-a64-i2s

9
Documentation/devicetree/bindings/sound/allwinner,sun8i-a23-codec-analog.yaml
View File

@ -12,12 +12,15 @@ maintainers:
properties:
compatible:
enum:
oneOf:
# FIXME: This is documented in the PRCM binding, but needs to be
# migrated here at some point
# - allwinner,sun8i-a23-codec-analog
- allwinner,sun8i-h3-codec-analog
- allwinner,sun8i-v3s-codec-analog
- const: allwinner,sun8i-h3-codec-analog
- items:
- const: allwinner,sun8i-v3-codec-analog
- const: allwinner,sun8i-h3-codec-analog
- const: allwinner,sun8i-v3s-codec-analog
reg:
maxItems: 1

73
Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml Normal file
View File

@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/nvidia,tegra30-tsensor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra30 Thermal Sensor
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
TSENSOR provides thermal and voltage sensors which monitor temperature
and voltage of the chip. Sensors are placed across the die to gauge the
temperature of the whole chip. The TSENSOR module:
Generates an interrupt to SW to lower temperature via DVFS on reaching
a certain thermal/voltage threshold.
Generates a signal to the CAR to reduce CPU frequency by half on reaching
a certain thermal/voltage threshold.
Generates a signal to the PMC when the temperature reaches dangerously high
levels to reset the chip and sets a flag in the PMC.
TSENSOR has two channels which monitor two different spots of the SoC.
properties:
compatible:
const: nvidia,tegra30-tsensor
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
"#thermal-sensor-cells":
const: 1
assigned-clock-parents: true
assigned-clock-rates: true
assigned-clocks: true
required:
- compatible
- reg
- clocks
- resets
- interrupts
- "#thermal-sensor-cells"
additionalProperties: false
examples:
- |
thermal-sensor@70014000 {
compatible = "nvidia,tegra30-tsensor";
reg = <0x70014000 0x500>;
interrupts = <0 102 4>;
clocks = <&clk 100>;
resets = <&rst 100>;
#thermal-sensor-cells = <1>;
};

2
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
View File

@ -46,6 +46,8 @@ properties:
- qcom,msm8996-tsens
- qcom,msm8998-tsens
- qcom,sc7180-tsens
- qcom,sc7280-tsens
- qcom,sc8180x-tsens
- qcom,sdm845-tsens
- qcom,sm8150-tsens
- qcom,sm8250-tsens

85
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
View File

@ -1,85 +0,0 @@
* Temperature Sensor ADC (TSADC) on rockchip SoCs
Required properties:
- compatible : should be "rockchip,<name>-tsadc"
"rockchip,px30-tsadc": found on PX30 SoCs
"rockchip,rv1108-tsadc": found on RV1108 SoCs
"rockchip,rk3228-tsadc": found on RK3228 SoCs
"rockchip,rk3288-tsadc": found on RK3288 SoCs
"rockchip,rk3328-tsadc": found on RK3328 SoCs
"rockchip,rk3368-tsadc": found on RK3368 SoCs
"rockchip,rk3399-tsadc": found on RK3399 SoCs
- reg : physical base address of the controller and length of memory mapped
region.
- interrupts : The interrupt number to the cpu. The interrupt specifier format
depends on the interrupt controller.
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for
the peripheral clock.
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the name "tsadc-apb".
- pinctrl-names : The pin control state names;
- pinctrl-0 : The "init" pinctrl state, it will be set before device probe.
- pinctrl-1 : The "default" pinctrl state, it will be set after reset the
TSADC controller.
- pinctrl-2 : The "sleep" pinctrl state, it will be in for suspend.
- #thermal-sensor-cells : Should be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
Optional properties:
- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW
1:HIGH.
- rockchip,grf : The phandle of the syscon node for the general register file.
Exiample:
tsadc: tsadc@ff280000 {
compatible = "rockchip,rk3288-tsadc";
reg = <0xff280000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
};
Example: referring to thermal sensors:
thermal-zones {
cpu_thermal: cpu_thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
/* sensor ID */
thermal-sensors = <&tsadc 1>;
trips {
cpu_alert0: cpu_alert {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <90000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};

96
Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml Normal file
View File

@ -0,0 +1,96 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/rockchip-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Temperature Sensor ADC (TSADC) on Rockchip SoCs
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,px30-tsadc # PX30 SoCs
- rockchip,rv1108-tsadc # RV1108 SoCs
- rockchip,rk3228-tsadc # RK3228 SoCs
- rockchip,rk3288-tsadc # RK3288 SoCs
- rockchip,rk3328-tsadc # RK3328 SoCs
- rockchip,rk3368-tsadc # RK3368 SoCs
- rockchip,rk3399-tsadc # RK3399 SoCs
- rockchip,rk3568-tsadc # RK3568 SoCs
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: tsadc
- const: apb_pclk
resets:
maxItems: 1
reset-names:
items:
- const: tsadc-apb
"#thermal-sensor-cells":
const: 1
rockchip,grf:
description: The phandle of the syscon node for the general register file.
$ref: /schemas/types.yaml#/definitions/phandle
rockchip,hw-tshut-temp:
description: The hardware-controlled shutdown temperature value.
$ref: /schemas/types.yaml#/definitions/uint32
rockchip,hw-tshut-mode:
description: The hardware-controlled shutdown mode 0:CRU 1:GPIO.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
rockchip,hw-tshut-polarity:
description: The hardware-controlled active polarity 0:LOW 1:HIGH.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- "#thermal-sensor-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/rk3288-cru.h>
tsadc: tsadc@ff280000 {
compatible = "rockchip,rk3288-tsadc";
reg = <0xff280000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
};

42
Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
View File

@ -12,11 +12,18 @@ maintainers:
properties:
compatible:
enum:
- allwinner,sun4i-a10-timer
- allwinner,sun8i-a23-timer
- allwinner,sun8i-v3s-timer
- allwinner,suniv-f1c100s-timer
oneOf:
- enum:
- allwinner,sun4i-a10-timer
- allwinner,sun8i-a23-timer
- allwinner,sun8i-v3s-timer
- allwinner,suniv-f1c100s-timer
- items:
- enum:
- allwinner,sun50i-a64-timer
- allwinner,sun50i-h6-timer
- allwinner,sun50i-h616-timer
- const: allwinner,sun8i-a23-timer
reg:
maxItems: 1
@ -34,8 +41,8 @@ allOf:
- if:
properties:
compatible:
items:
const: allwinner,sun4i-a10-timer
enum:
- allwinner,sun4i-a10-timer
then:
properties:
@ -46,8 +53,8 @@ allOf:
- if:
properties:
compatible:
items:
const: allwinner,sun8i-a23-timer
enum:
- allwinner,sun8i-a23-timer
then:
properties:
@ -58,20 +65,9 @@ allOf:
- if:
properties:
compatible:
items:
const: allwinner,sun8i-v3s-timer
then:
properties:
interrupts:
minItems: 3
maxItems: 3
- if:
properties:
compatible:
items:
const: allwinner,suniv-f1c100s-timer
enum:
- allwinner,sun8i-v3s-timer
- allwinner,suniv-f1c100s-timer
then:
properties:

8
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -249,6 +249,8 @@ patternProperties:
description: Colorful GRP, Shenzhen Xueyushi Technology Ltd.
"^compulab,.*":
description: CompuLab Ltd.
"^congatec,.*":
description: congatec GmbH
"^coreriver,.*":
description: CORERIVER Semiconductor Co.,Ltd.
"^corpro,.*":
@ -315,6 +317,8 @@ patternProperties:
description: DPTechnics
"^dragino,.*":
description: Dragino Technology Co., Limited
"^ds,.*":
description: DaSheng, Inc.
"^dserve,.*":
description: dServe Technology B.V.
"^dynaimage,.*":
@ -409,6 +413,8 @@ patternProperties:
description: Firefly
"^focaltech,.*":
description: FocalTech Systems Co.,Ltd
"^forlinx,.*":
description: Baoding Forlinx Embedded Technology Co., Ltd.
"^frida,.*":
description: Shenzhen Frida LCD Co., Ltd.
"^friendlyarm,.*":
@ -1252,6 +1258,8 @@ patternProperties:
description: Western Digital Corp.
"^we,.*":
description: Würth Elektronik GmbH.
"^welltech,.*":
description: Welltech Computer Co., Limited.
"^wetek,.*":
description: WeTek Electronics, limited.
"^wexler,.*":

74
Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml Normal file
View File

@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel SAMA5D4 Watchdog Timer (WDT) Controller
maintainers:
- Eugen Hristev <eugen.hristev@microchip.com>
allOf:
- $ref: "watchdog.yaml#"
properties:
compatible:
enum:
- atmel,sama5d4-wdt
- microchip,sam9x60-wdt
- microchip,sama7g5-wdt
reg:
maxItems: 1
atmel,watchdog-type:
$ref: /schemas/types.yaml#/definitions/string
description: should be hardware or software.
oneOf:
- description:
Enable watchdog fault reset. A watchdog fault triggers
watchdog reset.
const: hardware
- description:
Enable watchdog fault interrupt. A watchdog fault asserts
watchdog interrupt.
const: software
default: hardware
atmel,idle-halt:
$ref: /schemas/types.yaml#/definitions/flag
description: |
present if you want to stop the watchdog when the CPU is in idle state.
CAUTION: This property should be used with care, it actually makes the
watchdog not counting when the CPU is in idle state, therefore the
watchdog reset time depends on mean CPU usage and will not reset at all
if the CPU stop working while it is in idle state, which is probably
not what you want.
atmel,dbg-halt:
$ref: /schemas/types.yaml#/definitions/flag
description: |
present if you want to stop the watchdog when the CPU is in debug state.
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
watchdog@fc068640 {
compatible = "atmel,sama5d4-wdt";
reg = <0xfc068640 0x10>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
timeout-sec = <10>;
atmel,watchdog-type = "hardware";
atmel,dbg-halt;
atmel,idle-halt;
};
...

34
Documentation/devicetree/bindings/watchdog/atmel-sama5d4-wdt.txt
View File

@ -1,34 +0,0 @@
* Atmel SAMA5D4 Watchdog Timer (WDT) Controller
Required properties:
- compatible: "atmel,sama5d4-wdt" or "microchip,sam9x60-wdt"
- reg: base physical address and length of memory mapped region.
Optional properties:
- timeout-sec: watchdog timeout value (in seconds).
- interrupts: interrupt number to the CPU.
- atmel,watchdog-type: should be "hardware" or "software".
"hardware": enable watchdog fault reset. A watchdog fault triggers
watchdog reset.
"software": enable watchdog fault interrupt. A watchdog fault asserts
watchdog interrupt.
- atmel,idle-halt: present if you want to stop the watchdog when the CPU is
in idle state.
CAUTION: This property should be used with care, it actually makes the
watchdog not counting when the CPU is in idle state, therefore the
watchdog reset time depends on mean CPU usage and will not reset at all
if the CPU stop working while it is in idle state, which is probably
not what you want.
- atmel,dbg-halt: present if you want to stop the watchdog when the CPU is
in debug state.
Example:
watchdog@fc068640 {
compatible = "atmel,sama5d4-wdt";
reg = <0xfc068640 0x10>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
timeout-sec = <10>;
atmel,watchdog-type = "hardware";
atmel,dbg-halt;
atmel,idle-halt;
};

40
Documentation/devicetree/bindings/watchdog/mstar,msc313e-wdt.yaml Normal file
View File

@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/mstar,msc313e-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar Watchdog Device Tree Bindings
maintainers:
- Daniel Palmer <daniel@0x0f.com>
- Romain Perier <romain.perier@gmail.com>
allOf:
- $ref: watchdog.yaml#
properties:
compatible:
enum:
- mstar,msc313e-wdt
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- clocks
- reg
unevaluatedProperties: false
examples:
- |
watchdog@6000 {
compatible = "mstar,msc313e-wdt";
reg = <0x6000 0x1f>;
clocks = <&xtal_div2>;
};

6
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
View File

@ -1,5 +1,8 @@
Mediatek SoCs Watchdog timer
The watchdog supports a pre-timeout interrupt that fires timeout-sec/2
before the expiry.
Required properties:
- compatible should contain:
@ -13,10 +16,12 @@ Required properties:
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
- reg : Specifies base physical address and size of the registers.
Optional properties:
- interrupts: Watchdog pre-timeout (bark) interrupt.
- timeout-sec: contains the watchdog timeout in seconds.
- #reset-cells: Should be 1.
@ -26,6 +31,7 @@ watchdog: watchdog@10007000 {
compatible = "mediatek,mt8183-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
timeout-sec = <10>;
#reset-cells = <1>;
};

1
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
View File

@ -17,6 +17,7 @@ properties:
enum:
- qcom,apss-wdt-qcs404
- qcom,apss-wdt-sc7180
- qcom,apss-wdt-sc7280
- qcom,apss-wdt-sdm845
- qcom,apss-wdt-sdx55
- qcom,apss-wdt-sm8150

1
Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
View File

@ -27,6 +27,7 @@ properties:
- rockchip,rk3328-wdt
- rockchip,rk3368-wdt
- rockchip,rk3399-wdt
- rockchip,rk3568-wdt
- rockchip,rv1108-wdt
- const: snps,dw-wdt

3
Documentation/driver-api/driver-model/devres.rst
View File

@ -400,7 +400,8 @@ POWER
PWM
devm_pwm_get()
devm_pwm_put()
devm_of_pwm_get()
devm_fwnode_pwm_get()
REGULATOR
devm_regulator_bulk_get()

7
Documentation/driver-api/pwm.rst
View File

@ -40,7 +40,8 @@ after usage with pwm_free().
New users should use the pwm_get() function and pass to it the consumer
device or a consumer name. pwm_put() is used to free the PWM device. Managed
variants of these functions, devm_pwm_get() and devm_pwm_put(), also exist.
variants of the getter, devm_pwm_get(), devm_of_pwm_get(),
devm_fwnode_pwm_get(), also exist.
After being requested, a PWM has to be configured using::
@ -48,6 +49,10 @@ After being requested, a PWM has to be configured using::
This API controls both the PWM period/duty_cycle config and the
enable/disable state.
There is also a usage_power setting: If set, the PWM driver is only required to
maintain the power output but has more freedom regarding signal form.
If supported by the driver, the signal can be optimized, for example to improve
EMI by phase shifting the individual channels of a chip.
The pwm_config(), pwm_enable() and pwm_disable() functions are just wrappers
around pwm_apply_state() and should not be used if the user wants to change

50
Documentation/filesystems/f2fs.rst
View File

@ -281,6 +281,18 @@ compress_extension=%s Support adding specified extension, so that f2fs can enab
For other files, we can still enable compression via ioctl.
Note that, there is one reserved special extension '*', it
can be set to enable compression for all files.
nocompress_extension=%s Support adding specified extension, so that f2fs can disable
compression on those corresponding files, just contrary to compression extension.
If you know exactly which files cannot be compressed, you can use this.
The same extension name can't appear in both compress and nocompress
extension at the same time.
If the compress extension specifies all files, the types specified by the
nocompress extension will be treated as special cases and will not be compressed.
Don't allow use '*' to specifie all file in nocompress extension.
After add nocompress_extension, the priority should be:
dir_flag < comp_extention,nocompress_extension < comp_file_flag,no_comp_file_flag.
See more in compression sections.
compress_chksum Support verifying chksum of raw data in compressed cluster.
compress_mode=%s Control file compression mode. This supports "fs" and "user"
modes. In "fs" mode (default), f2fs does automatic compression
@ -289,6 +301,9 @@ compress_mode=%s Control file compression mode. This supports "fs" and "user"
choosing the target file and the timing. The user can do manual
compression/decompression on the compression enabled files using
ioctls.
compress_cache Support to use address space of a filesystem managed inode to
cache compressed block, in order to improve cache hit ratio of
random read.
inlinecrypt When possible, encrypt/decrypt the contents of encrypted
files using the blk-crypto framework rather than
filesystem-layer encryption. This allows the use of
@ -717,10 +732,10 @@ users.
===================== ======================== ===================
User F2FS Block
===================== ======================== ===================
META WRITE_LIFE_NOT_SET
HOT_NODE "
WARM_NODE "
COLD_NODE "
N/A META WRITE_LIFE_NOT_SET
N/A HOT_NODE "
N/A WARM_NODE "
N/A COLD_NODE "
ioctl(COLD) COLD_DATA WRITE_LIFE_EXTREME
extension list " "
@ -746,10 +761,10 @@ WRITE_LIFE_LONG " WRITE_LIFE_LONG
===================== ======================== ===================
User F2FS Block
===================== ======================== ===================
META WRITE_LIFE_MEDIUM;
HOT_NODE WRITE_LIFE_NOT_SET
WARM_NODE "
COLD_NODE WRITE_LIFE_NONE
N/A META WRITE_LIFE_MEDIUM;
N/A HOT_NODE WRITE_LIFE_NOT_SET
N/A WARM_NODE "
N/A COLD_NODE WRITE_LIFE_NONE
ioctl(COLD) COLD_DATA WRITE_LIFE_EXTREME
extension list " "
@ -814,13 +829,30 @@ Compression implementation
all logical blocks in cluster contain valid data and compress ratio of
cluster data is lower than specified threshold.
- To enable compression on regular inode, there are three ways:
- To enable compression on regular inode, there are four ways:
* chattr +c file
* chattr +c dir; touch dir/file
* mount w/ -o compress_extension=ext; touch file.ext
* mount w/ -o compress_extension=*; touch any_file
- To disable compression on regular inode, there are two ways:
* chattr -c file
* mount w/ -o nocompress_extension=ext; touch file.ext
- Priority in between FS_COMPR_FL, FS_NOCOMP_FS, extensions:
* compress_extension=so; nocompress_extension=zip; chattr +c dir; touch
dir/foo.so; touch dir/bar.zip; touch dir/baz.txt; then foo.so and baz.txt
should be compresse, bar.zip should be non-compressed. chattr +c dir/bar.zip
can enable compress on bar.zip.
* compress_extension=so; nocompress_extension=zip; chattr -c dir; touch
dir/foo.so; touch dir/bar.zip; touch dir/baz.txt; then foo.so should be
compresse, bar.zip and baz.txt should be non-compressed.
chattr+c dir/bar.zip; chattr+c dir/baz.txt; can enable compress on bar.zip
and baz.txt.
- At this point, compression feature doesn't expose compressed space to user
directly in order to guarantee potential data updates later to the space.
Instead, the main goal is to reduce data writes to flash disk as much as

32
Documentation/firmware-guide/acpi/enumeration.rst
View File

@ -258,6 +258,38 @@ input driver::
.id_table = mpu3050_ids,
};
Reference to PWM device
=======================
Sometimes a device can be a consumer of PWM channel. Obviously OS would like
to know which one. To provide this mapping the special property has been
introduced, i.e.::
Device (DEV)
{
Name (_DSD, Package ()
{
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", Package () { "pwm-leds" } },
Package () { "label", "alarm-led" },
Package () { "pwms",
Package () {
"\\_SB.PCI0.PWM", // <PWM device reference>
0, // <PWM index>
600000000, // <PWM period>
0, // <PWM flags>
}
}
}
})
...
In the above example the PWM-based LED driver references to the PWM channel 0
of \_SB.PCI0.PWM device with initial period setting equal to 600 ms (note that
value is given in nanoseconds).
GPIO support
============

5
Documentation/translations/zh_CN/cpu-freq/cpu-drivers.rst
View File

@ -64,8 +64,6 @@ CPUfreq核心层注册一个cpufreq_driver结构体。
.driver_data - cpufreq驱动程序的特定数据。
.resolve_freq - 返回最适合目标频率的频率。不过并不能改变频率。
.get_intermediate 和 target_intermediate - 用于在改变CPU频率时切换到稳定
的频率。
@ -76,9 +74,6 @@ CPUfreq核心层注册一个cpufreq_driver结构体。
.exit - 一个指向per-policy清理函数的指针，该函数在cpu热插拔过程的CPU_POST_DEAD
阶段被调用。
.stop_cpu - 一个指向per-policy停止函数的指针，该函数在cpu热插拔过程的CPU_DOWN_PREPARE
阶段被调用。
.suspend - 一个指向per-policy暂停函数的指针，该函数在关中断且在该策略的调节器停止
后被调用。

53
Documentation/x86/elf_auxvec.rst Normal file
View File

@ -0,0 +1,53 @@
.. SPDX-License-Identifier: GPL-2.0
==================================
x86-specific ELF Auxiliary Vectors
==================================
This document describes the semantics of the x86 auxiliary vectors.
Introduction
============
ELF Auxiliary vectors enable the kernel to efficiently provide
configuration-specific parameters to userspace. In this example, a program
allocates an alternate stack based on the kernel-provided size::
#include <sys/auxv.h>
#include <elf.h>
#include <signal.h>
#include <stdlib.h>
#include <assert.h>
#include <err.h>
#ifndef AT_MINSIGSTKSZ
#define AT_MINSIGSTKSZ 51
#endif
....
stack_t ss;
ss.ss_sp = malloc(ss.ss_size);
assert(ss.ss_sp);
ss.ss_size = getauxval(AT_MINSIGSTKSZ) + SIGSTKSZ;
ss.ss_flags = 0;
if (sigaltstack(&ss, NULL))
err(1, "sigaltstack");
The exposed auxiliary vectors
=============================
AT_SYSINFO is used for locating the vsyscall entry point. It is not
exported on 64-bit mode.
AT_SYSINFO_EHDR is the start address of the page containing the vDSO.
AT_MINSIGSTKSZ denotes the minimum stack size required by the kernel to
deliver a signal to user-space. AT_MINSIGSTKSZ comprehends the space
consumed by the kernel to accommodate the user context for the current
hardware configuration. It does not comprehend subsequent user-space stack
consumption, which must be added by the user. (e.g. Above, user-space adds
SIGSTKSZ to AT_MINSIGSTKSZ.)

1
Documentation/x86/index.rst
View File

@ -36,3 +36,4 @@ x86-specific Documentation
sva
sgx
features
elf_auxvec

56
MAINTAINERS
View File

@ -752,6 +752,12 @@ L: linux-crypto@vger.kernel.org
S: Maintained
F: drivers/crypto/allwinner/
ALLWINNER HARDWARE SPINLOCK SUPPORT
M: Wilken Gottwalt <wilken.gottwalt@posteo.net>
S: Maintained
F: Documentation/devicetree/bindings/hwlock/allwinner,sun6i-hwspinlock.yaml
F: drivers/hwspinlock/sun6i_hwspinlock.c
ALLWINNER THERMAL DRIVER
M: Vasily Khoruzhick <anarsoul@gmail.com>
M: Yangtao Li <tiny.windzz@gmail.com>
@ -1844,6 +1850,7 @@ F: Documentation/devicetree/bindings/arm/gemini.txt
F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
F: arch/arm/boot/dts/gemini*
F: arch/arm/mach-gemini/
F: drivers/crypto/gemini/
F: drivers/net/ethernet/cortina/
@ -2204,6 +2211,7 @@ M: Daniel Palmer <daniel@thingy.jp>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://linux-chenxing.org/
T: git git://github.com/linux-chenxing/linux.git
F: Documentation/devicetree/bindings/arm/mstar/*
F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml
F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml
@ -2211,6 +2219,7 @@ F: arch/arm/boot/dts/mstar-*
F: arch/arm/mach-mstar/
F: drivers/clk/mstar/
F: drivers/gpio/gpio-msc313.c
F: drivers/watchdog/msc313e_wdt.c
F: include/dt-bindings/clock/mstar-*
F: include/dt-bindings/gpio/msc313-gpio.h
@ -2472,9 +2481,12 @@ F: drivers/*/*/*s3c24*
F: drivers/*/*s3c24*
F: drivers/*/*s3c64xx*
F: drivers/*/*s5pv210*
F: drivers/clocksource/samsung_pwm_timer.c
F: drivers/memory/samsung/
F: drivers/pwm/pwm-samsung.c
F: drivers/soc/samsung/
F: drivers/tty/serial/samsung*
F: include/clocksource/samsung_pwm.h
F: include/linux/platform_data/*s3c*
F: include/linux/serial_s3c.h
F: include/linux/soc/samsung/
@ -3769,6 +3781,17 @@ S: Supported
F: Documentation/devicetree/bindings/gpio/brcm,kona-gpio.txt
F: drivers/gpio/gpio-bcm-kona.c
BROADCOM MPI3 STORAGE CONTROLLER DRIVER
M: Sathya Prakash Veerichetty <sathya.prakash@broadcom.com>
M: Kashyap Desai <kashyap.desai@broadcom.com>
M: Sumit Saxena <sumit.saxena@broadcom.com>
M: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
L: mpi3mr-linuxdrv.pdl@broadcom.com
L: linux-scsi@vger.kernel.org
S: Supported
W: https://www.broadcom.com/support/storage
F: drivers/scsi/mpi3mr/
BROADCOM NETXTREME-E ROCE DRIVER
M: Selvin Xavier <selvin.xavier@broadcom.com>
M: Naresh Kumar PBS <nareshkumar.pbs@broadcom.com>
@ -7003,7 +7026,7 @@ F: drivers/iommu/exynos-iommu.c
F2FS FILE SYSTEM
M: Jaegeuk Kim <jaegeuk@kernel.org>
M: Chao Yu <yuchao0@huawei.com>
M: Chao Yu <chao@kernel.org>
L: linux-f2fs-devel@lists.sourceforge.net
S: Maintained
W: https://f2fs.wiki.kernel.org/
@ -7170,6 +7193,13 @@ F: include/linux/firewire.h
F: include/uapi/linux/firewire*.h
F: tools/firewire/
FIRMWARE FRAMEWORK FOR ARMV8-A
M: Sudeep Holla <sudeep.holla@arm.com>
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: drivers/firmware/arm_ffa/
F: include/linux/arm_ffa.h
FIRMWARE LOADER (request_firmware)
M: Luis Chamberlain <mcgrof@kernel.org>
L: linux-kernel@vger.kernel.org
@ -9381,6 +9411,7 @@ F: include/linux/soc/ixp4xx/qmgr.h
INTEL IXP4XX RANDOM NUMBER GENERATOR SUPPORT
M: Deepak Saxena <dsaxena@plexity.net>
S: Maintained
F: Documentation/devicetree/bindings/display/intel,ixp46x-rng.yaml
F: drivers/char/hw_random/ixp4xx-rng.c
INTEL KEEM BAY DRM DRIVER
@ -11941,6 +11972,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git
F: Documentation/devicetree/bindings/memory-controllers/
F: drivers/memory/
F: include/dt-bindings/memory/
F: include/memory/
MEMORY FREQUENCY SCALING DRIVERS FOR NVIDIA TEGRA
M: Dmitry Osipenko <digetx@gmail.com>
@ -13516,12 +13548,6 @@ L: linux-omap@vger.kernel.org
S: Maintained
F: arch/arm/mach-omap2/omap_hwmod*data*
OMAP HWMOD DATA FOR OMAP4-BASED DEVICES
M: Benoît Cousson <bcousson@baylibre.com>
L: linux-omap@vger.kernel.org
S: Maintained
F: arch/arm/mach-omap2/omap_hwmod_44xx_data.c
OMAP HWMOD SUPPORT
M: Benoît Cousson <bcousson@baylibre.com>
M: Paul Walmsley <paul@pwsan.com>
@ -14112,8 +14138,7 @@ F: Documentation/devicetree/bindings/pci/aardvark-pci.txt
F: drivers/pci/controller/pci-aardvark.c
PCI DRIVER FOR ALTERA PCIE IP
M: Ley Foon Tan <ley.foon.tan@intel.com>
L: rfi@lists.rocketboards.org (moderated for non-subscribers)
M: Joyce Ooi <joyce.ooi@intel.com>
L: linux-pci@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/altera-pcie.txt
@ -14186,6 +14211,12 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
F: drivers/pci/controller/dwc/pcie-fu740.c
PCI DRIVER FOR INTEL IXP4XX
M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
F: Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
F: drivers/pci/controller/pci-ixp4xx.c
PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD)
M: Jonathan Derrick <jonathan.derrick@intel.com>
L: linux-pci@vger.kernel.org
@ -14311,8 +14342,7 @@ S: Supported
F: Documentation/PCI/pci-error-recovery.rst
PCI MSI DRIVER FOR ALTERA MSI IP
M: Ley Foon Tan <ley.foon.tan@intel.com>
L: rfi@lists.rocketboards.org (moderated for non-subscribers)
M: Joyce Ooi <joyce.ooi@intel.com>
L: linux-pci@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@ -14833,6 +14863,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git
F: Documentation/ABI/testing/sysfs-class-power
F: Documentation/devicetree/bindings/power/supply/
F: drivers/power/supply/
F: include/linux/power/
F: include/linux/power_supply.h
POWERNV OPERATOR PANEL LCD DISPLAY DRIVER
@ -16219,7 +16250,7 @@ W: http://www.ibm.com/developerworks/linux/linux390/
F: drivers/s390/scsi/zfcp_*
S3C ADC BATTERY DRIVER
M: Krzysztof Kozlowski <krzk@kernel.org>
M: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
L: linux-samsung-soc@vger.kernel.org
S: Odd Fixes
F: drivers/power/supply/s3c_adc_battery.c
@ -18133,6 +18164,7 @@ F: include/media/i2c/tw9910.h
TEE SUBSYSTEM
M: Jens Wiklander <jens.wiklander@linaro.org>
R: Sumit Garg <sumit.garg@linaro.org>
L: op-tee@lists.trustedfirmware.org
S: Maintained
F: Documentation/staging/tee.rst

135
Makefile
View File

@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 13
PATCHLEVEL = 14
SUBLEVEL = 0
EXTRAVERSION =
EXTRAVERSION = -rc1
NAME = Opossums on Parade
# *DOCUMENTATION*
@ -129,6 +129,11 @@ endif
$(if $(word 2, $(KBUILD_EXTMOD)), \
$(error building multiple external modules is not supported))
# Remove trailing slashes
ifneq ($(filter %/, $(KBUILD_EXTMOD)),)
KBUILD_EXTMOD := $(shell dirname $(KBUILD_EXTMOD).)
endif
export KBUILD_EXTMOD
# ANDROID: set up mixed-build support. mixed-build allows device kernel modules
@ -558,14 +563,21 @@ scripts_basic:
$(Q)rm -f .tmp_quiet_recordmcount
PHONY += outputmakefile
ifdef building_out_of_srctree
# Before starting out-of-tree build, make sure the source tree is clean.
# outputmakefile generates a Makefile in the output directory, if using a
# separate output directory. This allows convenient use of make in the
# output directory.
# At the same time when output Makefile generated, generate .gitignore to
# ignore whole output directory
quiet_cmd_makefile = GEN Makefile
cmd_makefile = { \
echo "\# Automatically generated by $(srctree)/Makefile: don't edit"; \
echo "include $(srctree)/Makefile"; \
} > Makefile
outputmakefile:
ifdef building_out_of_srctree
$(Q)if [ -f $(srctree)/.config -o \
-d $(srctree)/include/config -o \
-d $(srctree)/arch/$(SRCARCH)/include/generated ]; then \
@ -576,7 +588,7 @@ ifdef building_out_of_srctree
false; \
fi
$(Q)ln -fsn $(srctree) source
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile $(srctree)
$(call cmd,makefile)
$(Q)test -e .gitignore || \
{ echo "# this is build directory, ignore it"; echo "*"; } > .gitignore
endif
@ -672,7 +684,7 @@ endif
ifeq ($(KBUILD_EXTMOD),)
# Objects we will link into vmlinux / subdirs we need to visit
core-y := init/ usr/
core-y := init/ usr/ arch/$(SRCARCH)/
drivers-y := drivers/ sound/
drivers-$(CONFIG_SAMPLES) += samples/
drivers-$(CONFIG_NET) += net/
@ -977,8 +989,8 @@ KBUILD_CFLAGS += $(CC_FLAGS_CFI)
export CC_FLAGS_CFI
endif
ifdef CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B
KBUILD_CFLAGS += -falign-functions=32
ifdef CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B
KBUILD_CFLAGS += -falign-functions=64
endif
# arch Makefile may override CC so keep this after arch Makefile is included
@ -1105,42 +1117,6 @@ export INSTALL_DTBS_PATH ?= $(INSTALL_PATH)/dtbs/$(KERNELRELEASE)
MODLIB = $(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE)
export MODLIB
HOST_LIBELF_LIBS = $(shell pkg-config libelf --libs 2>/dev/null || echo -lelf)
has_libelf := $(call try-run,\
echo "int main() {}" | \
$(HOSTCC) $(KBUILD_HOSTCFLAGS) -xc -o /dev/null $(KBUILD_HOSTLDFLAGS) $(HOST_LIBELF_LIBS) -,1,0)
ifdef CONFIG_STACK_VALIDATION
ifeq ($(has_libelf),1)
objtool_target := tools/objtool FORCE
else
SKIP_STACK_VALIDATION := 1
export SKIP_STACK_VALIDATION
endif
endif
PHONY += resolve_btfids_clean
resolve_btfids_O = $(abspath $(objtree))/tools/bpf/resolve_btfids
# tools/bpf/resolve_btfids directory might not exist
# in output directory, skip its clean in that case
resolve_btfids_clean:
ifneq ($(wildcard $(resolve_btfids_O)),)
$(Q)$(MAKE) -sC $(srctree)/tools/bpf/resolve_btfids O=$(resolve_btfids_O) clean
endif
ifdef CONFIG_BPF
ifdef CONFIG_DEBUG_INFO_BTF
ifeq ($(has_libelf),1)
resolve_btfids_target := tools/bpf/resolve_btfids FORCE
else
ERROR_RESOLVE_BTFIDS := 1
endif
endif # CONFIG_DEBUG_INFO_BTF
endif # CONFIG_BPF
PHONY += prepare0
export extmod_prefix = $(if $(KBUILD_EXTMOD),$(KBUILD_EXTMOD)/)
@ -1290,7 +1266,7 @@ prepare0: archprepare
$(Q)$(MAKE) $(build)=.
# All the preparing..
prepare: prepare0 prepare-objtool prepare-resolve_btfids
prepare: prepare0
PHONY += remove-stale-files
remove-stale-files:
@ -1307,26 +1283,6 @@ uapi-asm-generic:
$(Q)$(MAKE) $(asm-generic)=arch/$(SRCARCH)/include/generated/uapi/asm \
generic=include/uapi/asm-generic
PHONY += prepare-objtool prepare-resolve_btfids
prepare-objtool: $(objtool_target)
ifeq ($(SKIP_STACK_VALIDATION),1)
ifdef CONFIG_FTRACE_MCOUNT_USE_OBJTOOL
@echo "error: Cannot generate __mcount_loc for CONFIG_DYNAMIC_FTRACE=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel" >&2
@false
endif
ifdef CONFIG_UNWINDER_ORC
@echo "error: Cannot generate ORC metadata for CONFIG_UNWINDER_ORC=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel" >&2
@false
else
@echo "warning: Cannot use CONFIG_STACK_VALIDATION=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel" >&2
endif
endif
prepare-resolve_btfids: $(resolve_btfids_target)
ifeq ($(ERROR_RESOLVE_BTFIDS),1)
@echo "error: Cannot resolve BTF IDs for CONFIG_DEBUG_INFO_BTF, please install libelf-dev, libelf-devel or elfutils-libelf-devel" >&2
@false
endif
# Generate some files
# ---------------------------------------------------------------------------
@ -1392,6 +1348,43 @@ PHONY += scripts_unifdef
scripts_unifdef: scripts_basic
$(Q)$(MAKE) $(build)=scripts scripts/unifdef
# ---------------------------------------------------------------------------
# Tools
ifdef CONFIG_STACK_VALIDATION
prepare: tools/objtool
endif
ifdef CONFIG_BPF
ifdef CONFIG_DEBUG_INFO_BTF
prepare: tools/bpf/resolve_btfids
endif
endif
PHONY += resolve_btfids_clean
resolve_btfids_O = $(abspath $(objtree))/tools/bpf/resolve_btfids
# tools/bpf/resolve_btfids directory might not exist
# in output directory, skip its clean in that case
resolve_btfids_clean:
ifneq ($(wildcard $(resolve_btfids_O)),)
$(Q)$(MAKE) -sC $(srctree)/tools/bpf/resolve_btfids O=$(resolve_btfids_O) clean
endif
# Clear a bunch of variables before executing the submake
ifeq ($(quiet),silent_)
tools_silent=s
endif
tools/: FORCE
$(Q)mkdir -p $(objtree)/tools
$(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(tools_silent) $(filter --j% -j,$(MAKEFLAGS))" O=$(abspath $(objtree)) subdir=tools -C $(srctree)/tools/
tools/%: FORCE
$(Q)mkdir -p $(objtree)/tools
$(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(tools_silent) $(filter --j% -j,$(MAKEFLAGS))" O=$(abspath $(objtree)) subdir=tools -C $(srctree)/tools/ $*
# ---------------------------------------------------------------------------
# Kernel selftest
@ -1997,20 +1990,6 @@ kernelversion:
image_name:
@echo $(KBUILD_IMAGE)
# Clear a bunch of variables before executing the submake
ifeq ($(quiet),silent_)
tools_silent=s
endif
tools/: FORCE
$(Q)mkdir -p $(objtree)/tools
$(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(tools_silent) $(filter --j% -j,$(MAKEFLAGS))" O=$(abspath $(objtree)) subdir=tools -C $(srctree)/tools/
tools/%: FORCE
$(Q)mkdir -p $(objtree)/tools
$(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(tools_silent) $(filter --j% -j,$(MAKEFLAGS))" O=$(abspath $(objtree)) subdir=tools -C $(srctree)/tools/ $*
quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files)))
cmd_rmfiles = rm -rf $(rm-files)

3
arch/alpha/Kbuild Normal file
View File

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += kernel/ mm/
obj-$(CONFIG_MATHEMU) += math-emu/

2
arch/alpha/Makefile
View File

@ -38,8 +38,6 @@ KBUILD_CFLAGS += $(cflags-y) -Wa,-mev6
head-y := arch/alpha/kernel/head.o
core-y += arch/alpha/kernel/ arch/alpha/mm/
core-$(CONFIG_MATHEMU) += arch/alpha/math-emu/
libs-y += arch/alpha/lib/
# export what is needed by arch/alpha/boot/Makefile

8
arch/alpha/include/asm/pgtable.h
View File

@ -236,8 +236,10 @@ pmd_page_vaddr(pmd_t pmd)
#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> 32))
#define pud_page(pud) (pfn_to_page(pud_val(pud) >> 32))
extern inline unsigned long pud_page_vaddr(pud_t pgd)
{ return PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)); }
extern inline pmd_t *pud_pgtable(pud_t pgd)
{
return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)));
}
extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; }
@ -287,7 +289,7 @@ extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; retu
/* Find an entry in the second-level page table.. */
extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address)
{
pmd_t *ret = (pmd_t *) pud_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
smp_rmb(); /* see above */
return ret;
}

3
arch/arc/Makefile
View File

@ -85,9 +85,6 @@ KBUILD_LDFLAGS += $(ldflags-y)
head-y := arch/arc/kernel/head.o
# See arch/arc/Kbuild for content of core part of the kernel
core-y += arch/arc/
# w/o this dtb won't embed into kernel binary
core-y += arch/arc/boot/dts/

5
arch/arc/mm/init.c
View File

@ -89,10 +89,7 @@ void __init setup_arch_memory(void)
{
unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
init_mm.start_code = (unsigned long)_text;
init_mm.end_code = (unsigned long)_etext;
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)_end;
setup_initial_init_mm(_text, _etext, _edata, _end);
/* first page of system - kernel .vector starts here */
min_low_pfn = virt_to_pfn(CONFIG_LINUX_RAM_BASE);

3
arch/arm/Kconfig
View File

@ -393,7 +393,8 @@ config ARCH_IXP4XX
select HAVE_PCI
select IXP4XX_IRQ
select IXP4XX_TIMER
select NEED_MACH_IO_H
# With the new PCI driver this is not needed
select NEED_MACH_IO_H if PCI_IXP4XX_LEGACY
select USB_EHCI_BIG_ENDIAN_DESC
select USB_EHCI_BIG_ENDIAN_MMIO
help

17
arch/arm/Kconfig.debug
View File

@ -66,6 +66,8 @@ config UNWINDER_FRAME_POINTER
config UNWINDER_ARM
bool "ARM EABI stack unwinder"
depends on AEABI && !FUNCTION_GRAPH_TRACER
# https://github.com/ClangBuiltLinux/linux/issues/732
depends on !LD_IS_LLD || LLD_VERSION >= 110000
select ARM_UNWIND
help
This option enables stack unwinding support in the kernel
@ -607,6 +609,14 @@ choice
when u-boot hands over to the kernel, the system
silently crashes, with no serial output at all.
config DEBUG_MSTARV7_PMUART
bool "Kernel low-level debugging messages via MSTARV7 PM UART"
depends on ARCH_MSTARV7
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
for MSTAR ARMv7-based platforms on PM UART.
config DEBUG_MT6589_UART0
bool "Mediatek mt6589 UART0"
depends on ARCH_MEDIATEK
@ -1605,6 +1615,7 @@ config DEBUG_UART_PHYS
default 0x18000400 if DEBUG_BCM_HR2
default 0x18023000 if DEBUG_BCM_IPROC_UART3
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
default 0x1f221000 if DEBUG_MSTARV7_PMUART
default 0x20001000 if DEBUG_HIP01_UART
default 0x20060000 if DEBUG_RK29_UART0
default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
@ -1722,6 +1733,7 @@ config DEBUG_UART_VIRT
default 0xf0100000 if DEBUG_DIGICOLOR_UA0
default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836
default 0xf0221000 if DEBUG_MSTARV7_PMUART
default 0xf1000300 if DEBUG_BCM_5301X
default 0xf1000400 if DEBUG_BCM_HR2
default 0xf1002000 if DEBUG_MT8127_UART0
@ -1803,8 +1815,8 @@ config DEBUG_UART_VIRT
default 0xfedc0000 if DEBUG_EP93XX
default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xfef36000 if DEBUG_HIGHBANK_UART
default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
@ -1827,6 +1839,7 @@ config DEBUG_UART_8250_SHIFT
default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \
DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \
DEBUG_OMAP7XXUART3
default 3 if DEBUG_MSTARV7_PMUART
default 2
config DEBUG_UART_8250_WORD

Some files were not shown because too many files have changed in this diff Show More