V_01-00-30
1. Added module parameters for Rx Queue Size, Flow Control thresholds and Tx Queue Size configuration. 2. Renamed all module parameters for easy readability.
This commit is contained in:
TC956X
jianzhou
parent
63bead311e
commit
a5e807500a
75
Readme.md
75
Readme.md
@ -1,7 +1,7 @@
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# Toshiba Electronic Devices & Storage Corporation TC956X PCIe Ethernet Host Driver
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Release Date: 03 Dec 2021
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Release Date: 08 Dec 2021
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Release Version: V_01-00-29 : Limited-tested version
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Release Version: V_01-00-30 : Limited-tested version
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TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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@ -30,11 +30,14 @@ TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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#modprobe phylink
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4. Load the driver
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#insmod tc956x_pcie_eth.ko tc956x_speed=X
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#insmod tc956x_pcie_eth.ko pcie_link_speed=X
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In the module parameter tc956x_speed, X is the desired PCIe Gen speed. X can be 3 or 2 or 1.
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Passing module parameter (tc956x_speed=X) is optional.
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In the module parameter pcie_link_speed, X is the desired PCIe Gen speed. X can be 3 or 2 or 1.
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Passing module parameter (pcie_link_speed=X) is optional.
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If module parameter is not passed, by default Gen3 speed will be selected by the driver.
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Please note that driver should be compiled using below command to use this feature:
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#make TC956X_PCIE_GEN3_SETTING=1
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5. Remove the driver
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#rmmod tc956x_pcie_eth
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@ -57,11 +60,11 @@ TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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2. Use the below command to insert the kernel module with specific modes for interfaces:
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#insmod tc956x_pcie_eth.ko tc956x_port0_interface=x tc956x_port1_interface=y
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#insmod tc956x_pcie_eth.ko mac0_interface=x mac1_interface=y
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argument info:
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tc956x_port0_interface: For PORT0 interface mode setting
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tc956x_port1_interface: For PORT1 interface mode setting
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mac0_interface: For PORT0 interface mode setting
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mac1_interface: For PORT1 interface mode setting
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x = [0: USXGMII, 1: XFI (default), 2: RGMII (unsupported), 3: SGMII]
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y = [0: USXGMII (unsupported), 1: XFI (unsupported), 2: RGMII, 3: SGMII(default)]
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@ -153,11 +156,11 @@ TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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10. Please use the below command to insert the kernel module for passing pause frames to application except pause frames from PHY:
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#insmod tc956x_pcie_eth.ko tc956x_port0_filter_phy_pause_frames=x tc956x_port1_filter_phy_pause_frames=x
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#insmod tc956x_pcie_eth.ko mac0_filter_phy_pause=x mac1_filter_phy_pause=x
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argument info:
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tc956x_port0_filter_phy_pause_frames: For PORT0
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tc956x_port1_filter_phy_pause_frames: For PORT1
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mac0_filter_phy_pause: For PORT0
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mac1_filter_phy_pause: For PORT1
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x = [0: DISABLE (default), 1: ENABLE]
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If invalid values are passed as kernel module parameter, the default value will be selected.
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@ -181,18 +184,18 @@ TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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13. Please use the below command to insert the kernel module to enable EEE and configure LPI Auto Entry timer:
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#insmod tc956x_pcie_eth.ko tc956x_port0_enable_eee=X tc956x_port0_lpi_auto_entry_timer=Y tc956x_port1_enable_eee=X tc956x_port1_lpi_auto_entry_timer=Y
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#insmod tc956x_pcie_eth.ko mac0_eee_enable=X mac0_lpi_timer=Y mac1_eee_enable=X mac1_lpi_timer=Y
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argument info:
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tc956x_port0_enable_eee: For PORT0
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tc956x_port1_enable_eee: For PORT1
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mac0_eee_enable: For PORT0
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mac1_eee_enable: For PORT1
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X = [0: DISABLE (default), 1: ENABLE]
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This module parameter is to Enable/Disable EEE for Port 0/1 - default is 0.
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If invalid values are passed as kernel module parameter, the default value will be selected.
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tc956x_port0_lpi_auto_entry_timer: For PORT0
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tc956x_port1_lpi_auto_entry_timer: For PORT1
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mac0_lpi_timer: For PORT0
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mac1_lpi_timer: For PORT1
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Y = [0..1048568 (us)]
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This module parameter is to configure LPI Automatic Entry Timer for Port 0/1 - default is 600 (us).
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If invalid values are passed as kernel module parameter, the default value will be selected.
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@ -204,6 +207,41 @@ TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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Use below command to check the status of EEE configuration
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#ethtool --show-eee <interface>
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14. Please use the below command to insert the kernel module for RX Queue size, Flow control thresholds & TX Queue size configuration.
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#insmod tc956x_pcie_eth.ko mac0_rxq0_size=x mac0_rxq0_rfd=y mac0_rxq0_rfa=y
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mac0_rxq1_size=x mac0_rxq1_rfd=y mac0_rxq1_rfa=y
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mac0_txq0_size=x mac0_txq1_size=x
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mac1_rxq0_size=x mac1_rxq0_rfd=y mac1_rxq0_rfa=y
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mac1_rxq1_size=x mac1_rxq1_rfd=y mac1_rxq1_rfa=y
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mac1_txq0_size=x mac1_txq1_size=x
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argument info:
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mac0_rxq0_size: For PORT0 RX Queue-0
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mac0_rxq1_size: For PORT0 RX Queue-1
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mac1_rxq0_size: For PORT1 RX Queue-0
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mac1_rxq1_size: For PORT1 RX Queue-1
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mac0_txq0_size: For PORT0 TX Queue-0
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mac0_txq1_size: For PORT0 TX Queue-1
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mac1_txq0_size: For PORT1 TX Queue-0
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mac1_txq1_size: For PORT1 TX Queue-1
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x = [Range Supported : 3072..44032 (bytes)], default is 18432 (bytes)
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mac0_rxq0_rfd: For PORT0 Queue-0 threshold for Disable flow control
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mac0_rxq1_rfd: For PORT0 Queue-1 threshold for Disable flow control
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mac0_rxq0_rfa: For PORT0 Queue-0 threshold for Enable flow control
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mac0_rxq1_rfa: For PORT0 Queue-1 threshold for Enable flow control
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mac1_rxq0_rfd: For PORT1 Queue-0 threshold for Disable flow control
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mac1_rxq1_rfd: For PORT1 Queue-1 threshold for Disable flow control
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mac1_rxq0_rfa: For PORT1 Queue-0 threshold for Enable flow control
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mac1_rxq1_rfa: For PORT1 Queue-1 threshold for Enable flow control
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y = [Range Supported : 0..84], default is 24 (13KB)
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If invalid values are passed as kernel module parameter, the default value will be selected for Queue Sizes and for Flow control 80% of Queue size will be used.
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Note:
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1. Please configure flow control thresholds (RFD & RFA) as per Queue size (Default values are for Default Queue size which is 18KB).
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# Release Versions:
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## TC956X_Host_Driver_20210326_V_01-00:
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@ -353,3 +391,8 @@ TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
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1. Max C22/C45 PHY address changed to PHY_MAX_ADDR.
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2. Added error check for phydev in tc956xmac_suspend().
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## TC956X_Host_Driver_20211208_V_01-00-30:
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1. Added module parameters for Rx Queue Size, Flow Control thresholds and Tx Queue Size configuration.
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2. Renamed all module parameters for easy readability.
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9
common.h
9
common.h
@ -64,7 +64,9 @@
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* 24 Nov 2021 : 1. Single Port Suspend/Resume supported
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* VERSION : 01-00-22
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* 24 Nov 2021 : 1. EEE update for runtime configuration and LPI interrupt disabled.
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* VERSION : 01-00-24
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* VERSION : 01-00-24
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* 08 Dec 2021 : 1. Added Macro for Maximum Tx, Rx Queue Size and byte size.
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* VERSION : 01-00-30
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*/
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#ifndef __COMMON_H__
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@ -106,6 +108,8 @@ enum TC956X_PORT_PM_STATE {
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#define DISABLE 0
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#define ENABLE 1
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#define SIZE_512B 512
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#define SIZE_1KB 1024
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/* Synopsys Core versions */
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#define DWMAC_CORE_3_40 0x34
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@ -384,6 +388,9 @@ enum packets_types {
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#define RX_QUEUE6_SIZE 0
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#define RX_QUEUE7_SIZE 0
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#define MAX_RX_QUEUE_SIZE 47104 /* 46KB Maximun RX Queue size */
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#define MAX_TX_QUEUE_SIZE 47104 /* 46KB Maximun TX Queue size */
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/*
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* RX Queue 0: Unicast/Untagged Packets - Packets with
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* unique MAC Address of Host/Guest OS DMA channel selection will be based on
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@ -57,6 +57,8 @@
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* 24 Nov 2021 : 1. EEE update for runtime configuration and LPI interrupt disabled.
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2. USXGMII support during link change
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* VERSION : 01-00-24
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* 08 Dec 2021 : 1. Renamed pause frames module parameter
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* VERSION : 01-00-30
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*/
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#include <linux/bitrev.h>
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@ -66,8 +68,8 @@
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#include "tc956xmac_ptp.h"
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#include "dwxgmac2.h"
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extern unsigned int tc956x_port0_filter_phy_pause_frames;
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extern unsigned int tc956x_port1_filter_phy_pause_frames;
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extern unsigned int mac0_filter_phy_pause;
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extern unsigned int mac1_filter_phy_pause;
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static void tc956x_set_mac_addr(struct tc956xmac_priv *priv, struct mac_device_info *hw,
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const u8 *mac, int index, int vf);
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@ -1028,8 +1030,8 @@ static void dwxgmac2_set_filter(struct tc956xmac_priv *priv, struct mac_device_i
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XGMAC_FILTER_RA);
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value |= XGMAC_FILTER_HPF;
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/* Configuring to Pass all pause frames to application, PHY pause frames will be filtered by FRP */
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if ((tc956x_port0_filter_phy_pause_frames == ENABLE && priv->port_num == RM_PF0_ID) ||
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(tc956x_port1_filter_phy_pause_frames == ENABLE && priv->port_num == RM_PF1_ID)) {
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if ((mac0_filter_phy_pause == ENABLE && priv->port_num == RM_PF0_ID) ||
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(mac1_filter_phy_pause == ENABLE && priv->port_num == RM_PF1_ID)) {
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/* setting pcf to 0b10 i.e. pass pause frames of address filter fail to Application */
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value |= 0x80;
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}
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@ -38,6 +38,8 @@
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* Threshold Limit for Activating Flow control
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* Threshold Limit for Deactivating Flow control
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* VERSION : 01-00-14
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* 08 Dec 2021 : 1. Added module parameter for Flow control thresholds per Queue
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* VERSION : 01-00-30
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*/
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#include <linux/iopoll.h>
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@ -254,28 +256,8 @@ static void dwxgmac2_dma_rx_mode(struct tc956xmac_priv *priv,
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value |= XGMAC_EHFC;
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/* Set Threshold for Activating Flow Control to min 2 frames,
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* i.e. 1500 * 2 = 3000 bytes.
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*
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* Set Threshold for Deactivating Flow Control to min 1 frame,
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* i.e. 1500 bytes.
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*/
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switch (fifosz) {
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case 4096:
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/* This violates the above formula because of FIFO size
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* limit therefore overflow may occur in spite of this.
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*/
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rfd = 0x03; /* Full-2.5K */
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rfa = 0x01; /* Full-1.5K */
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break;
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default:
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/* 13K Clear Trigger when Q(x) is filled with Max Size - 13K */
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rfd = 24;
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/* 13K Trigger when Q(x) is filled with Max Size - 13K */
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rfa = 24;
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break;
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}
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rfd = priv->plat->rx_queues_cfg[channel].rfd;
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rfa = priv->plat->rx_queues_cfg[channel].rfa;
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flow &= ~XGMAC_RFD;
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flow |= rfd << XGMAC_RFD_SHIFT;
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356
tc956x_pci.c
356
tc956x_pci.c
@ -105,6 +105,11 @@
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* VERSION : 01-00-28
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* 03 Dec 2021 : 1. Version update
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* VERSION : 01-00-29
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* 08 Dec 2021 : 1. Added Module parameter for Rx Queue Size, Flow control threaholds and Tx Queue Size configuration
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2. Renamed All Module parameters for easy readability.
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3. Printing User Configured/Default Module Parameters for future purpose.
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4. Version update.
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* VERSION : 01-00-30
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*/
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#include <linux/clk-provider.h>
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@ -129,20 +134,38 @@
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#endif /* #ifdef TC956X_PCIE_LOGSTAT */
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#ifdef TC956X_PCIE_GEN3_SETTING
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static unsigned int tc956x_speed = 3;
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static unsigned int pcie_link_speed = 3;
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#endif
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static unsigned int tc956x_port0_interface = ENABLE_XFI_INTERFACE;
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static unsigned int tc956x_port1_interface = ENABLE_SGMII_INTERFACE;
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static unsigned int mac0_interface = ENABLE_XFI_INTERFACE;
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static unsigned int mac1_interface = ENABLE_SGMII_INTERFACE;
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unsigned int tc956x_port0_filter_phy_pause_frames = DISABLE;
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unsigned int tc956x_port1_filter_phy_pause_frames = DISABLE;
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unsigned int mac0_filter_phy_pause = DISABLE;
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unsigned int mac1_filter_phy_pause = DISABLE;
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static unsigned int tc956x_port0_enable_eee = DISABLE;
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static unsigned int tc956x_port0_lpi_auto_entry_timer = TC956XMAC_LPIET_600US;
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static unsigned int tc956x_port1_enable_eee = DISABLE;
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static unsigned int tc956x_port1_lpi_auto_entry_timer = TC956XMAC_LPIET_600US;
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static unsigned int mac0_eee_enable = DISABLE;
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static unsigned int mac0_lpi_timer = TC956XMAC_LPIET_600US;
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static unsigned int mac1_eee_enable = DISABLE;
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static unsigned int mac1_lpi_timer = TC956XMAC_LPIET_600US;
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static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 2, 9};
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static unsigned int mac0_rxq0_size = RX_QUEUE0_SIZE;
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static unsigned int mac0_rxq1_size = RX_QUEUE1_SIZE;
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static unsigned int mac0_rxq0_rfd = 24;
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static unsigned int mac0_rxq0_rfa = 24;
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static unsigned int mac0_rxq1_rfd = 24;
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static unsigned int mac0_rxq1_rfa = 24;
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static unsigned int mac0_txq0_size = TX_QUEUE0_SIZE;
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static unsigned int mac0_txq1_size = TX_QUEUE1_SIZE;
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static unsigned int mac1_rxq0_size = RX_QUEUE0_SIZE;
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static unsigned int mac1_rxq1_size = RX_QUEUE1_SIZE;
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static unsigned int mac1_rxq0_rfd = 24;
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static unsigned int mac1_rxq0_rfa = 24;
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static unsigned int mac1_rxq1_rfd = 24;
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static unsigned int mac1_rxq1_rfa = 24;
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static unsigned int mac1_txq0_size = TX_QUEUE0_SIZE;
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static unsigned int mac1_txq1_size = TX_QUEUE1_SIZE;
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static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 3, 0};
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static int tc956xmac_pm_usage_counter; /* Device Usage Counter */
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struct mutex tc956x_pm_suspend_lock; /* This mutex is shared between all available EMAC ports. */
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@ -805,8 +828,8 @@ static void xgmac_default_data(struct plat_tc956xmacenet_data *plat)
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sizeof(struct tc956xmac_rx_parser_entry));
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/* Over writing the Default FRP table with FRP Table for Filtering PHY pause frames */
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if ((tc956x_port0_filter_phy_pause_frames == ENABLE && plat->port_num == RM_PF0_ID) ||
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(tc956x_port1_filter_phy_pause_frames == ENABLE && plat->port_num == RM_PF1_ID)) {
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if ((mac0_filter_phy_pause == ENABLE && plat->port_num == RM_PF0_ID) ||
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(mac1_filter_phy_pause == ENABLE && plat->port_num == RM_PF1_ID)) {
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plat->rxp_cfg.nve = ARRAY_SIZE(snps_rxp_entries_filter_phy_pause_frames);
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plat->rxp_cfg.npe = ARRAY_SIZE(snps_rxp_entries_filter_phy_pause_frames);
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memcpy(plat->rxp_cfg.entries, snps_rxp_entries_filter_phy_pause_frames,
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@ -819,6 +842,8 @@ static void xgmac_default_data(struct plat_tc956xmacenet_data *plat)
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static int tc956xmac_xgmac3_default_data(struct pci_dev *pdev,
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struct plat_tc956xmacenet_data *plat)
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{
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unsigned int queue0_rfd = 0, queue1_rfd = 0, queue0_rfa = 0, queue1_rfa = 0, temp_var = 0;
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unsigned int rxqueue0_size = 0, rxqueue1_size = 0, txqueue0_size = 0, txqueue1_size = 0;
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/* Set common default data first */
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xgmac_default_data(plat);
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@ -1122,6 +1147,92 @@ static int tc956xmac_xgmac3_default_data(struct pci_dev *pdev,
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plat->phy_interrupt_mode = false;
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#endif
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}
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/* Rx Queue size and flow control thresholds configuration */
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if (plat->port_num == RM_PF0_ID) {
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rxqueue0_size = mac0_rxq0_size;
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rxqueue1_size = mac0_rxq1_size;
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queue0_rfd = mac0_rxq0_rfd;
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queue0_rfa = mac0_rxq0_rfa;
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queue1_rfd = mac0_rxq1_rfd;
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queue1_rfa = mac0_rxq1_rfa;
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txqueue0_size = mac0_txq0_size;
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txqueue1_size = mac0_txq1_size;
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}
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if (plat->port_num == RM_PF1_ID) {
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rxqueue0_size = mac1_rxq0_size;
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rxqueue1_size = mac1_rxq1_size;
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queue0_rfd = mac1_rxq0_rfd;
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queue0_rfa = mac1_rxq0_rfa;
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queue1_rfd = mac1_rxq1_rfd;
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queue1_rfa = mac1_rxq1_rfa;
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txqueue0_size = mac1_txq0_size;
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txqueue1_size = mac1_txq1_size;
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}
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/* Validation of Queue size and Flow control thresholds and configuring local parameters to update registers*/
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if((rxqueue0_size + rxqueue1_size) <= MAX_RX_QUEUE_SIZE) {
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plat->rx_queues_cfg[0].size = rxqueue0_size;
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||||
plat->rx_queues_cfg[1].size = rxqueue1_size;
|
||||
} else {
|
||||
plat->rx_queues_cfg[0].size = RX_QUEUE0_SIZE; /* Default configuration when invalid input given */
|
||||
plat->rx_queues_cfg[1].size = RX_QUEUE1_SIZE;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid Rx Queue sizes passed rxq0_size=%d, rxq1_size=%d,Restoring default to rxq0_size=%d, rxq1_size=%d of port=%d\n",
|
||||
__func__, rxqueue0_size, rxqueue1_size, RX_QUEUE0_SIZE, RX_QUEUE1_SIZE, plat->port_num);
|
||||
|
||||
}
|
||||
|
||||
if((((queue0_rfd * SIZE_512B) + SIZE_1KB) < plat->rx_queues_cfg[0].size) &&
|
||||
(((queue0_rfa * SIZE_512B) + SIZE_1KB) < plat->rx_queues_cfg[0].size)) {
|
||||
plat->rx_queues_cfg[0].rfd = queue0_rfd;
|
||||
plat->rx_queues_cfg[0].rfa = queue0_rfa;
|
||||
} else {
|
||||
temp_var = ((plat->rx_queues_cfg[0].size - (((plat->rx_queues_cfg[0].size)*8)/10))/SIZE_512B); /* configuration to 80% of FIFO Size */
|
||||
if(temp_var >= 2) {
|
||||
temp_var = (temp_var - 2);
|
||||
} else {
|
||||
temp_var = 0;
|
||||
}
|
||||
plat->rx_queues_cfg[0].rfd = temp_var;
|
||||
plat->rx_queues_cfg[0].rfa = temp_var;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid Flow control threshold for Rx Queue-0 passed rxq0_rfd=%d, rxq0_rfa=%d,configuring to 80%% of Queue size, rxq0_rfd=%d, rxq0_rfa=%d of port=%d\n",
|
||||
__func__, queue0_rfd, queue0_rfa, plat->rx_queues_cfg[0].rfd, plat->rx_queues_cfg[0].rfa, plat->port_num);
|
||||
}
|
||||
|
||||
if((((queue1_rfd * SIZE_512B) + SIZE_1KB) < plat->rx_queues_cfg[1].size) &&
|
||||
(((queue1_rfa * SIZE_512B) + SIZE_1KB) < plat->rx_queues_cfg[1].size)) {
|
||||
plat->rx_queues_cfg[1].rfd = queue1_rfd;
|
||||
plat->rx_queues_cfg[1].rfa = queue1_rfa;
|
||||
} else {
|
||||
temp_var = ((plat->rx_queues_cfg[1].size - (((plat->rx_queues_cfg[1].size)*8)/10))/SIZE_512B); /* configuration to 80% of FIFO Size */
|
||||
if(temp_var >= 2){
|
||||
temp_var = (temp_var - 2);
|
||||
} else {
|
||||
temp_var = 0;
|
||||
}
|
||||
plat->rx_queues_cfg[1].rfd = temp_var;
|
||||
plat->rx_queues_cfg[1].rfa = temp_var;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid Flow control threshold for Rx Queue-1 passed rxq1_rfd=%d, rxq1_rfa=%d,configuring to 80%% of Queue size, rxq1_rfd=%d, rxq1_rfa=%d of port=%d\n",
|
||||
__func__, queue1_rfd, queue1_rfa, plat->rx_queues_cfg[1].rfd, plat->rx_queues_cfg[1].rfa, plat->port_num);
|
||||
}
|
||||
|
||||
if((txqueue0_size + txqueue1_size) <= MAX_TX_QUEUE_SIZE) {
|
||||
plat->tx_queues_cfg[0].size = txqueue0_size;
|
||||
plat->tx_queues_cfg[1].size = txqueue1_size;
|
||||
} else {
|
||||
plat->tx_queues_cfg[0].size = TX_QUEUE0_SIZE; /* Default configuration when invalid input given */
|
||||
plat->tx_queues_cfg[1].size = TX_QUEUE1_SIZE;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid Rx Queue sizes passed txq0_size=%d, txq1_size=%d, Restoring default to txq0_size=%d, txq1_size=%d of port=%d\n",
|
||||
__func__, rxqueue0_size, rxqueue1_size, TX_QUEUE0_SIZE, TX_QUEUE1_SIZE,plat->port_num);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1995,8 +2106,8 @@ static int tc956xmac_pci_probe(struct pci_dev *pdev,
|
||||
writel(0x02, res.addr + TC956X_PMA_LN_PCS2PMA_PHYMODE_R2);
|
||||
}
|
||||
|
||||
if ((tc956x_speed >= 1) && (tc956x_speed <= 3))
|
||||
tc956x_set_pci_speed(pdev, tc956x_speed);
|
||||
if ((pcie_link_speed >= 1) && (pcie_link_speed <= 3))
|
||||
tc956x_set_pci_speed(pdev, pcie_link_speed);
|
||||
#endif
|
||||
|
||||
#ifdef TC956X_PCIE_LINK_STATE_LATENCY_CTRL
|
||||
@ -2086,6 +2197,39 @@ static int tc956xmac_pci_probe(struct pci_dev *pdev,
|
||||
|
||||
plat->port_num = res.port_num;
|
||||
|
||||
/* User configured/Default Module parameters of TC956x*/
|
||||
NMSGPR_INFO(&pdev->dev, "User Configured/Default Module parameters of TC956x of Port-%d\n",plat->port_num);
|
||||
if (plat->port_num == RM_PF0_ID) {
|
||||
#ifdef TC956X_PCIE_GEN3_SETTING
|
||||
NMSGPR_INFO(&pdev->dev, "pcie_link_speed = %d \n", pcie_link_speed);
|
||||
#endif
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_interface = %d \n", mac0_interface);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_eee_enable = %d \n", mac0_eee_enable);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_lpi_timer = %d \n", mac0_lpi_timer);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_filter_phy_pause = %d \n", mac0_filter_phy_pause);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_rxq0_size = %d \n", mac0_rxq0_size);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_rxq1_size = %d \n", mac0_rxq1_size);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_rxq0_rfd = %d \n", mac0_rxq0_rfd);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_rxq0_rfa = %d \n", mac0_rxq0_rfa);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_rxq1_rfd = %d \n", mac0_rxq1_rfd);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_rxq1_rfa = %d \n", mac0_rxq1_rfa);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_txq0_size = %d \n", mac0_txq0_size);
|
||||
NMSGPR_INFO(&pdev->dev, "mac0_txq1_size = %d \n", mac0_txq1_size);
|
||||
} else if (plat->port_num == RM_PF1_ID) {
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_interface = %d \n", mac1_interface);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_eee_enable = %d \n", mac1_eee_enable);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_filter_phy_pause = %d \n", mac1_filter_phy_pause);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_lpi_timer = %d \n", mac1_lpi_timer);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_rxq0_size = %d \n", mac1_rxq0_size);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_rxq1_size = %d \n", mac1_rxq1_size);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_rxq0_rfd = %d \n", mac1_rxq0_rfd);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_rxq0_rfa = %d \n", mac1_rxq0_rfa);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_rxq1_rfd = %d \n", mac1_rxq1_rfd);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_rxq1_rfa = %d \n", mac1_rxq1_rfa);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_txq0_size = %d \n", mac1_txq0_size);
|
||||
NMSGPR_INFO(&pdev->dev, "mac1_txq1_size = %d \n", mac1_txq1_size);
|
||||
}
|
||||
|
||||
if (res.port_num == RM_PF0_ID) {
|
||||
plat->mdc_clk = PORT0_MDC;
|
||||
plat->c45_needed = PORT0_C45_STATE;
|
||||
@ -2098,60 +2242,60 @@ static int tc956xmac_pci_probe(struct pci_dev *pdev,
|
||||
|
||||
if (res.port_num == RM_PF0_ID) {
|
||||
/* Set the PORT0 interface mode to default, in case of invalid input */
|
||||
if ((tc956x_port0_interface == ENABLE_RGMII_INTERFACE) ||
|
||||
(tc956x_port0_interface > ENABLE_SGMII_INTERFACE))
|
||||
tc956x_port0_interface = ENABLE_XFI_INTERFACE;
|
||||
if ((mac0_interface == ENABLE_RGMII_INTERFACE) ||
|
||||
(mac0_interface > ENABLE_SGMII_INTERFACE))
|
||||
mac0_interface = ENABLE_XFI_INTERFACE;
|
||||
|
||||
res.port_interface = tc956x_port0_interface;
|
||||
res.port_interface = mac0_interface;
|
||||
}
|
||||
|
||||
if (res.port_num == RM_PF1_ID) {
|
||||
/* Set the PORT1 interface mode to default, in case of invalid input */
|
||||
if ((tc956x_port1_interface < ENABLE_RGMII_INTERFACE) ||
|
||||
(tc956x_port1_interface > ENABLE_SGMII_INTERFACE))
|
||||
tc956x_port1_interface = ENABLE_SGMII_INTERFACE;
|
||||
if ((mac1_interface < ENABLE_RGMII_INTERFACE) ||
|
||||
(mac1_interface > ENABLE_SGMII_INTERFACE))
|
||||
mac1_interface = ENABLE_SGMII_INTERFACE;
|
||||
|
||||
res.port_interface = tc956x_port1_interface;
|
||||
res.port_interface = mac1_interface;
|
||||
}
|
||||
|
||||
plat->port_interface = res.port_interface;
|
||||
|
||||
if (res.port_num == RM_PF0_ID) {
|
||||
if ((tc956x_port0_enable_eee != DISABLE) &&
|
||||
(tc956x_port0_enable_eee != ENABLE)) {
|
||||
tc956x_port0_enable_eee = DISABLE;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid tc956x_port0_enable_eee parameter passed. Restoring default to %d. Supported Values are 0 and 1.\n",
|
||||
__func__, tc956x_port1_enable_eee);
|
||||
if ((mac0_eee_enable != DISABLE) &&
|
||||
(mac0_eee_enable != ENABLE)) {
|
||||
mac0_eee_enable = DISABLE;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid mac0_eee_enable parameter passed. Restoring default to %d. Supported Values are 0 and 1.\n",
|
||||
__func__, mac1_eee_enable);
|
||||
}
|
||||
|
||||
if ((tc956x_port0_enable_eee == ENABLE) &&
|
||||
(tc956x_port0_lpi_auto_entry_timer > TC956X_MAX_LPI_AUTO_ENTRY_TIMER)) {
|
||||
tc956x_port0_lpi_auto_entry_timer = TC956XMAC_LPIET_600US;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid tc956x_port0_lpi_auto_entry_timer parameter passed. Restoring default to %d. Supported Values between %d and %d.\n",
|
||||
__func__, tc956x_port1_lpi_auto_entry_timer,
|
||||
if ((mac0_eee_enable == ENABLE) &&
|
||||
(mac0_lpi_timer > TC956X_MAX_LPI_AUTO_ENTRY_TIMER)) {
|
||||
mac0_lpi_timer = TC956XMAC_LPIET_600US;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid mac0_lpi_timer parameter passed. Restoring default to %d. Supported Values between %d and %d.\n",
|
||||
__func__, mac1_lpi_timer,
|
||||
TC956X_MIN_LPI_AUTO_ENTRY_TIMER, TC956X_MAX_LPI_AUTO_ENTRY_TIMER);
|
||||
}
|
||||
res.eee_enabled = tc956x_port0_enable_eee;
|
||||
res.tx_lpi_timer = tc956x_port0_lpi_auto_entry_timer;
|
||||
res.eee_enabled = mac0_eee_enable;
|
||||
res.tx_lpi_timer = mac0_lpi_timer;
|
||||
}
|
||||
|
||||
if (res.port_num == RM_PF1_ID) {
|
||||
if ((tc956x_port1_enable_eee != DISABLE) &&
|
||||
(tc956x_port1_enable_eee != ENABLE)) {
|
||||
tc956x_port1_enable_eee = DISABLE;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid tc956x_port1_enable_eee parameter passed. Restoring default to %d. Supported Values are 0 and 1.\n",
|
||||
__func__, tc956x_port1_enable_eee);
|
||||
if ((mac1_eee_enable != DISABLE) &&
|
||||
(mac1_eee_enable != ENABLE)) {
|
||||
mac1_eee_enable = DISABLE;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid mac1_eee_enable parameter passed. Restoring default to %d. Supported Values are 0 and 1.\n",
|
||||
__func__, mac1_eee_enable);
|
||||
}
|
||||
|
||||
if ((tc956x_port0_enable_eee == ENABLE) &&
|
||||
(tc956x_port1_lpi_auto_entry_timer > TC956X_MAX_LPI_AUTO_ENTRY_TIMER)) {
|
||||
tc956x_port1_lpi_auto_entry_timer = TC956XMAC_LPIET_600US;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid tc956x_port1_lpi_auto_entry_timer parameter passed. Restoring default to %d. Supported Values between %d and %d.\n",
|
||||
__func__, tc956x_port1_lpi_auto_entry_timer,
|
||||
if ((mac0_eee_enable == ENABLE) &&
|
||||
(mac1_lpi_timer > TC956X_MAX_LPI_AUTO_ENTRY_TIMER)) {
|
||||
mac1_lpi_timer = TC956XMAC_LPIET_600US;
|
||||
NMSGPR_INFO(&(pdev->dev), "%s: ERROR Invalid mac1_lpi_timer parameter passed. Restoring default to %d. Supported Values between %d and %d.\n",
|
||||
__func__, mac1_lpi_timer,
|
||||
TC956X_MIN_LPI_AUTO_ENTRY_TIMER, TC956X_MAX_LPI_AUTO_ENTRY_TIMER);
|
||||
}
|
||||
res.eee_enabled = tc956x_port1_enable_eee;
|
||||
res.tx_lpi_timer = tc956x_port1_lpi_auto_entry_timer;
|
||||
res.eee_enabled = mac1_eee_enable;
|
||||
res.tx_lpi_timer = mac1_lpi_timer;
|
||||
}
|
||||
|
||||
ret = info->setup(pdev, plat);
|
||||
@ -2867,8 +3011,8 @@ static int tc956x_pcie_resume(struct device *dev)
|
||||
writel(0x02, priv->ioaddr + TC956X_PMA_LN_PCS2PMA_PHYMODE_R2);
|
||||
}
|
||||
|
||||
if ((tc956x_speed >= 1) && (tc956x_speed <= 3))
|
||||
tc956x_set_pci_speed(pdev, tc956x_speed);
|
||||
if ((pcie_link_speed >= 1) && (pcie_link_speed <= 3))
|
||||
tc956x_set_pci_speed(pdev, pcie_link_speed);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -3107,51 +3251,131 @@ module_init(tc956x_init_module);
|
||||
module_exit(tc956x_exit_module);
|
||||
|
||||
#ifdef TC956X_PCIE_GEN3_SETTING
|
||||
module_param(tc956x_speed, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_speed,
|
||||
module_param(pcie_link_speed, uint, 0444);
|
||||
MODULE_PARM_DESC(pcie_link_speed,
|
||||
"PCIe speed Gen TC956X - default is 3, [1..3]");
|
||||
#endif
|
||||
|
||||
module_param(tc956x_port0_interface, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_port0_interface,
|
||||
module_param(mac0_interface, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_interface,
|
||||
"PORT0 interface mode TC956X - default is 1,\
|
||||
[0: USXGMII, 1: XFI, 2: RGMII(not supported), 3: SGMII]");
|
||||
|
||||
module_param(tc956x_port1_interface, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_port1_interface,
|
||||
module_param(mac1_interface, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_interface,
|
||||
"PORT1 interface mode TC956X - default is 3,\
|
||||
[0: USXGMII(not supported), 1: XFI(not supported), 2: RGMII, 3: SGMII]");
|
||||
|
||||
module_param(tc956x_port0_filter_phy_pause_frames, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_port0_filter_phy_pause_frames,
|
||||
module_param(mac0_filter_phy_pause, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_filter_phy_pause,
|
||||
"Filter PHY pause frames alone and pass Link partner pause frames to application in PORT0 - default is 0,\
|
||||
[0: DISABLE, 1: ENABLE]");
|
||||
|
||||
module_param(tc956x_port1_filter_phy_pause_frames, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_port1_filter_phy_pause_frames,
|
||||
module_param(mac1_filter_phy_pause, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_filter_phy_pause,
|
||||
"Filter PHY pause frames alone and pass Link partner pause frames to application in PORT1 - default is 0,\
|
||||
[0: DISABLE, 1: ENABLE]");
|
||||
|
||||
module_param(tc956x_port0_enable_eee, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_port0_enable_eee,
|
||||
module_param(mac0_eee_enable, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_eee_enable,
|
||||
"Enable/Disable EEE for Port 0 - default is 0,\
|
||||
[0: DISABLE, 1: ENABLE]");
|
||||
|
||||
module_param(tc956x_port0_lpi_auto_entry_timer, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_port0_lpi_auto_entry_timer,
|
||||
module_param(mac0_lpi_timer, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_lpi_timer,
|
||||
"LPI Automatic Entry Timer for Port 0 - default is 600 (us),\
|
||||
[Range Supported : 0..1048568 (us)]");
|
||||
|
||||
module_param(tc956x_port1_enable_eee, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_port1_enable_eee,
|
||||
module_param(mac1_eee_enable, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_eee_enable,
|
||||
"Enable/Disable EEE for Port 1 - default is 0,\
|
||||
[0: DISABLE, 1: ENABLE]");
|
||||
|
||||
module_param(tc956x_port1_lpi_auto_entry_timer, uint, 0444);
|
||||
MODULE_PARM_DESC(tc956x_port1_lpi_auto_entry_timer,
|
||||
module_param(mac1_lpi_timer, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_lpi_timer,
|
||||
"LPI Automatic Entry Timer for Port 1 - default is 600 (us),\
|
||||
[Range Supported : 0..1048568 (us)]");
|
||||
|
||||
module_param(mac0_rxq0_size, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_rxq0_size,
|
||||
"Rx Queue-0 size of Port 0 - default is 18432 (bytes),\
|
||||
[Range Supported : 3072..44032 (bytes)]");
|
||||
|
||||
module_param(mac0_rxq1_size, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_rxq1_size,
|
||||
"Rx Queue-1 size of Port 0 - default is 18432 (bytes),\
|
||||
[Range Supported : 3072..44032 (bytes)]");
|
||||
|
||||
module_param(mac0_rxq0_rfd, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_rxq0_rfd,
|
||||
"Flow control thresholds for Rx Queue-0 of Port 0 for disable - default is 24 (13KB) \
|
||||
[Range Supported : 0..84]");
|
||||
|
||||
module_param(mac0_rxq1_rfd, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_rxq1_rfd,
|
||||
"Flow control thresholds for Rx Queue-1 of Port 0 for disable - default is 24 (13KB)\
|
||||
[Range Supported : 0..84]");
|
||||
|
||||
module_param(mac0_rxq0_rfa, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_rxq0_rfa,
|
||||
"Flow control thresholds for Rx Queue-0 of Port 0 for enable - default is 24 (13KB) \
|
||||
[Range Supported : 0..84]");
|
||||
|
||||
module_param(mac0_rxq1_rfa, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_rxq1_rfa,
|
||||
"Flow control thresholds for Rx Queue-1 of Port 0 for enable - default is 24 (13KB)\
|
||||
[Range Supported : 0..84]");
|
||||
|
||||
module_param(mac0_txq0_size, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_txq0_size,
|
||||
"Tx Queue-0 size of Port 0 - default is 18432 (bytes),\
|
||||
[Range Supported : 3072..44032 (bytes)]");
|
||||
|
||||
module_param(mac0_txq1_size, uint, 0444);
|
||||
MODULE_PARM_DESC(mac0_txq1_size,
|
||||
"Tx Queue-1 size of Port 0 - default is 18432 (bytes),\
|
||||
[Range Supported : 3072..44032 (bytes)]");
|
||||
|
||||
module_param(mac1_rxq0_size, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_rxq0_size,
|
||||
"Rx Queue-0 size of Port 1 - default is 18432 (bytes),\
|
||||
[Range Supported : 3072..44032 (bytes)]");
|
||||
|
||||
module_param(mac1_rxq1_size, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_rxq1_size,
|
||||
"Rx Queue-1 size of Port 1 - default is 18432 (bytes),\
|
||||
[Range Supported : 3072..44032 (bytes)]");
|
||||
|
||||
module_param(mac1_rxq0_rfd, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_rxq0_rfd,
|
||||
"Flow control thresholds for Rx Queue-0 of Port 1 for disable - default is 24 (13KB) \
|
||||
[Range Supported : 0..84]");
|
||||
|
||||
module_param(mac1_rxq1_rfd, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_rxq1_rfd,
|
||||
"Flow control thresholds for Rx Queue-1 of Port 1 for disable - default is 24 (13KB)\
|
||||
[Range Supported : 0..84]");
|
||||
|
||||
module_param(mac1_rxq0_rfa, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_rxq0_rfa,
|
||||
"Flow control thresholds for Rx Queue-0 of Port 1 for enable - default is 24 (13KB) \
|
||||
[Range Supported : 0..84]");
|
||||
|
||||
module_param(mac1_rxq1_rfa, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_rxq1_rfa,
|
||||
"Flow control thresholds for Rx Queue-1 of Port 1 for enable - default is 24 (13KB)\
|
||||
[Range Supported : 0..84]");
|
||||
|
||||
module_param(mac1_txq0_size, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_txq0_size,
|
||||
"Tx Queue-0 size of Port 1 - default is 18432 (bytes),\
|
||||
[Range Supported : 3072..44032 (bytes)]");
|
||||
|
||||
module_param(mac1_txq1_size, uint, 0444);
|
||||
MODULE_PARM_DESC(mac1_txq1_size,
|
||||
"Tx Queue-1 size of Port 1 - default is 18432 (bytes),\
|
||||
[Range Supported : 3072..44032 (bytes)]");
|
||||
|
||||
MODULE_DESCRIPTION("TC956X PCI Express Ethernet Network Driver");
|
||||
MODULE_AUTHOR("Toshiba Electronic Devices & Storage Corporation");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -102,6 +102,8 @@
|
||||
* VERSION : 01-00-28
|
||||
* 03 Dec 2021 : 1. Version update
|
||||
* VERSION : 01-00-29
|
||||
* 08 Dec 2021 : 1. Version update
|
||||
* VERSION : 01-00-30
|
||||
*/
|
||||
|
||||
#ifndef __TC956XMAC_H__
|
||||
@ -154,7 +156,7 @@
|
||||
#ifdef TC956X
|
||||
|
||||
#define TC956X_RESOURCE_NAME "tc956x_pci-eth"
|
||||
#define DRV_MODULE_VERSION "V_01-00-29"
|
||||
#define DRV_MODULE_VERSION "V_01-00-30"
|
||||
#define TC956X_FW_MAX_SIZE (64*1024)
|
||||
|
||||
#define ATR_AXI4_SLV_BASE 0x0800
|
||||
|
||||
@ -42,6 +42,8 @@
|
||||
* VERSION : 01-00-09
|
||||
* 24 Aug 2021 : 1. Disable TC956X_PCIE_GEN3_SETTING and TC956X_LOAD_FW_HEADER macros and provide support via Makefile
|
||||
* VERSION : 01-00-10
|
||||
* 08 Dec 2021 : 1. Added Module parameters for Flow control thresholds per Queue.
|
||||
* VERSION : 01-00-30
|
||||
*/
|
||||
|
||||
#ifndef __TC956XMAC_PLATFORM_DATA
|
||||
@ -206,6 +208,9 @@ struct tc956xmac_rxq_cfg {
|
||||
u8 pkt_route;
|
||||
bool use_prio;
|
||||
u32 prio;
|
||||
u32 size;
|
||||
u32 rfd;
|
||||
u32 rfa;
|
||||
};
|
||||
|
||||
struct tc956xmac_txq_cfg {
|
||||
@ -221,6 +226,7 @@ struct tc956xmac_txq_cfg {
|
||||
u32 tbs_en;
|
||||
u32 tso_en;
|
||||
u8 traffic_class;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
struct tc956xmac_fpe_cfg {
|
||||
|
||||
@ -81,6 +81,8 @@
|
||||
* VERSION : 01-00-27
|
||||
* 03 Dec 2021 : 1. Added error check for phydev in tc956xmac_suspend().
|
||||
* VERSION : 01-00-29
|
||||
* 08 Dec 2021 : 1. Added Module parameter for Rx & Tx Queue Size configuration.
|
||||
* VERSION : 01-00-30
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
@ -3123,10 +3125,10 @@ static void tc956xmac_dma_operation_mode(struct tc956xmac_priv *priv)
|
||||
#ifdef TC956X
|
||||
switch (chan) {
|
||||
case 0:
|
||||
rxfifosz = RX_QUEUE0_SIZE;
|
||||
rxfifosz = priv->plat->rx_queues_cfg[0].size;
|
||||
break;
|
||||
case 1:
|
||||
rxfifosz = RX_QUEUE1_SIZE;
|
||||
rxfifosz = priv->plat->rx_queues_cfg[1].size;
|
||||
break;
|
||||
case 2:
|
||||
rxfifosz = RX_QUEUE2_SIZE;
|
||||
@ -3168,10 +3170,10 @@ static void tc956xmac_dma_operation_mode(struct tc956xmac_priv *priv)
|
||||
#ifdef TC956X
|
||||
switch (chan) {
|
||||
case 0:
|
||||
txfifosz = TX_QUEUE0_SIZE;
|
||||
txfifosz = priv->plat->tx_queues_cfg[0].size;
|
||||
break;
|
||||
case 1:
|
||||
txfifosz = TX_QUEUE1_SIZE;
|
||||
txfifosz = priv->plat->tx_queues_cfg[1].size;
|
||||
break;
|
||||
case 2:
|
||||
txfifosz = TX_QUEUE2_SIZE;
|
||||
@ -3377,12 +3379,12 @@ static void tc956xmac_set_dma_operation_mode(struct tc956xmac_priv *priv, u32 tx
|
||||
#ifdef TC956X
|
||||
switch (chan) {
|
||||
case 0:
|
||||
rxfifosz = RX_QUEUE0_SIZE;
|
||||
txfifosz = TX_QUEUE0_SIZE;
|
||||
rxfifosz = priv->plat->rx_queues_cfg[0].size;
|
||||
txfifosz = priv->plat->tx_queues_cfg[0].size;
|
||||
break;
|
||||
case 1:
|
||||
rxfifosz = RX_QUEUE1_SIZE;
|
||||
txfifosz = TX_QUEUE1_SIZE;
|
||||
rxfifosz = priv->plat->rx_queues_cfg[1].size;
|
||||
txfifosz = priv->plat->tx_queues_cfg[1].size;
|
||||
break;
|
||||
case 2:
|
||||
rxfifosz = RX_QUEUE2_SIZE;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user