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Merge v5.6-rc1 into android-mainline

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Linux 5.6-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Ifd1731444572c6f42c2dfb6ddeef8f76cdda8e66
This commit is contained in:
Greg Kroah-Hartman 2020-02-10 10:37:02 -08:00
commit a0c97da799
1012 changed files with 47257 additions and 20763 deletions
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6
Documentation/arm/microchip.rst
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@ -92,6 +92,12 @@ the Microchip website: http://www.microchip.com.
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001517A.pdf
- sam9x60
* Datasheet
http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579A.pdf
* ARM Cortex-A5 based SoCs
- sama5d3 family

3
Documentation/devicetree/bindings/arm/amlogic.yaml
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@ -59,6 +59,7 @@ properties:
- friendlyarm,nanopi-k2
- hardkernel,odroid-c2
- nexbox,a95x
- videostrong,kii-pro
- wetek,hub
- wetek,play2
- const: amlogic,meson-gxbb
@ -104,6 +105,7 @@ properties:
- enum:
- amlogic,p230
- amlogic,p231
- libretech,aml-s905d-pc
- phicomm,n1
- const: amlogic,s905d
- const: amlogic,meson-gxl
@ -115,6 +117,7 @@ properties:
- amlogic,q201
- khadas,vim2
- kingnovel,r-box-pro
- libretech,aml-s912-pc
- nexbox,a1
- tronsmart,vega-s96
- const: amlogic,s912

31
Documentation/devicetree/bindings/arm/atmel-at91.yaml
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@ -35,6 +35,16 @@ properties:
- atmel,at91sam9x60
- const: atmel,at91sam9
- items:
- enum:
- overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board
- overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board
- overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN
- overkiz,smartkiz # Overkiz SmartKiz Board
- const: atmel,at91sam9g25
- const: atmel,at91sam9x5
- const: atmel,at91sam9
- items:
- enum:
- atmel,at91sam9g15
@ -52,11 +62,32 @@ properties:
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D27 WLSOM1
items:
- const: microchip,sama5d27-wlsom1
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D27 WLSOM1 Evaluation Kit
items:
- const: microchip,sama5d27-wlsom1-ek
- const: microchip,sama5d27-wlsom1
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- items:
- const: atmel,sama5d27
- const: atmel,sama5d2
- const: atmel,sama5
- description: SAM9X60-EK board
items:
- const: microchip,sam9x60ek
- const: microchip,sam9x60
- const: atmel,at91sam9
- description: Nattis v2 board with Natte v2 power board
items:
- const: axentia,nattis-2

1
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
View File

@ -45,6 +45,7 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
"microchip,sam9x60-ddramc"
- reg: Should contain registers location and length
Examples:

15
Documentation/devicetree/bindings/arm/cpus.yaml
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@ -242,6 +242,21 @@ properties:
where voltage is in V, frequency is in MHz.
power-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description:
List of phandles and PM domain specifiers, as defined by bindings of the
PM domain provider (see also ../power_domain.txt).
power-domain-names:
$ref: '/schemas/types.yaml#/definitions/string-array'
description:
A list of power domain name strings sorted in the same order as the
power-domains property.
For PSCI based platforms, the name corresponding to the index of the PSCI
PM domain provider, must be "psci".
qcom,saw:
$ref: '/schemas/types.yaml#/definitions/phandle'
description: |

54
Documentation/devicetree/bindings/arm/fsl.yaml
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@ -128,6 +128,27 @@ properties:
- variscite,dt6customboard
- const: fsl,imx6q
- description: i.MX6Q Gateworks Ventana Boards
items:
- enum:
- gw,imx6q-gw51xx
- gw,imx6q-gw52xx
- gw,imx6q-gw53xx
- gw,imx6q-gw5400-a
- gw,imx6q-gw54xx
- gw,imx6q-gw551x
- gw,imx6q-gw552x
- gw,imx6q-gw553x
- gw,imx6q-gw560x
- gw,imx6q-gw5903
- gw,imx6q-gw5904
- gw,imx6q-gw5907
- gw,imx6q-gw5910
- gw,imx6q-gw5912
- gw,imx6q-gw5913
- const: gw,ventana
- const: fsl,imx6q
- description: i.MX6QP based Boards
items:
- enum:
@ -154,10 +175,31 @@ properties:
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
- const: fsl,imx6dl
- description: i.MX6DL Gateworks Ventana Boards
items:
- enum:
- gw,imx6dl-gw51xx
- gw,imx6dl-gw52xx
- gw,imx6dl-gw53xx
- gw,imx6dl-gw54xx
- gw,imx6dl-gw551x
- gw,imx6dl-gw552x
- gw,imx6dl-gw553x
- gw,imx6dl-gw560x
- gw,imx6dl-gw5903
- gw,imx6dl-gw5904
- gw,imx6dl-gw5907
- gw,imx6dl-gw5910
- gw,imx6dl-gw5912
- gw,imx6dl-gw5913
- const: gw,ventana
- const: fsl,imx6dl
- description: i.MX6SL based Boards
items:
- enum:
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
- kobo,tolino-shine3
- const: fsl,imx6sl
- description: i.MX6SLL based Boards
@ -172,6 +214,7 @@ properties:
- enum:
- fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board
- fsl,imx6sx-sdb # i.MX6 SoloX SDB Board
- fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board
- const: fsl,imx6sx
- description: i.MX6UL based Boards
@ -239,6 +282,7 @@ properties:
items:
- enum:
- fsl,imx7d-sdb # i.MX7 SabreSD Board
- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
@ -263,6 +307,7 @@ properties:
- description: i.MX7ULP based Boards
items:
- enum:
- ea,imx7ulp-com # i.MX7ULP Embedded Artists COM Board
- fsl,imx7ulp-evk # i.MX7ULP Evaluation Kit
- const: fsl,imx7ulp
@ -283,7 +328,9 @@ properties:
items:
- enum:
- boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board
- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
- fsl,imx8mq-evk # i.MX8MQ EVK Board
- google,imx8mq-phanbell # Google Coral Edge TPU
- purism,librem5-devkit # Purism Librem5 devkit
- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
@ -385,6 +432,13 @@ properties:
- fsl,ls2088a-rdb
- const: fsl,ls2088a
- description: LX2160A based Boards
items:
- enum:
- fsl,lx2160a-qds
- fsl,lx2160a-rdb
- const: fsl,lx2160a
- description: S32V234 based Boards
items:
- enum:

2
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
View File

@ -47,7 +47,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
cache-controller@1100000 {
system-cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
reg-names = "llcc_base", "llcc_broadcast_base";

104
Documentation/devicetree/bindings/arm/psci.yaml
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@ -102,6 +102,34 @@ properties:
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.txt
"#power-domain-cells":
description:
The number of cells in a PM domain specifier as per binding in [3].
Must be 0 as to represent a single PM domain.
ARM systems can have multiple cores, sometimes in an hierarchical
arrangement. This often, but not always, maps directly to the processor
power topology of the system. Individual nodes in a topology have their
own specific power states and can be better represented hierarchically.
For these cases, the definitions of the idle states for the CPUs and the
CPU topology, must conform to the binding in [3]. The idle states
themselves must conform to the binding in [4] and must specify the
arm,psci-suspend-param property.
It should also be noted that, in PSCI firmware v1.0 the OS-Initiated
(OSI) CPU suspend mode is introduced. Using a hierarchical representation
helps to implement support for OSI mode and OS implementations may choose
to mandate it.
[3] Documentation/devicetree/bindings/power/power_domain.txt
[4] Documentation/devicetree/bindings/power/domain-idle-state.txt
power-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description:
List of phandles and PM domain specifiers, as defined by bindings of the
PM domain provider.
required:
- compatible
@ -160,4 +188,80 @@ examples:
cpu_on = <0x95c10002>;
cpu_off = <0x95c10001>;
};
- |+
// Case 4: CPUs and CPU idle states described using the hierarchical model.
cpus {
#size-cells = <0>;
#address-cells = <1>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x100>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
};
idle-states {
CPU_PWRDN: cpu-power-down {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0000001>;
entry-latency-us = <10>;
exit-latency-us = <10>;
min-residency-us = <100>;
};
CLUSTER_RET: cluster-retention {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x1000011>;
entry-latency-us = <500>;
exit-latency-us = <500>;
min-residency-us = <2000>;
};
CLUSTER_PWRDN: cluster-power-down {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x1000031>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu-pd0 {
#power-domain-cells = <0>;
domain-idle-states = <&CPU_PWRDN>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD1: cpu-pd1 {
#power-domain-cells = <0>;
domain-idle-states = <&CPU_PWRDN>;
power-domains = <&CLUSTER_PD>;
};
CLUSTER_PD: cluster-pd {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
};
};
...

44
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -24,28 +24,30 @@ description: |
The 'SoC' element must be one of the following strings:
apq8016
apq8074
apq8084
apq8096
msm8916
msm8974
msm8992
msm8994
msm8996
mdm9615
ipq8074
sdm845
apq8016
apq8074
apq8084
apq8096
ipq8074
mdm9615
msm8916
msm8974
msm8992
msm8994
msm8996
sc7180
sdm845
The 'board' element must be one of the following strings:
cdp
liquid
dragonboard
mtp
sbc
hk01
qrd
cdp
dragonboard
hk01
idp
liquid
mtp
qrd
sbc
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
@ -144,4 +146,8 @@ properties:
- qcom,ipq8074-hk01
- const: qcom,ipq8074
- items:
- enum:
- qcom,sc7180-idp
- const: qcom,sc7180
...

9
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -409,6 +409,9 @@ properties:
- description: Pine64 RockPro64
items:
- enum:
- pine64,rockpro64-v2.1
- pine64,rockpro64-v2.0
- const: pine64,rockpro64
- const: rockchip,rk3399
@ -422,6 +425,12 @@ properties:
- const: radxa,rockpi4
- const: rockchip,rk3399
- description: Radxa ROCK Pi N10
items:
- const: radxa,rockpi-n10
- const: vamrs,rk3399pro-vmarc-som
- const: rockchip,rk3399pro
- description: Radxa Rock2 Square
items:
- const: radxa,rock2-square

2
Documentation/devicetree/bindings/arm/sprd.yaml → Documentation/devicetree/bindings/arm/sprd/sprd.yaml
View File

@ -2,7 +2,7 @@
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sprd.yaml#
$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Unisoc platforms device tree bindings

23
Documentation/devicetree/bindings/arm/sunxi.yaml
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@ -342,6 +342,16 @@ properties:
- const: libretech,all-h3-cc-h5
- const: allwinner,sun50i-h5
- description: Libre Computer Board ALL-H3-IT H5
items:
- const: libretech,all-h3-it-h5
- const: allwinner,sun50i-h5
- description: Libre Computer Board ALL-H5-CC H5
items:
- const: libretech,all-h5-cc-h5
- const: allwinner,sun50i-h5
- description: Lichee Pi One
items:
- const: licheepi,licheepi-one
@ -470,6 +480,12 @@ properties:
- const: emlid,neutis-n5
- const: allwinner,sun50i-h5
- description: Emlid Neutis N5H3 Developper Board
items:
- const: emlid,neutis-n5h3-devboard
- const: emlid,neutis-n5h3
- const: allwinner,sun8i-h3
- description: NextThing Co. CHIP
items:
- const: nextthing,chip
@ -599,11 +615,16 @@ properties:
- const: pine64,pine64-plus
- const: allwinner,sun50i-a64
- description: Pine64 PineH64
- description: Pine64 PineH64 model A
items:
- const: pine64,pine-h64
- const: allwinner,sun50i-h6
- description: Pine64 PineH64 model B
items:
- const: pine64,pine-h64-model-b
- const: allwinner,sun50i-h6
- description: Pine64 LTS
items:
- const: pine64,pine64-lts

36
Documentation/devicetree/bindings/arm/ux500.yaml Normal file
View File

@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ux500.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ux500 platforms device tree bindings
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: ST-Ericsson HREF (pre-v60)
items:
- const: st-ericsson,mop500
- const: st-ericsson,u8500
- description: ST-Ericsson HREF (v60+)
items:
- const: st-ericsson,hrefv60+
- const: st-ericsson,u8500
- description: Calao Systems Snowball
items:
- const: calaosystems,snowball-a9500
- const: st-ericsson,u9500
- description: Samsung Galaxy S III mini (GT-I8190)
items:
- const: samsung,golden
- const: st-ericsson,u8500

76
Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml Normal file
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@ -0,0 +1,76 @@
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A83t Display Engine 2/3 Clock Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
oneOf:
- const: allwinner,sun8i-a83t-de2-clk
- const: allwinner,sun8i-h3-de2-clk
- const: allwinner,sun8i-v3s-de2-clk
- const: allwinner,sun50i-a64-de2-clk
- const: allwinner,sun50i-h5-de2-clk
- const: allwinner,sun50i-h6-de2-clk
- items:
- const: allwinner,sun8i-r40-de2-clk
- const: allwinner,sun8i-h3-de2-clk
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: bus
- const: mod
resets:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/reset/sun8i-h3-ccu.h>
de2_clocks: clock@1000000 {
compatible = "allwinner,sun8i-h3-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

67
Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-de-clks.yaml Normal file
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@ -0,0 +1,67 @@
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 Display Engine Clock Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-de-clks
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: RAM Bus Clock
- description: Module Clock
clock-names:
items:
- const: mod
- const: dram
- const: bus
resets:
maxItems: 1
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
de_clocks: clock@3000000 {
compatible = "allwinner,sun9i-a80-de-clks";
reg = <0x03000000 0x30>;
clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
clock-names = "mod", "dram", "bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

59
Documentation/devicetree/bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml Normal file
View File

@ -0,0 +1,59 @@
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A80 USB Clock Controller Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
const: allwinner,sun9i-a80-usb-clocks
reg:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: High Frequency Oscillator
clock-names:
items:
- const: bus
- const: hosc
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun9i-a80-ccu.h>
usb_clocks: clock@a08000 {
compatible = "allwinner,sun9i-a80-usb-clks";
reg = <0x00a08000 0x8>;
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
clock-names = "bus", "hosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
...

34
Documentation/devicetree/bindings/clock/sun8i-de2.txt
View File

@ -1,34 +0,0 @@
Allwinner Display Engine 2.0/3.0 Clock Control Binding
------------------------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
- "allwinner,sun50i-h6-de3-clk"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
Three are needed:
- "mod": the display engine module clock (on A83T it's the DE PLL)
- "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
de2_clocks: clock@1000000 {
compatible = "allwinner,sun8i-h3-de2-clk";
reg = <0x01000000 0x100000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",
"mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};

28
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@ -1,28 +0,0 @@
Allwinner A80 Display Engine Clock Control Binding
--------------------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun9i-a80-de-clks"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
Three are needed:
- "mod": the display engine module clock
- "dram": the DRAM bus clock for the system
- "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
de_clocks: clock@3000000 {
compatible = "allwinner,sun9i-a80-de-clks";
reg = <0x03000000 0x30>;
clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
clock-names = "mod", "dram", "bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};

24
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@ -1,24 +0,0 @@
Allwinner A80 USB Clock Control Binding
---------------------------------------
Required properties :
- compatible: must contain one of the following compatibles:
- "allwinner,sun9i-a80-usb-clocks"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the USB subsystem. Two are needed:
- "bus": the bus clock for the whole USB subsystem
- "hosc": the high frequency oscillator (usually at 24MHz)
- clock-names: Must contain the clock names described just above
- #clock-cells : must contain 1
- #reset-cells : must contain 1
Example:
usb_clocks: clock@a08000 {
compatible = "allwinner,sun9i-a80-usb-clks";
reg = <0x00a08000 0x8>;
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
clock-names = "bus", "hosc";
#clock-cells = <1>;
#reset-cells = <1>;
};

1
Documentation/devicetree/bindings/display/mxsfb.txt
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@ -6,6 +6,7 @@ Required properties:
- compatible: Should be "fsl,imx23-lcdif" for i.MX23.
Should be "fsl,imx28-lcdif" for i.MX28.
Should be "fsl,imx6sx-lcdif" for i.MX6SX.
Should be "fsl,imx8mq-lcdif" for i.MX8MQ.
- reg: Address and length of the register set for LCDIF
- interrupts: Should contain LCDIF interrupt
- clocks: A list of phandle + clock-specifier pairs, one for each

4
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@ -2,9 +2,7 @@
* XDMA Controller
Required properties:
- compatible: Should be "atmel,<chip>-dma".
<chip> compatible description:
- sama5d4: first SoC adding the XDMAC
- compatible: Should be "atmel,sama5d4-dma" or "microchip,sam9x60-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain DMA interrupt.
- #dma-cells: Must be <1>, used to represent the number of integer cells in

1
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
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@ -18,6 +18,7 @@ properties:
- enum:
- amlogic,meson-g12a-mali
- realtek,rtd1619-mali
- rockchip,px30-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
reg:

2
Documentation/devicetree/bindings/iio/adc/at91-sama5d2_adc.txt
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@ -1,7 +1,7 @@
* AT91 SAMA5D2 Analog to Digital Converter (ADC)
Required properties:
- compatible: Should be "atmel,sama5d2-adc".
- compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
- reg: Should contain ADC registers location and length.
- interrupts: Should contain the IRQ line for the ADC.
- clocks: phandle to device clock.

2
Documentation/devicetree/bindings/media/atmel-isi.txt
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@ -2,7 +2,7 @@ Atmel Image Sensor Interface (ISI)
----------------------------------
Required properties for ISI:
- compatible: must be "atmel,at91sam9g45-isi".
- compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
- reg: physical base address and length of the registers set for the device.
- interrupts: should contain IRQ line for the ISI.
- clocks: list of clock specifiers, corresponding to entries in the clock-names

2
Documentation/devicetree/bindings/media/fsl-pxp.txt
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@ -8,7 +8,7 @@ i.MX SoCs from i.MX23 to i.MX7.
Required properties:
- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
imx6dl, imx6sl, imx6ul, imx6sx, imx6ull, or imx7d.
imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
- reg: the register base and size for the device registers
- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
- clock-names: should be "axi"

1
Documentation/devicetree/bindings/media/rc.yaml
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@ -123,6 +123,7 @@ properties:
- rc-su3000
- rc-tango
- rc-tanix-tx3mini
- rc-tanix-tx5max
- rc-tbs-nec
- rc-technisat-ts35
- rc-technisat-usb2

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@ -1,374 +0,0 @@
NVIDIA Tegra124 SoC EMC (external memory controller)
====================================================
Required properties :
- compatible : Should be "nvidia,tegra124-emc".
- reg : physical base address and length of the controller's registers.
- nvidia,memory-controller : phandle of the MC driver.
The node should contain a "emc-timings" subnode for each supported RAM type
(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
being its RAM_CODE.
Required properties for "emc-timings" nodes :
- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
used for.
Each "emc-timings" node should contain a "timing" subnode for every supported
EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
their unit address.
Required properties for "timing" nodes :
- clock-frequency : Should contain the memory clock rate in Hz.
- The following properties contain EMC timing characterization values
(specified in the board documentation) :
- nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG
- nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2
- nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3
- nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL
- nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
- nvidia,emc-cfg : EMC_CFG
- nvidia,emc-cfg-2 : EMC_CFG_2
- nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
- nvidia,emc-mode-1 : Mode Register 1
- nvidia,emc-mode-2 : Mode Register 2
- nvidia,emc-mode-4 : Mode Register 4
- nvidia,emc-mode-reset : Mode Register 0
- nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT
- nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
- nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2
- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
- nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL
- nvidia,emc-configuration : EMC timing characterization data. These are the
registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to
be specified, according to the board documentation:
EMC_RC
EMC_RFC
EMC_RFC_SLR
EMC_RAS
EMC_RP
EMC_R2W
EMC_W2R
EMC_R2P
EMC_W2P
EMC_RD_RCD
EMC_WR_RCD
EMC_RRD
EMC_REXT
EMC_WEXT
EMC_WDV
EMC_WDV_MASK
EMC_QUSE
EMC_QUSE_WIDTH
EMC_IBDLY
EMC_EINPUT
EMC_EINPUT_DURATION
EMC_PUTERM_EXTRA
EMC_PUTERM_WIDTH
EMC_PUTERM_ADJ
EMC_CDB_CNTL_1
EMC_CDB_CNTL_2
EMC_CDB_CNTL_3
EMC_QRST
EMC_QSAFE
EMC_RDV
EMC_RDV_MASK
EMC_REFRESH
EMC_BURST_REFRESH_NUM
EMC_PRE_REFRESH_REQ_CNT
EMC_PDEX2WR
EMC_PDEX2RD
EMC_PCHG2PDEN
EMC_ACT2PDEN
EMC_AR2PDEN
EMC_RW2PDEN
EMC_TXSR
EMC_TXSRDLL
EMC_TCKE
EMC_TCKESR
EMC_TPD
EMC_TFAW
EMC_TRPAB
EMC_TCLKSTABLE
EMC_TCLKSTOP
EMC_TREFBW
EMC_FBIO_CFG6
EMC_ODT_WRITE
EMC_ODT_READ
EMC_FBIO_CFG5
EMC_CFG_DIG_DLL
EMC_CFG_DIG_DLL_PERIOD
EMC_DLL_XFORM_DQS0
EMC_DLL_XFORM_DQS1
EMC_DLL_XFORM_DQS2
EMC_DLL_XFORM_DQS3
EMC_DLL_XFORM_DQS4
EMC_DLL_XFORM_DQS5
EMC_DLL_XFORM_DQS6
EMC_DLL_XFORM_DQS7
EMC_DLL_XFORM_DQS8
EMC_DLL_XFORM_DQS9
EMC_DLL_XFORM_DQS10
EMC_DLL_XFORM_DQS11
EMC_DLL_XFORM_DQS12
EMC_DLL_XFORM_DQS13
EMC_DLL_XFORM_DQS14
EMC_DLL_XFORM_DQS15
EMC_DLL_XFORM_QUSE0
EMC_DLL_XFORM_QUSE1
EMC_DLL_XFORM_QUSE2
EMC_DLL_XFORM_QUSE3
EMC_DLL_XFORM_QUSE4
EMC_DLL_XFORM_QUSE5
EMC_DLL_XFORM_QUSE6
EMC_DLL_XFORM_QUSE7
EMC_DLL_XFORM_ADDR0
EMC_DLL_XFORM_ADDR1
EMC_DLL_XFORM_ADDR2
EMC_DLL_XFORM_ADDR3
EMC_DLL_XFORM_ADDR4
EMC_DLL_XFORM_ADDR5
EMC_DLL_XFORM_QUSE8
EMC_DLL_XFORM_QUSE9
EMC_DLL_XFORM_QUSE10
EMC_DLL_XFORM_QUSE11
EMC_DLL_XFORM_QUSE12
EMC_DLL_XFORM_QUSE13
EMC_DLL_XFORM_QUSE14
EMC_DLL_XFORM_QUSE15
EMC_DLI_TRIM_TXDQS0
EMC_DLI_TRIM_TXDQS1
EMC_DLI_TRIM_TXDQS2
EMC_DLI_TRIM_TXDQS3
EMC_DLI_TRIM_TXDQS4
EMC_DLI_TRIM_TXDQS5
EMC_DLI_TRIM_TXDQS6
EMC_DLI_TRIM_TXDQS7
EMC_DLI_TRIM_TXDQS8
EMC_DLI_TRIM_TXDQS9
EMC_DLI_TRIM_TXDQS10
EMC_DLI_TRIM_TXDQS11
EMC_DLI_TRIM_TXDQS12
EMC_DLI_TRIM_TXDQS13
EMC_DLI_TRIM_TXDQS14
EMC_DLI_TRIM_TXDQS15
EMC_DLL_XFORM_DQ0
EMC_DLL_XFORM_DQ1
EMC_DLL_XFORM_DQ2
EMC_DLL_XFORM_DQ3
EMC_DLL_XFORM_DQ4
EMC_DLL_XFORM_DQ5
EMC_DLL_XFORM_DQ6
EMC_DLL_XFORM_DQ7
EMC_XM2CMDPADCTRL
EMC_XM2CMDPADCTRL4
EMC_XM2CMDPADCTRL5
EMC_XM2DQPADCTRL2
EMC_XM2DQPADCTRL3
EMC_XM2CLKPADCTRL
EMC_XM2CLKPADCTRL2
EMC_XM2COMPPADCTRL
EMC_XM2VTTGENPADCTRL
EMC_XM2VTTGENPADCTRL2
EMC_XM2VTTGENPADCTRL3
EMC_XM2DQSPADCTRL3
EMC_XM2DQSPADCTRL4
EMC_XM2DQSPADCTRL5
EMC_XM2DQSPADCTRL6
EMC_DSR_VTTGEN_DRV
EMC_TXDSRVTTGEN
EMC_FBIO_SPARE
EMC_ZCAL_WAIT_CNT
EMC_MRS_WAIT_CNT2
EMC_CTT
EMC_CTT_DURATION
EMC_CFG_PIPE
EMC_DYN_SELF_REF_CONTROL
EMC_QPOP
Example SoC include file:
/ {
emc@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
nvidia,memory-controller = <&mc>;
};
};
Example board file:
/ {
emc@7001b000 {
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emc-zcal-cnt-long = <0x00000042>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-ctt-term-ctrl = <0x00000802>;
nvidia,emc-cfg = <0x73240000>;
nvidia,emc-cfg-2 = <0x000008c5>;
nvidia,emc-sel-dpd-ctrl = <0x00040128>;
nvidia,emc-bgbias-ctl0 = <0x00000008>;
nvidia,emc-auto-cal-config = <0xa1430000>;
nvidia,emc-auto-cal-config2 = <0x00000000>;
nvidia,emc-auto-cal-config3 = <0x00000000>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-4 = <0x00000000>;
nvidia,emc-configuration = <
0x00000000 /* EMC_RC */
0x00000003 /* EMC_RFC */
0x00000000 /* EMC_RFC_SLR */
0x00000000 /* EMC_RAS */
0x00000000 /* EMC_RP */
0x00000004 /* EMC_R2W */
0x0000000a /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x0000000b /* EMC_W2P */
0x00000000 /* EMC_RD_RCD */
0x00000000 /* EMC_WR_RCD */
0x00000003 /* EMC_RRD */
0x00000003 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000006 /* EMC_WDV */
0x00000006 /* EMC_WDV_MASK */
0x00000006 /* EMC_QUSE */
0x00000002 /* EMC_QUSE_WIDTH */
0x00000000 /* EMC_IBDLY */
0x00000005 /* EMC_EINPUT */
0x00000005 /* EMC_EINPUT_DURATION */
0x00010000 /* EMC_PUTERM_EXTRA */
0x00000003 /* EMC_PUTERM_WIDTH */
0x00000000 /* EMC_PUTERM_ADJ */
0x00000000 /* EMC_CDB_CNTL_1 */
0x00000000 /* EMC_CDB_CNTL_2 */
0x00000000 /* EMC_CDB_CNTL_3 */
0x00000004 /* EMC_QRST */
0x0000000c /* EMC_QSAFE */
0x0000000d /* EMC_RDV */
0x0000000f /* EMC_RDV_MASK */
0x00000060 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x00000002 /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x00000007 /* EMC_AR2PDEN */
0x0000000f /* EMC_RW2PDEN */
0x00000005 /* EMC_TXSR */
0x00000005 /* EMC_TXSRDLL */
0x00000004 /* EMC_TCKE */
0x00000005 /* EMC_TCKESR */
0x00000004 /* EMC_TPD */
0x00000000 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000005 /* EMC_TCLKSTABLE */
0x00000005 /* EMC_TCLKSTOP */
0x00000064 /* EMC_TREFBW */
0x00000000 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x106aa298 /* EMC_FBIO_CFG5 */
0x002c00a0 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00064000 /* EMC_DLL_XFORM_DQS0 */
0x00064000 /* EMC_DLL_XFORM_DQS1 */
0x00064000 /* EMC_DLL_XFORM_DQS2 */
0x00064000 /* EMC_DLL_XFORM_DQS3 */
0x00064000 /* EMC_DLL_XFORM_DQS4 */
0x00064000 /* EMC_DLL_XFORM_DQS5 */
0x00064000 /* EMC_DLL_XFORM_DQS6 */
0x00064000 /* EMC_DLL_XFORM_DQS7 */
0x00064000 /* EMC_DLL_XFORM_DQS8 */
0x00064000 /* EMC_DLL_XFORM_DQS9 */
0x00064000 /* EMC_DLL_XFORM_DQS10 */
0x00064000 /* EMC_DLL_XFORM_DQS11 */
0x00064000 /* EMC_DLL_XFORM_DQS12 */
0x00064000 /* EMC_DLL_XFORM_DQS13 */
0x00064000 /* EMC_DLL_XFORM_DQS14 */
0x00064000 /* EMC_DLL_XFORM_DQS15 */
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLL_XFORM_ADDR0 */
0x00000000 /* EMC_DLL_XFORM_ADDR1 */
0x00000000 /* EMC_DLL_XFORM_ADDR2 */
0x00000000 /* EMC_DLL_XFORM_ADDR3 */
0x00000000 /* EMC_DLL_XFORM_ADDR4 */
0x00000000 /* EMC_DLL_XFORM_ADDR5 */
0x00000000 /* EMC_DLL_XFORM_QUSE8 */
0x00000000 /* EMC_DLL_XFORM_QUSE9 */
0x00000000 /* EMC_DLL_XFORM_QUSE10 */
0x00000000 /* EMC_DLL_XFORM_QUSE11 */
0x00000000 /* EMC_DLL_XFORM_QUSE12 */
0x00000000 /* EMC_DLL_XFORM_QUSE13 */
0x00000000 /* EMC_DLL_XFORM_QUSE14 */
0x00000000 /* EMC_DLL_XFORM_QUSE15 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
0x000fc000 /* EMC_DLL_XFORM_DQ0 */
0x000fc000 /* EMC_DLL_XFORM_DQ1 */
0x000fc000 /* EMC_DLL_XFORM_DQ2 */
0x000fc000 /* EMC_DLL_XFORM_DQ3 */
0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
0x10000280 /* EMC_XM2CMDPADCTRL */
0x00000000 /* EMC_XM2CMDPADCTRL4 */
0x00111111 /* EMC_XM2CMDPADCTRL5 */
0x00000000 /* EMC_XM2DQPADCTRL2 */
0x00000000 /* EMC_XM2DQPADCTRL3 */
0x77ffc081 /* EMC_XM2CLKPADCTRL */
0x00000e0e /* EMC_XM2CLKPADCTRL2 */
0x81f1f108 /* EMC_XM2COMPPADCTRL */
0x07070004 /* EMC_XM2VTTGENPADCTRL */
0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
0x51451400 /* EMC_XM2DQSPADCTRL3 */
0x00514514 /* EMC_XM2DQSPADCTRL4 */
0x00514514 /* EMC_XM2DQSPADCTRL5 */
0x51451400 /* EMC_XM2DQSPADCTRL6 */
0x0000003f /* EMC_DSR_VTTGEN_DRV */
0x00000007 /* EMC_TXDSRVTTGEN */
0x00000000 /* EMC_FBIO_SPARE */
0x00000042 /* EMC_ZCAL_WAIT_CNT */
0x000e000e /* EMC_MRS_WAIT_CNT2 */
0x00000000 /* EMC_CTT */
0x00000003 /* EMC_CTT_DURATION */
0x0000f2f3 /* EMC_CFG_PIPE */
0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a /* EMC_QPOP */
>;
};
};
};
};

528
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@ -0,0 +1,528 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 SoC External Memory Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The EMC interfaces with the off-chip SDRAM to service the request stream
sent from the memory controller.
properties:
compatible:
const: nvidia,tegra124-emc
reg:
maxItems: 1
clocks:
items:
- description: external memory clock
clock-names:
items:
- const: emc
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the memory controller node
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
this timing set is used for
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
external memory clock rate in Hz
minimum: 1000000
maximum: 1000000000
nvidia,emc-auto-cal-config:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG register for this set of
timings
nvidia,emc-auto-cal-config2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG2 register for this set of
timings
nvidia,emc-auto-cal-config3:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG3 register for this set of
timings
nvidia,emc-auto-cal-interval:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
description:
pad calibration interval in microseconds
minimum: 0
maximum: 2097151
nvidia,emc-bgbias-ctl0:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_BGBIAS_CTL0 register for this set of timings
nvidia,emc-cfg:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CFG register for this set of timings
nvidia,emc-cfg-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CFG_2 register for this set of timings
nvidia,emc-ctt-term-ctrl:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CTT_TERM_CTRL register for this set of timings
nvidia,emc-mode-1:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW register for this set of timings
nvidia,emc-mode-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW2 register for this set of timings
nvidia,emc-mode-4:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW4 register for this set of timings
nvidia,emc-mode-reset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
reset value of the EMC_MRS register for this set of timings
nvidia,emc-mrs-wait-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMR_MRS_WAIT_CNT register for this set of timings
nvidia,emc-sel-dpd-ctrl:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_SEL_DPD_CTRL register for this set of timings
nvidia,emc-xm2dqspadctrl2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_XM2DQSPADCTRL2 register for this set of timings
nvidia,emc-zcal-cnt-long:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
description:
number of EMC clocks to wait before issuing any commands after
clock change
minimum: 0
maximum: 1023
nvidia,emc-zcal-interval:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_ZCAL_INTERVAL register for this set of timings
nvidia,emc-configuration:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
description:
EMC timing characterization data. These are the registers (see
section "15.6.2 EMC Registers" in the TRM) whose values need to
be specified, according to the board documentation.
items:
- description: EMC_RC
- description: EMC_RFC
- description: EMC_RFC_SLR
- description: EMC_RAS
- description: EMC_RP
- description: EMC_R2W
- description: EMC_W2R
- description: EMC_R2P
- description: EMC_W2P
- description: EMC_RD_RCD
- description: EMC_WR_RCD
- description: EMC_RRD
- description: EMC_REXT
- description: EMC_WEXT
- description: EMC_WDV
- description: EMC_WDV_MASK
- description: EMC_QUSE
- description: EMC_QUSE_WIDTH
- description: EMC_IBDLY
- description: EMC_EINPUT
- description: EMC_EINPUT_DURATION
- description: EMC_PUTERM_EXTRA
- description: EMC_PUTERM_WIDTH
- description: EMC_PUTERM_ADJ
- description: EMC_CDB_CNTL_1
- description: EMC_CDB_CNTL_2
- description: EMC_CDB_CNTL_3
- description: EMC_QRST
- description: EMC_QSAFE
- description: EMC_RDV
- description: EMC_RDV_MASK
- description: EMC_REFRESH
- description: EMC_BURST_REFRESH_NUM
- description: EMC_PRE_REFRESH_REQ_CNT
- description: EMC_PDEX2WR
- description: EMC_PDEX2RD
- description: EMC_PCHG2PDEN
- description: EMC_ACT2PDEN
- description: EMC_AR2PDEN
- description: EMC_RW2PDEN
- description: EMC_TXSR
- description: EMC_TXSRDLL
- description: EMC_TCKE
- description: EMC_TCKESR
- description: EMC_TPD
- description: EMC_TFAW
- description: EMC_TRPAB
- description: EMC_TCLKSTABLE
- description: EMC_TCLKSTOP
- description: EMC_TREFBW
- description: EMC_FBIO_CFG6
- description: EMC_ODT_WRITE
- description: EMC_ODT_READ
- description: EMC_FBIO_CFG5
- description: EMC_CFG_DIG_DLL
- description: EMC_CFG_DIG_DLL_PERIOD
- description: EMC_DLL_XFORM_DQS0
- description: EMC_DLL_XFORM_DQS1
- description: EMC_DLL_XFORM_DQS2
- description: EMC_DLL_XFORM_DQS3
- description: EMC_DLL_XFORM_DQS4
- description: EMC_DLL_XFORM_DQS5
- description: EMC_DLL_XFORM_DQS6
- description: EMC_DLL_XFORM_DQS7
- description: EMC_DLL_XFORM_DQS8
- description: EMC_DLL_XFORM_DQS9
- description: EMC_DLL_XFORM_DQS10
- description: EMC_DLL_XFORM_DQS11
- description: EMC_DLL_XFORM_DQS12
- description: EMC_DLL_XFORM_DQS13
- description: EMC_DLL_XFORM_DQS14
- description: EMC_DLL_XFORM_DQS15
- description: EMC_DLL_XFORM_QUSE0
- description: EMC_DLL_XFORM_QUSE1
- description: EMC_DLL_XFORM_QUSE2
- description: EMC_DLL_XFORM_QUSE3
- description: EMC_DLL_XFORM_QUSE4
- description: EMC_DLL_XFORM_QUSE5
- description: EMC_DLL_XFORM_QUSE6
- description: EMC_DLL_XFORM_QUSE7
- description: EMC_DLL_XFORM_ADDR0
- description: EMC_DLL_XFORM_ADDR1
- description: EMC_DLL_XFORM_ADDR2
- description: EMC_DLL_XFORM_ADDR3
- description: EMC_DLL_XFORM_ADDR4
- description: EMC_DLL_XFORM_ADDR5
- description: EMC_DLL_XFORM_QUSE8
- description: EMC_DLL_XFORM_QUSE9
- description: EMC_DLL_XFORM_QUSE10
- description: EMC_DLL_XFORM_QUSE11
- description: EMC_DLL_XFORM_QUSE12
- description: EMC_DLL_XFORM_QUSE13
- description: EMC_DLL_XFORM_QUSE14
- description: EMC_DLL_XFORM_QUSE15
- description: EMC_DLI_TRIM_TXDQS0
- description: EMC_DLI_TRIM_TXDQS1
- description: EMC_DLI_TRIM_TXDQS2
- description: EMC_DLI_TRIM_TXDQS3
- description: EMC_DLI_TRIM_TXDQS4
- description: EMC_DLI_TRIM_TXDQS5
- description: EMC_DLI_TRIM_TXDQS6
- description: EMC_DLI_TRIM_TXDQS7
- description: EMC_DLI_TRIM_TXDQS8
- description: EMC_DLI_TRIM_TXDQS9
- description: EMC_DLI_TRIM_TXDQS10
- description: EMC_DLI_TRIM_TXDQS11
- description: EMC_DLI_TRIM_TXDQS12
- description: EMC_DLI_TRIM_TXDQS13
- description: EMC_DLI_TRIM_TXDQS14
- description: EMC_DLI_TRIM_TXDQS15
- description: EMC_DLL_XFORM_DQ0
- description: EMC_DLL_XFORM_DQ1
- description: EMC_DLL_XFORM_DQ2
- description: EMC_DLL_XFORM_DQ3
- description: EMC_DLL_XFORM_DQ4
- description: EMC_DLL_XFORM_DQ5
- description: EMC_DLL_XFORM_DQ6
- description: EMC_DLL_XFORM_DQ7
- description: EMC_XM2CMDPADCTRL
- description: EMC_XM2CMDPADCTRL4
- description: EMC_XM2CMDPADCTRL5
- description: EMC_XM2DQPADCTRL2
- description: EMC_XM2DQPADCTRL3
- description: EMC_XM2CLKPADCTRL
- description: EMC_XM2CLKPADCTRL2
- description: EMC_XM2COMPPADCTRL
- description: EMC_XM2VTTGENPADCTRL
- description: EMC_XM2VTTGENPADCTRL2
- description: EMC_XM2VTTGENPADCTRL3
- description: EMC_XM2DQSPADCTRL3
- description: EMC_XM2DQSPADCTRL4
- description: EMC_XM2DQSPADCTRL5
- description: EMC_XM2DQSPADCTRL6
- description: EMC_DSR_VTTGEN_DRV
- description: EMC_TXDSRVTTGEN
- description: EMC_FBIO_SPARE
- description: EMC_ZCAL_WAIT_CNT
- description: EMC_MRS_WAIT_CNT2
- description: EMC_CTT
- description: EMC_CTT_DURATION
- description: EMC_CFG_PIPE
- description: EMC_DYN_SELF_REF_CONTROL
- description: EMC_QPOP
required:
- clock-frequency
- nvidia,emc-auto-cal-config
- nvidia,emc-auto-cal-config2
- nvidia,emc-auto-cal-config3
- nvidia,emc-auto-cal-interval
- nvidia,emc-bgbias-ctl0
- nvidia,emc-cfg
- nvidia,emc-cfg-2
- nvidia,emc-ctt-term-ctrl
- nvidia,emc-mode-1
- nvidia,emc-mode-2
- nvidia,emc-mode-4
- nvidia,emc-mode-reset
- nvidia,emc-mrs-wait-cnt
- nvidia,emc-sel-dpd-ctrl
- nvidia,emc-xm2dqspadctrl2
- nvidia,emc-zcal-cnt-long
- nvidia,emc-zcal-interval
- nvidia,emc-configuration
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- nvidia,memory-controller
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
};
external-memory-controller@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
clocks = <&car TEGRA124_CLK_EMC>;
clock-names = "emc";
nvidia,memory-controller = <&mc>;
emc-timings-0 {
nvidia,ram-code = <3>;
timing-0 {
clock-frequency = <12750000>;
nvidia,emc-zcal-cnt-long = <0x00000042>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-ctt-term-ctrl = <0x00000802>;
nvidia,emc-cfg = <0x73240000>;
nvidia,emc-cfg-2 = <0x000008c5>;
nvidia,emc-sel-dpd-ctrl = <0x00040128>;
nvidia,emc-bgbias-ctl0 = <0x00000008>;
nvidia,emc-auto-cal-config = <0xa1430000>;
nvidia,emc-auto-cal-config2 = <0x00000000>;
nvidia,emc-auto-cal-config3 = <0x00000000>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-4 = <0x00000000>;
nvidia,emc-configuration = <
0x00000000 /* EMC_RC */
0x00000003 /* EMC_RFC */
0x00000000 /* EMC_RFC_SLR */
0x00000000 /* EMC_RAS */
0x00000000 /* EMC_RP */
0x00000004 /* EMC_R2W */
0x0000000a /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x0000000b /* EMC_W2P */
0x00000000 /* EMC_RD_RCD */
0x00000000 /* EMC_WR_RCD */
0x00000003 /* EMC_RRD */
0x00000003 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000006 /* EMC_WDV */
0x00000006 /* EMC_WDV_MASK */
0x00000006 /* EMC_QUSE */
0x00000002 /* EMC_QUSE_WIDTH */
0x00000000 /* EMC_IBDLY */
0x00000005 /* EMC_EINPUT */
0x00000005 /* EMC_EINPUT_DURATION */
0x00010000 /* EMC_PUTERM_EXTRA */
0x00000003 /* EMC_PUTERM_WIDTH */
0x00000000 /* EMC_PUTERM_ADJ */
0x00000000 /* EMC_CDB_CNTL_1 */
0x00000000 /* EMC_CDB_CNTL_2 */
0x00000000 /* EMC_CDB_CNTL_3 */
0x00000004 /* EMC_QRST */
0x0000000c /* EMC_QSAFE */
0x0000000d /* EMC_RDV */
0x0000000f /* EMC_RDV_MASK */
0x00000060 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x00000002 /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x00000007 /* EMC_AR2PDEN */
0x0000000f /* EMC_RW2PDEN */
0x00000005 /* EMC_TXSR */
0x00000005 /* EMC_TXSRDLL */
0x00000004 /* EMC_TCKE */
0x00000005 /* EMC_TCKESR */
0x00000004 /* EMC_TPD */
0x00000000 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000005 /* EMC_TCLKSTABLE */
0x00000005 /* EMC_TCLKSTOP */
0x00000064 /* EMC_TREFBW */
0x00000000 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x106aa298 /* EMC_FBIO_CFG5 */
0x002c00a0 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00064000 /* EMC_DLL_XFORM_DQS0 */
0x00064000 /* EMC_DLL_XFORM_DQS1 */
0x00064000 /* EMC_DLL_XFORM_DQS2 */
0x00064000 /* EMC_DLL_XFORM_DQS3 */
0x00064000 /* EMC_DLL_XFORM_DQS4 */
0x00064000 /* EMC_DLL_XFORM_DQS5 */
0x00064000 /* EMC_DLL_XFORM_DQS6 */
0x00064000 /* EMC_DLL_XFORM_DQS7 */
0x00064000 /* EMC_DLL_XFORM_DQS8 */
0x00064000 /* EMC_DLL_XFORM_DQS9 */
0x00064000 /* EMC_DLL_XFORM_DQS10 */
0x00064000 /* EMC_DLL_XFORM_DQS11 */
0x00064000 /* EMC_DLL_XFORM_DQS12 */
0x00064000 /* EMC_DLL_XFORM_DQS13 */
0x00064000 /* EMC_DLL_XFORM_DQS14 */
0x00064000 /* EMC_DLL_XFORM_DQS15 */
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLL_XFORM_ADDR0 */
0x00000000 /* EMC_DLL_XFORM_ADDR1 */
0x00000000 /* EMC_DLL_XFORM_ADDR2 */
0x00000000 /* EMC_DLL_XFORM_ADDR3 */
0x00000000 /* EMC_DLL_XFORM_ADDR4 */
0x00000000 /* EMC_DLL_XFORM_ADDR5 */
0x00000000 /* EMC_DLL_XFORM_QUSE8 */
0x00000000 /* EMC_DLL_XFORM_QUSE9 */
0x00000000 /* EMC_DLL_XFORM_QUSE10 */
0x00000000 /* EMC_DLL_XFORM_QUSE11 */
0x00000000 /* EMC_DLL_XFORM_QUSE12 */
0x00000000 /* EMC_DLL_XFORM_QUSE13 */
0x00000000 /* EMC_DLL_XFORM_QUSE14 */
0x00000000 /* EMC_DLL_XFORM_QUSE15 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
0x000fc000 /* EMC_DLL_XFORM_DQ0 */
0x000fc000 /* EMC_DLL_XFORM_DQ1 */
0x000fc000 /* EMC_DLL_XFORM_DQ2 */
0x000fc000 /* EMC_DLL_XFORM_DQ3 */
0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
0x10000280 /* EMC_XM2CMDPADCTRL */
0x00000000 /* EMC_XM2CMDPADCTRL4 */
0x00111111 /* EMC_XM2CMDPADCTRL5 */
0x00000000 /* EMC_XM2DQPADCTRL2 */
0x00000000 /* EMC_XM2DQPADCTRL3 */
0x77ffc081 /* EMC_XM2CLKPADCTRL */
0x00000e0e /* EMC_XM2CLKPADCTRL2 */
0x81f1f108 /* EMC_XM2COMPPADCTRL */
0x07070004 /* EMC_XM2VTTGENPADCTRL */
0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
0x51451400 /* EMC_XM2DQSPADCTRL3 */
0x00514514 /* EMC_XM2DQSPADCTRL4 */
0x00514514 /* EMC_XM2DQSPADCTRL5 */
0x51451400 /* EMC_XM2DQSPADCTRL6 */
0x0000003f /* EMC_DSR_VTTGEN_DRV */
0x00000007 /* EMC_TXDSRVTTGEN */
0x00000000 /* EMC_FBIO_SPARE */
0x00000042 /* EMC_ZCAL_WAIT_CNT */
0x000e000e /* EMC_MRS_WAIT_CNT2 */
0x00000000 /* EMC_CTT */
0x00000003 /* EMC_CTT_DURATION */
0x0000f2f3 /* EMC_CFG_PIPE */
0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a /* EMC_QPOP */
>;
};
};
};

130
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml Normal file
View File

@ -0,0 +1,130 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) SoC Memory Controller
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
handles memory requests for 40-bit virtual addresses from internal clients
and arbitrates among them to allocate memory bandwidth.
Up to 15 GiB of physical memory can be supported. Security features such as
encryption of traffic to and from DRAM via general security apertures are
available for video and other secure applications, as well as DRAM ECC for
automotive safety applications (single bit error correction and double bit
error detection).
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
items:
- enum:
- nvidia,tegra186-mc
- nvidia,tegra194-mc
reg:
maxItems: 1
interrupts:
maxItems: 1
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
dma-ranges: true
patternProperties:
"^external-memory-controller@[0-9a-f]+$":
description:
The bulk of the work involved in controlling the external memory
controller on NVIDIA Tegra186 and later is performed on the BPMP. This
coprocessor exposes the EMC clock that is used to set the frequency at
which the external memory is clocked and a remote procedure call that
can be used to obtain the set of available frequencies.
type: object
properties:
compatible:
items:
- enum:
- nvidia,tegra186-emc
- nvidia,tegra194-emc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: external memory clock
clock-names:
items:
- const: emc
nvidia,bpmp:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the node representing the BPMP
required:
- compatible
- reg
- interrupts
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0xb0000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>;
/*
* Memory clients have access to all 40 bits that the memory
* controller can address.
*/
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
external-memory-controller@2c60000 {
compatible = "nvidia,tegra186-emc";
reg = <0x0 0x02c60000 0x0 0x50000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_EMC>;
clock-names = "emc";
nvidia,bpmp = <&bpmp>;
};
};
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
#clock-cells = <1>;
};

4
Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
View File

@ -3,7 +3,9 @@
The GPBR are a set of battery-backed registers.
Required properties:
- compatible: "atmel,at91sam9260-gpbr", "syscon"
- compatible: Should be one of the following:
"atmel,at91sam9260-gpbr", "syscon"
"microchip,sam9x60-gpbr", "syscon"
- reg: contains offset/length value of the GPBR memory
region.

1
Documentation/devicetree/bindings/mfd/atmel-matrix.txt
View File

@ -13,6 +13,7 @@ Required properties:
"atmel,at91sam9n12-matrix", "syscon"
"atmel,at91sam9x5-matrix", "syscon"
"atmel,sama5d3-matrix", "syscon"
"microchip,sam9x60-matrix", "syscon"
- reg: Contains offset/length value of the Bus Matrix
memory region.

1
Documentation/devicetree/bindings/mfd/atmel-smc.txt
View File

@ -9,6 +9,7 @@ Required properties:
"atmel,at91sam9260-smc", "syscon"
"atmel,sama5d3-smc", "syscon"
"atmel,sama5d2-smc", "syscon"
"microchip,sam9x60-smc", "syscon"
- reg: Contains offset/length value of the SMC memory
region.

1
Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt
View File

@ -18,6 +18,7 @@ Required properties:
Optional properties:
===================
- reg: A hint for the memory regions associated with the P2A controller
- memory-region: A phandle to a reserved_memory region to be used for the PCI
to AHB mapping

1
Documentation/devicetree/bindings/mtd/atmel-nand.txt
View File

@ -57,6 +57,7 @@ Required properties:
"atmel,at91sam9g45-pmecc"
"atmel,sama5d4-pmecc"
"atmel,sama5d2-pmecc"
"microchip,sam9x60-pmecc"
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
block, and the second one to the PMECC_ERRLOC block.

3
Documentation/devicetree/bindings/net/can/atmel-can.txt
View File

@ -1,7 +1,8 @@
* AT91 CAN *
Required properties:
- compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can"
- compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
"microchip,sam9x60-can"
- reg: Should contain CAN controller registers location and length
- interrupts: Should contain IRQ line for the CAN controller

5
Documentation/devicetree/bindings/net/can/rcar_can.txt
View File

@ -7,6 +7,7 @@ Required properties:
"renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
"renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC.
"renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
"renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC.
"renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
"renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
"renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
@ -36,8 +37,8 @@ Required properties:
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must be "default".
Required properties for R8A774A1, R8A774C0, R8A7795, R8A7796, R8A77965,
R8A77990, and R8A77995:
Required properties for R8A774A1, R8A774B1, R8A774C0, R8A7795, R8A7796,
R8A77965, R8A77990, and R8A77995:
For the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can
be used by both CAN and CAN FD controller at the same time. It needs to be
scaled to maximum frequency if any of these controllers use it. This is done

5
Documentation/devicetree/bindings/net/can/rcar_canfd.txt
View File

@ -5,6 +5,7 @@ Required properties:
- compatible: Must contain one or more of the following:
- "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
- "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller.
- "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller.
- "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
- "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
- "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
@ -31,8 +32,8 @@ The name of the child nodes are "channel0" and "channel1" respectively. Each
child node supports the "status" property only, which is used to
enable/disable the respective channel.
Required properties for R8A774A1, R8A774C0, R8A7795, R8A7796, R8A77965,
R8A77990, and R8A77995:
Required properties for R8A774A1, R8A774B1, R8A774C0, R8A7795, R8A7796,
R8A77965, R8A77990, and R8A77995:
In the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN
and CAN FD controller at the same time. It needs to be scaled to maximum
frequency if any of these controllers use it. This is done using the below

42
Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml Normal file
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@ -0,0 +1,42 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright 2019 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Marvell MMP3 HSIC PHY
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
properties:
compatible:
const: marvell,mmp3-hsic-phy
reg:
maxItems: 1
description: base address of the device
reset-gpios:
maxItems: 1
description: GPIO connected to reset
"#phy-cells":
const: 0
required:
- compatible
- reg
- reset-gpios
- "#phy-cells"
examples:
- |
#include <dt-bindings/gpio/gpio.h>
hsic-phy@f0001800 {
compatible = "marvell,mmp3-hsic-phy";
reg = <0xf0001800 0x40>;
reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
#phy-cells = <0>;
};

3
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
View File

@ -22,6 +22,9 @@ description: |+
properties:
compatible:
const: aspeed,ast2400-pinctrl
reg:
description: |
A hint for the memory regions associated with the pin-controller
patternProperties:
'^.*$':

3
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View File

@ -23,6 +23,9 @@ description: |+
properties:
compatible:
const: aspeed,ast2500-pinctrl
reg:
description: |
A hint for the memory regions associated with the pin-controller
aspeed,external-nodes:
minItems: 2
maxItems: 2

148
Documentation/devicetree/bindings/power/qcom,rpmpd.txt
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@ -1,148 +0,0 @@
Qualcomm RPM/RPMh Power domains
For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh
which then translates it into a corresponding voltage on a rail
Required Properties:
- compatible: Should be one of the following
* qcom,msm8976-rpmpd: RPM Power domain for the msm8976 family of SoC
* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC
* qcom,msm8998-rpmpd: RPM Power domain for the msm8998 family of SoC
* qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC
* qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC
- #power-domain-cells: number of cells in Power domain specifier
must be 1.
- operating-points-v2: Phandle to the OPP table for the Power domain.
Refer to Documentation/devicetree/bindings/power/power_domain.txt
and Documentation/devicetree/bindings/opp/opp.txt for more details
Refer to <dt-bindings/power/qcom-rpmpd.h> for the level values for
various OPPs for different platforms as well as Power domain indexes
Example: rpmh power domain controller and OPP table
#include <dt-bindings/power/qcom-rpmhpd.h>
opp-level values specified in the OPP tables for RPMh power domains
should use the RPMH_REGULATOR_LEVEL_* constants from
<dt-bindings/power/qcom-rpmhpd.h>
rpmhpd: power-controller {
compatible = "qcom,sdm845-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_nom: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
Example: rpm power domain controller and OPP table
rpmpd: power-controller {
compatible = "qcom,msm8996-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_low: opp1 {
opp-level = <1>;
};
rpmpd_opp_ret: opp2 {
opp-level = <2>;
};
rpmpd_opp_svs: opp3 {
opp-level = <3>;
};
rpmpd_opp_normal: opp4 {
opp-level = <4>;
};
rpmpd_opp_high: opp5 {
opp-level = <5>;
};
rpmpd_opp_turbo: opp6 {
opp-level = <6>;
};
};
};
Example: Client/Consumer device using OPP table
leaky-device0@12350000 {
compatible = "foo,i-leak-current";
reg = <0x12350000 0x1000>;
power-domains = <&rpmhpd SDM845_MX>;
operating-points-v2 = <&leaky_opp_table>;
};
leaky_opp_table: opp-table {
compatible = "operating-points-v2";
opp1 {
opp-hz = /bits/ 64 <144000>;
required-opps = <&rpmhpd_opp_low>;
};
opp2 {
opp-hz = /bits/ 64 <400000>;
required-opps = <&rpmhpd_opp_ret>;
};
opp3 {
opp-hz = /bits/ 64 <20000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp4 {
opp-hz = /bits/ 64 <25000000>;
required-opps = <&rpmpd_opp_normal>;
};
};

170
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@ -0,0 +1,170 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/qcom,rpmpd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPM/RPMh Power domains
maintainers:
- Rajendra Nayak <rnayak@codeaurora.org>
description:
For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh
which then translates it into a corresponding voltage on a rail.
properties:
compatible:
enum:
- qcom,msm8976-rpmpd
- qcom,msm8996-rpmpd
- qcom,msm8998-rpmpd
- qcom,qcs404-rpmpd
- qcom,sc7180-rpmhpd
- qcom,sdm845-rpmhpd
- qcom,sm8150-rpmhpd
'#power-domain-cells':
const: 1
operating-points-v2: true
opp-table:
type: object
required:
- compatible
- '#power-domain-cells'
- operating-points-v2
additionalProperties: false
examples:
- |
// Example 1 (rpmh power domain controller and OPP table):
#include <dt-bindings/power/qcom-rpmpd.h>
rpmhpd: power-controller {
compatible = "qcom,sdm845-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_nom: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
- |
// Example 2 (rpm power domain controller and OPP table):
rpmpd: power-controller {
compatible = "qcom,msm8996-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_low: opp1 {
opp-level = <1>;
};
rpmpd_opp_ret: opp2 {
opp-level = <2>;
};
rpmpd_opp_svs: opp3 {
opp-level = <3>;
};
rpmpd_opp_normal: opp4 {
opp-level = <4>;
};
rpmpd_opp_high: opp5 {
opp-level = <5>;
};
rpmpd_opp_turbo: opp6 {
opp-level = <6>;
};
};
};
- |
// Example 3 (Client/Consumer device using OPP table):
leaky-device0@12350000 {
compatible = "foo,i-leak-current";
reg = <0x12350000 0x1000>;
power-domains = <&rpmhpd 0>;
operating-points-v2 = <&leaky_opp_table>;
};
leaky_opp_table: opp-table {
compatible = "operating-points-v2";
opp1 {
opp-hz = /bits/ 64 <144000>;
required-opps = <&rpmhpd_opp_low>;
};
opp2 {
opp-hz = /bits/ 64 <400000>;
required-opps = <&rpmhpd_opp_ret>;
};
opp3 {
opp-hz = /bits/ 64 <20000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp4 {
opp-hz = /bits/ 64 <25000000>;
required-opps = <&rpmpd_opp_normal>;
};
};
...

42
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
View File

@ -8,9 +8,27 @@ Required properties:
- compatible: Must contain: "xlnx,zynqmp-power"
- interrupts: Interrupt specifier
-------
Example
-------
Optional properties:
- mbox-names : Name given to channels seen in the 'mboxes' property.
"tx" - Mailbox corresponding to transmit path
"rx" - Mailbox corresponding to receive path
- mboxes : Standard property to specify a Mailbox. Each value of
the mboxes property should contain a phandle to the
mailbox controller device node and an args specifier
that will be the phandle to the intended sub-mailbox
child node to be used for communication. See
Documentation/devicetree/bindings/mailbox/mailbox.txt
for more details about the generic mailbox controller
and client driver bindings. Also see
Documentation/devicetree/bindings/mailbox/ \
xlnx,zynqmp-ipi-mailbox.txt for typical controller that
is used to communicate with this System controllers.
--------
Examples
--------
Example with interrupt method:
firmware {
zynqmp_firmware: zynqmp-firmware {
@ -23,3 +41,21 @@ firmware {
};
};
};
Example with IPI mailbox method:
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
zynqmp_power: zynqmp-power {
compatible = "xlnx,zynqmp-power";
interrupt-parent = <&gic>;
interrupts = <0 35 4>;
mboxes = <&ipi_mailbox_pmu0 0>,
<&ipi_mailbox_pmu0 1>;
mbox-names = "tx", "rx";
};
};
};

51
Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
View File

@ -30,13 +30,51 @@ properties:
- items:
- const: allwinner,sun50i-h5-pwm
- const: allwinner,sun5i-a13-pwm
- const: allwinner,sun50i-h6-pwm
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
items:
- description: Module Clock
- description: Bus Clock
# Even though it only applies to subschemas under the conditionals,
# not listing them here will trigger a warning because of the
# additionalsProperties set to false.
clock-names: true
resets:
maxItems: 1
if:
properties:
compatible:
contains:
const: allwinner,sun50i-h6-pwm
then:
properties:
clocks:
maxItems: 2
clock-names:
items:
- const: mod
- const: bus
required:
- clock-names
- resets
else:
properties:
clocks:
maxItems: 1
required:
- "#pwm-cells"
- compatible
@ -54,4 +92,17 @@ examples:
#pwm-cells = <3>;
};
- |
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
pwm@300a000 {
compatible = "allwinner,sun50i-h6-pwm";
reg = <0x0300a000 0x400>;
clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
clock-names = "mod", "bus";
resets = <&ccu RST_BUS_PWM>;
#pwm-cells = <3>;
};
...

37
Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml Normal file
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@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 Broadcom
%YAML 1.2
---
$id: "http://devicetree.org/schemas/reset/brcm,bcm7216-pcie-sata-rescal.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: BCM7216 RESCAL reset controller
description: This document describes the BCM7216 RESCAL reset controller which is responsible for controlling the reset of the SATA and PCIe0/1 instances on BCM7216.
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
- Jim Quinlan <jim2101024@gmail.com>
properties:
compatible:
const: brcm,bcm7216-pcie-sata-rescal
reg:
maxItems: 1
"#reset-cells":
const: 0
required:
- compatible
- reg
- "#reset-cells"
examples:
- |
reset-controller@8b2c800 {
compatible = "brcm,bcm7216-pcie-sata-rescal";
reg = <0x8b2c800 0x10>;
#reset-cells = <0>;
};

63
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@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: System Reset Controller on Intel Gateway SoCs
maintainers:
- Dilip Kota <eswara.kota@linux.intel.com>
properties:
compatible:
enum:
- intel,rcu-lgm
- intel,rcu-xrx200
reg:
description: Reset controller registers.
maxItems: 1
intel,global-reset:
description: Global reset register offset and bit offset.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- maxItems: 2
"#reset-cells":
minimum: 2
maximum: 3
description: |
First cell is reset request register offset.
Second cell is bit offset in reset request register.
Third cell is bit offset in reset status register.
For LGM SoC, reset cell count is 2 as bit offset in
reset request and reset status registers is same. Whereas
3 for legacy SoCs as bit offset differs.
required:
- compatible
- reg
- intel,global-reset
- "#reset-cells"
additionalProperties: false
examples:
- |
rcu0: reset-controller@e0000000 {
compatible = "intel,rcu-lgm";
reg = <0xe0000000 0x20000>;
intel,global-reset = <0x10 30>;
#reset-cells = <2>;
};
pwm: pwm@e0d00000 {
status = "disabled";
compatible = "intel,lgm-pwm";
reg = <0xe0d00000 0x30>;
clocks = <&cgu0 1>;
#pwm-cells = <2>;
resets = <&rcu0 0x30 21>;
};

32
Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt Normal file
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@ -0,0 +1,32 @@
Nuvoton NPCM Reset controller
Required properties:
- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
- reg : specifies physical base address and size of the register.
- #reset-cells: must be set to 2
Optional property:
- nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
NPCM7xx contain four software reset that represent numbers 1 to 4.
If 'nuvoton,sw-reset-number' is not specfied software reset is disabled.
Example:
rstc: rstc@f0801000 {
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
#reset-cells = <2>;
nuvoton,sw-reset-number = <2>;
};
Specifying reset lines connected to IP NPCM7XX modules
======================================================
example:
spi0: spi@..... {
...
resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
...
};
The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.

6
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
View File

@ -11,6 +11,7 @@ The driver implements the Generic PM domain bindings described in
power/power-domain.yaml. It provides the power domains defined in
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt6765-power.h
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
@ -19,6 +20,7 @@ Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
- "mediatek,mt2712-scpsys"
- "mediatek,mt6765-scpsys"
- "mediatek,mt6797-scpsys"
- "mediatek,mt7622-scpsys"
- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
@ -33,6 +35,10 @@ Required properties:
enabled before enabling certain power domains.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6765: MUX: "mm", "mfg"
CG: "mm-0", "mm-1", "mm-2", "mm-3", "isp-0",
"isp-1", "cam-0", "cam-1", "cam-2",
"cam-3","cam-4"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"

1
Documentation/devicetree/bindings/timer/renesas,tmu.txt
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@ -11,6 +11,7 @@ Required Properties:
- compatible: must contain one or more of the following:
- "renesas,tmu-r8a7740" for the r8a7740 TMU
- "renesas,tmu-r8a774a1" for the r8a774A1 TMU
- "renesas,tmu-r8a774b1" for the r8a774B1 TMU
- "renesas,tmu-r8a774c0" for the r8a774C0 TMU
- "renesas,tmu-r8a7778" for the r8a7778 TMU
- "renesas,tmu-r8a7779" for the r8a7779 TMU

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -1034,6 +1034,8 @@ patternProperties:
description: Variscite Ltd.
"^via,.*":
description: VIA Technologies, Inc.
"^videostrong,.*":
description: Videostrong Technology Co., Ltd.
"^virtio,.*":
description: Virtual I/O Device Specification, developed by the OASIS consortium
"^vishay,.*":

404
Documentation/filesystems/zonefs.txt Normal file
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@ -0,0 +1,404 @@
ZoneFS - Zone filesystem for Zoned block devices
Introduction
============
zonefs is a very simple file system exposing each zone of a zoned block device
as a file. Unlike a regular POSIX-compliant file system with native zoned block
device support (e.g. f2fs), zonefs does not hide the sequential write
constraint of zoned block devices to the user. Files representing sequential
write zones of the device must be written sequentially starting from the end
of the file (append only writes).
As such, zonefs is in essence closer to a raw block device access interface
than to a full-featured POSIX file system. The goal of zonefs is to simplify
the implementation of zoned block device support in applications by replacing
raw block device file accesses with a richer file API, avoiding relying on
direct block device file ioctls which may be more obscure to developers. One
example of this approach is the implementation of LSM (log-structured merge)
tree structures (such as used in RocksDB and LevelDB) on zoned block devices
by allowing SSTables to be stored in a zone file similarly to a regular file
system rather than as a range of sectors of the entire disk. The introduction
of the higher level construct "one file is one zone" can help reducing the
amount of changes needed in the application as well as introducing support for
different application programming languages.
Zoned block devices
-------------------
Zoned storage devices belong to a class of storage devices with an address
space that is divided into zones. A zone is a group of consecutive LBAs and all
zones are contiguous (there are no LBA gaps). Zones may have different types.
* Conventional zones: there are no access constraints to LBAs belonging to
conventional zones. Any read or write access can be executed, similarly to a
regular block device.
* Sequential zones: these zones accept random reads but must be written
sequentially. Each sequential zone has a write pointer maintained by the
device that keeps track of the mandatory start LBA position of the next write
to the device. As a result of this write constraint, LBAs in a sequential zone
cannot be overwritten. Sequential zones must first be erased using a special
command (zone reset) before rewriting.
Zoned storage devices can be implemented using various recording and media
technologies. The most common form of zoned storage today uses the SCSI Zoned
Block Commands (ZBC) and Zoned ATA Commands (ZAC) interfaces on Shingled
Magnetic Recording (SMR) HDDs.
Solid State Disks (SSD) storage devices can also implement a zoned interface
to, for instance, reduce internal write amplification due to garbage collection.
The NVMe Zoned NameSpace (ZNS) is a technical proposal of the NVMe standard
committee aiming at adding a zoned storage interface to the NVMe protocol.
Zonefs Overview
===============
Zonefs exposes the zones of a zoned block device as files. The files
representing zones are grouped by zone type, which are themselves represented
by sub-directories. This file structure is built entirely using zone information
provided by the device and so does not require any complex on-disk metadata
structure.
On-disk metadata
----------------
zonefs on-disk metadata is reduced to an immutable super block which
persistently stores a magic number and optional feature flags and values. On
mount, zonefs uses blkdev_report_zones() to obtain the device zone configuration
and populates the mount point with a static file tree solely based on this
information. File sizes come from the device zone type and write pointer
position managed by the device itself.
The super block is always written on disk at sector 0. The first zone of the
device storing the super block is never exposed as a zone file by zonefs. If
the zone containing the super block is a sequential zone, the mkzonefs format
tool always "finishes" the zone, that is, it transitions the zone to a full
state to make it read-only, preventing any data write.
Zone type sub-directories
-------------------------
Files representing zones of the same type are grouped together under the same
sub-directory automatically created on mount.
For conventional zones, the sub-directory "cnv" is used. This directory is
however created if and only if the device has usable conventional zones. If
the device only has a single conventional zone at sector 0, the zone will not
be exposed as a file as it will be used to store the zonefs super block. For
such devices, the "cnv" sub-directory will not be created.
For sequential write zones, the sub-directory "seq" is used.
These two directories are the only directories that exist in zonefs. Users
cannot create other directories and cannot rename nor delete the "cnv" and
"seq" sub-directories.
The size of the directories indicated by the st_size field of struct stat,
obtained with the stat() or fstat() system calls, indicates the number of files
existing under the directory.
Zone files
----------
Zone files are named using the number of the zone they represent within the set
of zones of a particular type. That is, both the "cnv" and "seq" directories
contain files named "0", "1", "2", ... The file numbers also represent
increasing zone start sector on the device.
All read and write operations to zone files are not allowed beyond the file
maximum size, that is, beyond the zone size. Any access exceeding the zone
size is failed with the -EFBIG error.
Creating, deleting, renaming or modifying any attribute of files and
sub-directories is not allowed.
The number of blocks of a file as reported by stat() and fstat() indicates the
size of the file zone, or in other words, the maximum file size.
Conventional zone files
-----------------------
The size of conventional zone files is fixed to the size of the zone they
represent. Conventional zone files cannot be truncated.
These files can be randomly read and written using any type of I/O operation:
buffered I/Os, direct I/Os, memory mapped I/Os (mmap), etc. There are no I/O
constraint for these files beyond the file size limit mentioned above.
Sequential zone files
---------------------
The size of sequential zone files grouped in the "seq" sub-directory represents
the file's zone write pointer position relative to the zone start sector.
Sequential zone files can only be written sequentially, starting from the file
end, that is, write operations can only be append writes. Zonefs makes no
attempt at accepting random writes and will fail any write request that has a
start offset not corresponding to the end of the file, or to the end of the last
write issued and still in-flight (for asynchrnous I/O operations).
Since dirty page writeback by the page cache does not guarantee a sequential
write pattern, zonefs prevents buffered writes and writeable shared mappings
on sequential files. Only direct I/O writes are accepted for these files.
zonefs relies on the sequential delivery of write I/O requests to the device
implemented by the block layer elevator. An elevator implementing the sequential
write feature for zoned block device (ELEVATOR_F_ZBD_SEQ_WRITE elevator feature)
must be used. This type of elevator (e.g. mq-deadline) is the set by default
for zoned block devices on device initialization.
There are no restrictions on the type of I/O used for read operations in
sequential zone files. Buffered I/Os, direct I/Os and shared read mappings are
all accepted.
Truncating sequential zone files is allowed only down to 0, in which case, the
zone is reset to rewind the file zone write pointer position to the start of
the zone, or up to the zone size, in which case the file's zone is transitioned
to the FULL state (finish zone operation).
Format options
--------------
Several optional features of zonefs can be enabled at format time.
* Conventional zone aggregation: ranges of contiguous conventional zones can be
aggregated into a single larger file instead of the default one file per zone.
* File ownership: The owner UID and GID of zone files is by default 0 (root)
but can be changed to any valid UID/GID.
* File access permissions: the default 640 access permissions can be changed.
IO error handling
-----------------
Zoned block devices may fail I/O requests for reasons similar to regular block
devices, e.g. due to bad sectors. However, in addition to such known I/O
failure pattern, the standards governing zoned block devices behavior define
additional conditions that result in I/O errors.
* A zone may transition to the read-only condition (BLK_ZONE_COND_READONLY):
While the data already written in the zone is still readable, the zone can
no longer be written. No user action on the zone (zone management command or
read/write access) can change the zone condition back to a normal read/write
state. While the reasons for the device to transition a zone to read-only
state are not defined by the standards, a typical cause for such transition
would be a defective write head on an HDD (all zones under this head are
changed to read-only).
* A zone may transition to the offline condition (BLK_ZONE_COND_OFFLINE):
An offline zone cannot be read nor written. No user action can transition an
offline zone back to an operational good state. Similarly to zone read-only
transitions, the reasons for a drive to transition a zone to the offline
condition are undefined. A typical cause would be a defective read-write head
on an HDD causing all zones on the platter under the broken head to be
inaccessible.
* Unaligned write errors: These errors result from the host issuing write
requests with a start sector that does not correspond to a zone write pointer
position when the write request is executed by the device. Even though zonefs
enforces sequential file write for sequential zones, unaligned write errors
may still happen in the case of a partial failure of a very large direct I/O
operation split into multiple BIOs/requests or asynchronous I/O operations.
If one of the write request within the set of sequential write requests
issued to the device fails, all write requests after queued after it will
become unaligned and fail.
* Delayed write errors: similarly to regular block devices, if the device side
write cache is enabled, write errors may occur in ranges of previously
completed writes when the device write cache is flushed, e.g. on fsync().
Similarly to the previous immediate unaligned write error case, delayed write
errors can propagate through a stream of cached sequential data for a zone
causing all data to be dropped after the sector that caused the error.
All I/O errors detected by zonefs are notified to the user with an error code
return for the system call that trigered or detected the error. The recovery
actions taken by zonefs in response to I/O errors depend on the I/O type (read
vs write) and on the reason for the error (bad sector, unaligned writes or zone
condition change).
* For read I/O errors, zonefs does not execute any particular recovery action,
but only if the file zone is still in a good condition and there is no
inconsistency between the file inode size and its zone write pointer position.
If a problem is detected, I/O error recovery is executed (see below table).
* For write I/O errors, zonefs I/O error recovery is always executed.
* A zone condition change to read-only or offline also always triggers zonefs
I/O error recovery.
Zonefs minimal I/O error recovery may change a file size and a file access
permissions.
* File size changes:
Immediate or delayed write errors in a sequential zone file may cause the file
inode size to be inconsistent with the amount of data successfully written in
the file zone. For instance, the partial failure of a multi-BIO large write
operation will cause the zone write pointer to advance partially, even though
the entire write operation will be reported as failed to the user. In such
case, the file inode size must be advanced to reflect the zone write pointer
change and eventually allow the user to restart writing at the end of the
file.
A file size may also be reduced to reflect a delayed write error detected on
fsync(): in this case, the amount of data effectively written in the zone may
be less than originally indicated by the file inode size. After such I/O
error, zonefs always fixes a file inode size to reflect the amount of data
persistently stored in the file zone.
* Access permission changes:
A zone condition change to read-only is indicated with a change in the file
access permissions to render the file read-only. This disables changes to the
file attributes and data modification. For offline zones, all permissions
(read and write) to the file are disabled.
Further action taken by zonefs I/O error recovery can be controlled by the user
with the "errors=xxx" mount option. The table below summarizes the result of
zonefs I/O error processing depending on the mount option and on the zone
conditions.
+--------------+-----------+-----------------------------------------+
| | | Post error state |
| "errors=xxx" | device | access permissions |
| mount | zone | file file device zone |
| option | condition | size read write read write |
+--------------+-----------+-----------------------------------------+
| | good | fixed yes no yes yes |
| remount-ro | read-only | fixed yes no yes no |
| (default) | offline | 0 no no no no |
+--------------+-----------+-----------------------------------------+
| | good | fixed yes no yes yes |
| zone-ro | read-only | fixed yes no yes no |
| | offline | 0 no no no no |
+--------------+-----------+-----------------------------------------+
| | good | 0 no no yes yes |
| zone-offline | read-only | 0 no no yes no |
| | offline | 0 no no no no |
+--------------+-----------+-----------------------------------------+
| | good | fixed yes yes yes yes |
| repair | read-only | fixed yes no yes no |
| | offline | 0 no no no no |
+--------------+-----------+-----------------------------------------+
Further notes:
* The "errors=remount-ro" mount option is the default behavior of zonefs I/O
error processing if no errors mount option is specified.
* With the "errors=remount-ro" mount option, the change of the file access
permissions to read-only applies to all files. The file system is remounted
read-only.
* Access permission and file size changes due to the device transitioning zones
to the offline condition are permanent. Remounting or reformating the device
with mkfs.zonefs (mkzonefs) will not change back offline zone files to a good
state.
* File access permission changes to read-only due to the device transitioning
zones to the read-only condition are permanent. Remounting or reformating
the device will not re-enable file write access.
* File access permission changes implied by the remount-ro, zone-ro and
zone-offline mount options are temporary for zones in a good condition.
Unmounting and remounting the file system will restore the previous default
(format time values) access rights to the files affected.
* The repair mount option triggers only the minimal set of I/O error recovery
actions, that is, file size fixes for zones in a good condition. Zones
indicated as being read-only or offline by the device still imply changes to
the zone file access permissions as noted in the table above.
Mount options
-------------
zonefs define the "errors=<behavior>" mount option to allow the user to specify
zonefs behavior in response to I/O errors, inode size inconsistencies or zone
condition chages. The defined behaviors are as follow:
* remount-ro (default)
* zone-ro
* zone-offline
* repair
The I/O error actions defined for each behavior is detailed in the previous
section.
Zonefs User Space Tools
=======================
The mkzonefs tool is used to format zoned block devices for use with zonefs.
This tool is available on Github at:
https://github.com/damien-lemoal/zonefs-tools
zonefs-tools also includes a test suite which can be run against any zoned
block device, including null_blk block device created with zoned mode.
Examples
--------
The following formats a 15TB host-managed SMR HDD with 256 MB zones
with the conventional zones aggregation feature enabled.
# mkzonefs -o aggr_cnv /dev/sdX
# mount -t zonefs /dev/sdX /mnt
# ls -l /mnt/
total 0
dr-xr-xr-x 2 root root 1 Nov 25 13:23 cnv
dr-xr-xr-x 2 root root 55356 Nov 25 13:23 seq
The size of the zone files sub-directories indicate the number of files
existing for each type of zones. In this example, there is only one
conventional zone file (all conventional zones are aggregated under a single
file).
# ls -l /mnt/cnv
total 137101312
-rw-r----- 1 root root 140391743488 Nov 25 13:23 0
This aggregated conventional zone file can be used as a regular file.
# mkfs.ext4 /mnt/cnv/0
# mount -o loop /mnt/cnv/0 /data
The "seq" sub-directory grouping files for sequential write zones has in this
example 55356 zones.
# ls -lv /mnt/seq
total 14511243264
-rw-r----- 1 root root 0 Nov 25 13:23 0
-rw-r----- 1 root root 0 Nov 25 13:23 1
-rw-r----- 1 root root 0 Nov 25 13:23 2
...
-rw-r----- 1 root root 0 Nov 25 13:23 55354
-rw-r----- 1 root root 0 Nov 25 13:23 55355
For sequential write zone files, the file size changes as data is appended at
the end of the file, similarly to any regular file system.
# dd if=/dev/zero of=/mnt/seq/0 bs=4096 count=1 conv=notrunc oflag=direct
1+0 records in
1+0 records out
4096 bytes (4.1 kB, 4.0 KiB) copied, 0.00044121 s, 9.3 MB/s
# ls -l /mnt/seq/0
-rw-r----- 1 root root 4096 Nov 25 13:23 /mnt/seq/0
The written file can be truncated to the zone size, preventing any further
write operation.
# truncate -s 268435456 /mnt/seq/0
# ls -l /mnt/seq/0
-rw-r----- 1 root root 268435456 Nov 25 13:49 /mnt/seq/0
Truncation to 0 size allows freeing the file zone storage space and restart
append-writes to the file.
# truncate -s 0 /mnt/seq/0
# ls -l /mnt/seq/0
-rw-r----- 1 root root 0 Nov 25 13:49 /mnt/seq/0
Since files are statically mapped to zones on the disk, the number of blocks of
a file as reported by stat() and fstat() indicates the size of the file zone.
# stat /mnt/seq/0
File: /mnt/seq/0
Size: 0 Blocks: 524288 IO Block: 4096 regular empty file
Device: 870h/2160d Inode: 50431 Links: 1
Access: (0640/-rw-r-----) Uid: ( 0/ root) Gid: ( 0/ root)
Access: 2019-11-25 13:23:57.048971997 +0900
Modify: 2019-11-25 13:52:25.553805765 +0900
Change: 2019-11-25 13:52:25.553805765 +0900
Birth: -
The number of blocks of the file ("Blocks") in units of 512B blocks gives the
maximum file size of 524288 * 512 B = 256 MB, corresponding to the device zone
size in this example. Of note is that the "IO block" field always indicates the
minimum I/O size for writes and corresponds to the device physical sector size.

53
Documentation/kbuild/makefiles.rst
View File

@ -28,7 +28,6 @@ This document describes the Linux kernel Makefiles.
--- 4.3 Using C++ for host programs
--- 4.4 Controlling compiler options for host programs
--- 4.5 When host programs are actually built
--- 4.6 Using hostprogs-$(CONFIG_FOO)
=== 5 Kbuild clean infrastructure
@ -595,11 +594,11 @@ compilation stage.
Two steps are required in order to use a host executable.
The first step is to tell kbuild that a host program exists. This is
done utilising the variable hostprogs-y.
done utilising the variable "hostprogs".
The second step is to add an explicit dependency to the executable.
This can be done in two ways. Either add the dependency in a rule,
or utilise the variable $(always).
or utilise the variable "always-y".
Both possibilities are described in the following.
4.1 Simple Host Program
@ -612,7 +611,7 @@ Both possibilities are described in the following.
Example::
hostprogs-y := bin2hex
hostprogs := bin2hex
Kbuild assumes in the above example that bin2hex is made from a single
c-source file named bin2hex.c located in the same directory as
@ -630,7 +629,7 @@ Both possibilities are described in the following.
Example::
#scripts/lxdialog/Makefile
hostprogs-y := lxdialog
hostprogs := lxdialog
lxdialog-objs := checklist.o lxdialog.o
Objects with extension .o are compiled from the corresponding .c
@ -650,7 +649,7 @@ Both possibilities are described in the following.
Example::
#scripts/kconfig/Makefile
hostprogs-y := qconf
hostprogs := qconf
qconf-cxxobjs := qconf.o
In the example above the executable is composed of the C++ file
@ -662,7 +661,7 @@ Both possibilities are described in the following.
Example::
#scripts/kconfig/Makefile
hostprogs-y := qconf
hostprogs := qconf
qconf-cxxobjs := qconf.o
qconf-objs := check.o
@ -710,7 +709,7 @@ Both possibilities are described in the following.
Example::
#drivers/pci/Makefile
hostprogs-y := gen-devlist
hostprogs := gen-devlist
$(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
( cd $(obj); ./gen-devlist ) < $<
@ -718,47 +717,31 @@ Both possibilities are described in the following.
$(obj)/gen-devlist is updated. Note that references to
the host programs in special rules must be prefixed with $(obj).
(2) Use $(always)
(2) Use always-y
When there is no suitable special rule, and the host program
shall be built when a makefile is entered, the $(always)
shall be built when a makefile is entered, the always-y
variable shall be used.
Example::
#scripts/lxdialog/Makefile
hostprogs-y := lxdialog
always := $(hostprogs-y)
hostprogs := lxdialog
always-y := $(hostprogs)
This will tell kbuild to build lxdialog even if not referenced in
any rule.
4.6 Using hostprogs-$(CONFIG_FOO)
---------------------------------
A typical pattern in a Kbuild file looks like this:
Example::
#scripts/Makefile
hostprogs-$(CONFIG_KALLSYMS) += kallsyms
Kbuild knows about both 'y' for built-in and 'm' for module.
So if a config symbol evaluates to 'm', kbuild will still build
the binary. In other words, Kbuild handles hostprogs-m exactly
like hostprogs-y. But only hostprogs-y is recommended to be used
when no CONFIG symbols are involved.
5 Kbuild clean infrastructure
=============================
"make clean" deletes most generated files in the obj tree where the kernel
is compiled. This includes generated files such as host programs.
Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
$(extra-y) and $(targets). They are all deleted during "make clean".
Files matching the patterns "*.[oas]", "*.ko", plus some additional files
generated by kbuild are deleted all over the kernel src tree when
"make clean" is executed.
Kbuild knows targets listed in $(hostprogs), $(always-y), $(always-m),
$(always-), $(extra-y), $(extra-) and $(targets). They are all deleted
during "make clean". Files matching the patterns "*.[oas]", "*.ko", plus
some additional files generated by kbuild are deleted all over the kernel
source tree when "make clean" is executed.
Additional files or directories can be specified in kbuild makefiles by use of
$(clean-files).
@ -1269,12 +1252,12 @@ When kbuild executes, the following steps are followed (roughly):
Example::
#arch/x86/kernel/Makefile
always := vmlinux.lds
extra-y := vmlinux.lds
#Makefile
export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
The assignment to $(always) is used to tell kbuild to build the
The assignment to extra-y is used to tell kbuild to build the
target vmlinux.lds.
The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
specified options when building the target vmlinux.lds.

8
Kbuild
View File

@ -7,7 +7,7 @@
bounds-file := include/generated/bounds.h
always := $(bounds-file)
always-y := $(bounds-file)
targets := kernel/bounds.s
$(bounds-file): kernel/bounds.s FORCE
@ -28,7 +28,7 @@ $(timeconst-file): kernel/time/timeconst.bc FORCE
offsets-file := include/generated/asm-offsets.h
always += $(offsets-file)
always-y += $(offsets-file)
targets += arch/$(SRCARCH)/kernel/asm-offsets.s
arch/$(SRCARCH)/kernel/asm-offsets.s: $(timeconst-file) $(bounds-file)
@ -39,7 +39,7 @@ $(offsets-file): arch/$(SRCARCH)/kernel/asm-offsets.s FORCE
#####
# Check for missing system calls
always += missing-syscalls
always-y += missing-syscalls
quiet_cmd_syscalls = CALL $<
cmd_syscalls = $(CONFIG_SHELL) $< $(CC) $(c_flags) $(missing_syscalls_flags)
@ -50,7 +50,7 @@ missing-syscalls: scripts/checksyscalls.sh $(offsets-file) FORCE
#####
# Check atomic headers are up-to-date
always += old-atomics
always-y += old-atomics
quiet_cmd_atomics = CALL $<
cmd_atomics = $(CONFIG_SHELL) $<

25
MAINTAINERS
View File

@ -2092,6 +2092,7 @@ F: drivers/rtc/rtc-pl031.c
F: drivers/watchdog/coh901327_wdt.c
F: Documentation/devicetree/bindings/arm/ste-*
F: Documentation/devicetree/bindings/arm/ux500/
F: Documentation/devicetree/bindings/arm/ux500.yaml
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
ARM/NUVOTON NPCM ARCHITECTURE
@ -3288,6 +3289,8 @@ S: Maintained
N: bcm2711
N: bcm2835
F: drivers/staging/vc04_services
F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
F: drivers/pci/controller/pcie-brcmstb.c
BROADCOM BCM47XX MIPS ARCHITECTURE
M: Hauke Mehrtens <hauke@hauke-m.de>
@ -3343,6 +3346,8 @@ F: drivers/bus/brcmstb_gisb.c
F: arch/arm/mm/cache-b15-rac.c
F: arch/arm/include/asm/hardware/cache-b15-rac.h
N: brcmstb
F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
F: drivers/pci/controller/pcie-brcmstb.c
BROADCOM BMIPS CPUFREQ DRIVER
M: Markus Mayer <mmayer@broadcom.com>
@ -13355,7 +13360,7 @@ S: Maintained
F: fs/timerfd.c
F: include/linux/timer*
F: include/linux/time_namespace.h
F: kernel/time_namespace.c
F: kernel/time/namespace.c
F: kernel/time/*timer*
POWER MANAGEMENT CORE
@ -16147,6 +16152,7 @@ F: drivers/firmware/arm_scpi.c
F: drivers/firmware/arm_scmi/
F: drivers/reset/reset-scmi.c
F: include/linux/sc[mp]i_protocol.h
F: include/trace/events/scmi.h
SYSTEM RESET/SHUTDOWN DRIVERS
M: Sebastian Reichel <sre@kernel.org>
@ -17132,7 +17138,6 @@ F: drivers/staging/unisys/
UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER
R: Alim Akhtar <alim.akhtar@samsung.com>
R: Avri Altman <avri.altman@wdc.com>
R: Pedro Sousa <pedrom.sousa@synopsys.com>
L: linux-scsi@vger.kernel.org
S: Supported
F: Documentation/scsi/ufs.txt
@ -17786,6 +17791,12 @@ F: include/linux/vbox_utils.h
F: include/uapi/linux/vbox*.h
F: drivers/virt/vboxguest/
VIRTUAL BOX SHARED FOLDER VFS DRIVER:
M: Hans de Goede <hdegoede@redhat.com>
L: linux-fsdevel@vger.kernel.org
S: Maintained
F: fs/vboxsf/*
VIRTUAL SERIO DEVICE DRIVER
M: Stephen Chandler Paul <thatslyude@gmail.com>
S: Maintained
@ -18485,6 +18496,16 @@ L: linux-kernel@vger.kernel.org
S: Maintained
F: arch/x86/kernel/cpu/zhaoxin.c
ZONEFS FILESYSTEM
M: Damien Le Moal <damien.lemoal@wdc.com>
M: Naohiro Aota <naohiro.aota@wdc.com>
R: Johannes Thumshirn <jth@kernel.org>
L: linux-fsdevel@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/zonefs.git
S: Maintained
F: fs/zonefs/
F: Documentation/filesystems/zonefs.txt
ZPOOL COMPRESSED PAGE STORAGE API
M: Dan Streetman <ddstreet@ieee.org>
L: linux-mm@kvack.org

6
Makefile
View File

@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 5
PATCHLEVEL = 6
SUBLEVEL = 0
EXTRAVERSION =
EXTRAVERSION = -rc1
NAME = Kleptomaniac Octopus
# *DOCUMENTATION*
@ -1742,7 +1742,7 @@ PHONY += descend $(build-dirs)
descend: $(build-dirs)
$(build-dirs): prepare
$(Q)$(MAKE) $(build)=$@ \
single-build=$(if $(filter-out $@/, $(single-no-ko)),1) \
single-build=$(if $(filter-out $@/, $(filter $@/%, $(single-no-ko))),1) \
need-builtin=1 need-modorder=1
clean-dirs := $(addprefix _clean_, $(clean-dirs))

2
arch/alpha/boot/Makefile
View File

@ -8,7 +8,7 @@
# Copyright (C) 1994 by Linus Torvalds
#
hostprogs-y := tools/mkbb tools/objstrip
hostprogs := tools/mkbb tools/objstrip
targets := vmlinux.gz vmlinux \
vmlinux.nh tools/lxboot tools/bootlx tools/bootph \
tools/bootpzh bootloader bootpheader bootpzheader

6
arch/arm/Kconfig.debug
View File

@ -147,14 +147,14 @@ choice
0x80024000 | 0xf0024000 | UART9
config DEBUG_AT91_RM9200_DBGU
bool "Kernel low-level debugging on AT91RM9200, AT91SAM9 DBGU"
bool "Kernel low-level debugging on AT91RM9200, AT91SAM9, SAM9X60 DBGU"
select DEBUG_AT91_UART
depends on SOC_AT91RM9200 || SOC_AT91SAM9
depends on SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60
help
Say Y here if you want kernel low-level debugging support
on the DBGU port of:
at91rm9200, at91sam9260, at91sam9g20, at91sam9261,
at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5
at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5, sam9x60
config DEBUG_AT91_SAM9263_DBGU
bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU"

26
arch/arm/boot/dts/Makefile
View File

@ -37,18 +37,24 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91-ariag25.dtb \
at91-ariettag25.dtb \
at91-cosino_mega2560.dtb \
at91-kizboxmini.dtb \
at91-kizboxmini-base.dtb \
at91-kizboxmini-mb.dtb \
at91-kizboxmini-rd.dtb \
at91-smartkiz.dtb \
at91-wb45n.dtb \
at91sam9g15ek.dtb \
at91sam9g25ek.dtb \
at91sam9g35ek.dtb \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
dtb-$(CONFIG_SOC_SAM9X60) += \
at91-sam9x60ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2-2.dtb \
at91-kizbox3-hs.dtb \
at91-nattis-2-natte-2.dtb \
at91-sama5d27_som1_ek.dtb \
at91-sama5d27_wlsom1_ek.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
@ -422,6 +428,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw560x.dtb \
imx6dl-gw5903.dtb \
imx6dl-gw5904.dtb \
imx6dl-gw5907.dtb \
imx6dl-gw5910.dtb \
imx6dl-gw5912.dtb \
imx6dl-gw5913.dtb \
imx6dl-hummingboard.dtb \
imx6dl-hummingboard-emmc-som-v15.dtb \
imx6dl-hummingboard-som-v15.dtb \
@ -493,6 +503,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw560x.dtb \
imx6q-gw5903.dtb \
imx6q-gw5904.dtb \
imx6q-gw5907.dtb \
imx6q-gw5910.dtb \
imx6q-gw5912.dtb \
imx6q-gw5913.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-hummingboard-emmc-som-v15.dtb \
@ -554,6 +568,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-tolino-shine3.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk.dtb \
@ -612,6 +627,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7s-mba7.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
@ -691,6 +707,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
omap3-devkit8000.dtb \
omap3-devkit8000-lcd43.dtb \
omap3-devkit8000-lcd70.dtb \
omap3-echo.dtb \
omap3-evm.dtb \
omap3-evm-37xx.dtb \
omap3-gta04a3.dtb \
@ -1129,6 +1146,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
sun8i-h3-rervision-dvk.dtb \
sun8i-h3-emlid-neutis-n5h3-devboard.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-nintendo-super-nes-classic.dtb \
@ -1182,7 +1200,9 @@ dtb-$(CONFIG_ARCH_U8500) += \
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
ste-hrefv60plus-stuib.dtb \
ste-hrefv60plus-tvk.dtb
ste-hrefv60plus-tvk.dtb \
ste-href520-tvk.dtb \
ste-ux500-samsung-golden.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ld4-ref.dtb \
uniphier-ld6b-ref.dtb \
@ -1238,6 +1258,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-clearfog-gtr-s4.dtb \
armada-385-clearfog-gtr-l8.dtb \
armada-385-db-88f6820-amc.dtb \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \

40
arch/arm/boot/dts/am335x-evm.dts
View File

@ -113,7 +113,7 @@ switch10 {
};
};
backlight {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 0>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@ -121,35 +121,15 @@ backlight {
};
panel {
compatible = "ti,tilcdc,panel";
status = "okay";
compatible = "tfc,s9700rtwv43tr-01b";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins_s0>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
backlight = <&backlight>;
display-timings {
800x480p62 {
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <39>;
hback-porch = <39>;
hsync-len = <47>;
vback-porch = <29>;
vfront-porch = <13>;
vsync-len = <2>;
hsync-active = <1>;
vsync-active = <1>;
port {
panel_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
@ -500,6 +480,12 @@ &lcdc {
status = "okay";
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&panel_0>;
};
};
};
&elm {

38
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -183,36 +183,16 @@ sound_master: simple-audio-card,codec {
};
panel {
compatible = "ti,tilcdc,panel";
compatible = "newhaven,nhd-4.3-480272ef-atxl";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
backlight = <&lcd_bl>;
status = "okay";
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
480x272 {
hactive = <480>;
vactive = <272>;
hback-porch = <43>;
hfront-porch = <8>;
hsync-len = <4>;
vback-porch = <12>;
vfront-porch = <4>;
vsync-len = <10>;
clock-frequency = <9000000>;
hsync-active = <0>;
vsync-active = <0>;
port {
panel_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
@ -725,6 +705,12 @@ &lcdc {
status = "okay";
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&panel_0>;
};
};
};
&rtc {

13
arch/arm/boot/dts/am335x-icev2.dts
View File

@ -287,6 +287,19 @@ pca9536: gpio@41 {
gpio-controller;
#gpio-cells = <2>;
};
/* osd9616p0899-10 */
display@3c {
compatible = "solomon,ssd1306fb-i2c";
reg = <0x3c>;
solomon,height = <16>;
solomon,width = <96>;
solomon,com-seq;
solomon,com-invdir;
solomon,page-offset = <0>;
solomon,prechargep1 = <2>;
solomon,prechargep2 = <13>;
};
};
&spi0 {

16
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -225,7 +225,6 @@ i2c0: i2c@0 {
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
@ -1009,7 +1008,6 @@ i2c1: i2c@0 {
target-module@30000 { /* 0x48030000, ap 77 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
@ -1134,7 +1132,6 @@ timer2: timer@0 {
target-module@42000 { /* 0x48042000, ap 24 1c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
@ -1160,7 +1157,6 @@ timer3: timer@0 {
target-module@44000 { /* 0x48044000, ap 26 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
@ -1187,7 +1183,6 @@ timer4: timer@0 {
target-module@46000 { /* 0x48046000, ap 28 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
@ -1214,7 +1209,6 @@ timer5: timer@0 {
target-module@48000 { /* 0x48048000, ap 30 22.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
@ -1241,7 +1235,6 @@ timer6: timer@0 {
target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
@ -1344,7 +1337,6 @@ mmc1: mmc@0 {
target-module@80000 { /* 0x48080000, ap 38 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@ -1412,7 +1404,6 @@ mbox_wkupm3: wkup_m3 {
target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
@ -1533,7 +1524,6 @@ i2c2: i2c@0 {
target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
@ -1749,7 +1739,6 @@ target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
<&dcan0_fck>;
@ -1773,7 +1762,6 @@ target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
<&dcan1_fck>;
@ -1863,7 +1851,6 @@ segment@300000 { /* 0x48300000 */
target-module@0 { /* 0x48300000, ap 66 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
@ -1916,7 +1903,6 @@ ehrpwm0: pwm@200 {
target-module@2000 { /* 0x48302000, ap 68 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
@ -1969,7 +1955,6 @@ ehrpwm1: pwm@200 {
target-module@4000 { /* 0x48304000, ap 70 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@ -2022,7 +2007,6 @@ ehrpwm2: pwm@200 {
target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "lcdc";
reg = <0xe000 0x4>,
<0xe054 0x4>;
reg-names = "rev", "sysc";

94
arch/arm/boot/dts/am33xx.dtsi
View File

@ -439,23 +439,87 @@ gpmc: gpmc@50000000 {
status = "disabled";
};
sham: sham@53100000 {
compatible = "ti,omap4-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x200>;
interrupts = <109>;
dmas = <&edma 36 0>;
dma-names = "rx";
sham_target: target-module@53100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x53100100 0x4>,
<0x53100110 0x4>,
<0x53100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap4-sham";
reg = <0 0x200>;
interrupts = <109>;
dmas = <&edma 36 0>;
dma-names = "rx";
};
};
aes: aes@53500000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x53500000 0xa0>;
interrupts = <103>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
aes_target: target-module@53500000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53500080 0x4>,
<0x53500084 0x4>,
<0x53500088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53500000 0x1000>;
aes: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <103>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
};
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_gfx 0>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x1000000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
};
};

2
arch/arm/boot/dts/am3517.dtsi
View File

@ -74,7 +74,7 @@ davinci_emac: ethernet@5c000000 {
clock-names = "ick";
};
davinci_mdio: ethernet@5c030000 {
davinci_mdio: mdio@5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";

14
arch/arm/boot/dts/am3703.dtsi Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
*/
#include "omap36xx.dtsi"
&iva {
status = "disabled";
};
&sgx_module {
status = "disabled";
};

10
arch/arm/boot/dts/am3715.dtsi Normal file
View File

@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
*/
#include "omap36xx.dtsi"
&iva {
status = "disabled";
};

162
arch/arm/boot/dts/am4372.dtsi
View File

@ -256,33 +256,92 @@ mmc3: mmc@0 {
};
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x300>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
sham_target: target-module@53100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x53100100 0x4>,
<0x53100110 0x4>,
<0x53100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap5-sham";
reg = <0 0x300>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
};
aes: aes@53501000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x53501000 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
aes_target: target-module@53501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53501080 0x4>,
<0x53501084 0x4>,
<0x53501088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53501000 0x1000>;
aes: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
};
des: des@53701000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x53701000 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
des_target: target-module@53701000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53701030 0x4>,
<0x53701034 0x4>,
<0x53701038 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x53701000 0x1000>;
des: des@0 {
compatible = "ti,omap4-des";
reg = <0 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
};
};
gpmc: gpmc@50000000 {
@ -305,17 +364,34 @@ gpmc: gpmc@50000000 {
status = "disabled";
};
qspi: spi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
target-module@47900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x47900000 0x4>,
<0x47900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
interrupts = <0 138 0x4>;
num-cs = <4>;
status = "disabled";
#size-cells = <1>;
ranges = <0x0 0x47900000 0x1000>,
<0x30000000 0x30000000 0x4000000>;
qspi: spi@0 {
compatible = "ti,am4372-qspi";
reg = <0 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
clocks = <&dpll_per_m2_div4_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 138 0x4>;
num-cs = <4>;
};
};
dss: dss@4832a000 {
@ -369,6 +445,26 @@ pm_sram_data: pm-data-sram@1000 {
pool;
};
};
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_gfx 0>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x1000000>;
};
};
};

29
arch/arm/boot/dts/am437x-l4.dtsi
View File

@ -225,7 +225,6 @@ i2c0: i2c@0 {
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
@ -763,7 +762,6 @@ i2c1: i2c@0 {
target-module@30000 { /* 0x48030000, ap 65 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
@ -900,7 +898,6 @@ timer2: timer@0 {
target-module@42000 { /* 0x48042000, ap 20 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
@ -927,7 +924,6 @@ timer3: timer@0 {
target-module@44000 { /* 0x48044000, ap 22 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
@ -955,7 +951,6 @@ timer4: timer@0 {
target-module@46000 { /* 0x48046000, ap 24 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
@ -983,7 +978,6 @@ timer5: timer@0 {
target-module@48000 { /* 0x48048000, ap 26 1a.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
@ -1011,7 +1005,6 @@ timer6: timer@0 {
target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
@ -1107,7 +1100,6 @@ mmc1: mmc@0 {
target-module@80000 { /* 0x48080000, ap 32 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@ -1169,7 +1161,6 @@ mbox_wkupm3: wkup_m3 {
target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
@ -1282,7 +1273,6 @@ i2c2: i2c@0 {
target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
@ -1313,7 +1303,6 @@ spi1: spi@0 {
target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi2";
reg = <0xa2000 0x4>,
<0xa2110 0x4>,
<0xa2114 0x4>;
@ -1344,7 +1333,6 @@ spi2: spi@0 {
target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi3";
reg = <0xa4000 0x4>,
<0xa4110 0x4>,
<0xa4114 0x4>;
@ -1527,7 +1515,6 @@ gpio3: gpio@0 {
target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer8";
reg = <0xc1000 0x4>,
<0xc1010 0x4>,
<0xc1014 0x4>;
@ -1556,7 +1543,6 @@ target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
@ -1577,7 +1563,6 @@ target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";
@ -1695,7 +1680,6 @@ segment@300000 { /* 0x48300000 */
target-module@0 { /* 0x48300000, ap 56 40.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
@ -1748,7 +1732,6 @@ ehrpwm0: pwm@200 {
target-module@2000 { /* 0x48302000, ap 58 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
@ -1801,7 +1784,6 @@ ehrpwm1: pwm@200 {
target-module@4000 { /* 0x48304000, ap 60 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@ -1854,7 +1836,6 @@ ehrpwm2: pwm@200 {
target-module@6000 { /* 0x48306000, ap 96 58.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss3";
reg = <0x6000 0x4>,
<0x6004 0x4>;
reg-names = "rev", "sysc";
@ -1896,7 +1877,6 @@ ehrpwm3: pwm@200 {
target-module@8000 { /* 0x48308000, ap 98 54.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss4";
reg = <0x8000 0x4>,
<0x8004 0x4>;
reg-names = "rev", "sysc";
@ -1938,7 +1918,6 @@ ehrpwm4: pwm@48308200 {
target-module@a000 { /* 0x4830a000, ap 100 60.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss5";
reg = <0xa000 0x4>,
<0xa004 0x4>;
reg-names = "rev", "sysc";
@ -2086,7 +2065,6 @@ gpio5: gpio@0 {
target-module@26000 { /* 0x48326000, ap 86 66.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "vpfe0";
reg = <0x26000 0x4>,
<0x26104 0x4>;
reg-names = "rev", "sysc";
@ -2113,7 +2091,6 @@ vpfe0: vpfe@0 {
target-module@28000 { /* 0x48328000, ap 75 0e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "vpfe1";
reg = <0x28000 0x4>,
<0x28104 0x4>;
reg-names = "rev", "sysc";
@ -2162,7 +2139,6 @@ target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer9";
reg = <0x3d000 0x4>,
<0x3d010 0x4>,
<0x3d014 0x4>;
@ -2189,7 +2165,6 @@ timer9: timer@0 {
target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer10";
reg = <0x3f000 0x4>,
<0x3f010 0x4>,
<0x3f014 0x4>;
@ -2216,7 +2191,6 @@ timer10: timer@0 {
target-module@41000 { /* 0x48341000, ap 106 76.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer11";
reg = <0x41000 0x4>,
<0x41010 0x4>,
<0x41014 0x4>;
@ -2243,7 +2217,6 @@ timer11: timer@0 {
target-module@45000 { /* 0x48345000, ap 108 6a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi4";
reg = <0x45000 0x4>,
<0x45110 0x4>,
<0x45114 0x4>;
@ -2358,7 +2331,6 @@ usb1: usb@10000 {
target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ocp2scp0";
reg = <0xa8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
@ -2440,7 +2412,6 @@ usb2: usb@10000 {
target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ocp2scp1";
reg = <0xe8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */

27
arch/arm/boot/dts/am437x-sk-evm.dts
View File

@ -272,6 +272,12 @@ AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};
clkout1_pin: pinmux_clkout1_pin {
pinctrl-single,pins = <
0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
@ -593,6 +599,25 @@ &i2c1 {
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&clkout1_pin>;
clocks = <&clkout1_mux_ck>;
clock-names = "xvclk";
assigned-clocks = <&clkout1_mux_ck>;
assigned-clock-parents = <&clkout1_osc_div_ck>;
port {
ov2659_1: endpoint {
remote-endpoint = <&vpfe0_ep>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
edt-ft5306@38 {
status = "okay";
compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
@ -877,7 +902,7 @@ &vpfe0 {
/* Camera port */
port {
vpfe0_ep: endpoint {
/* remote-endpoint = <&sensor>; add once we have it */
remote-endpoint = <&ov2659_1>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;

23
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -145,6 +145,12 @@ sound0_master: simple-audio-card,codec {
system-clock-frequency = <12000000>;
};
};
audio_mstrclk: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
};
&am43xx_pinmux {
@ -696,6 +702,21 @@ tlv320aic3111: tlv320aic3111@18 {
IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
};
ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
clocks = <&audio_mstrclk>;
clock-names = "xvclk";
port {
ov2659_1: endpoint {
remote-endpoint = <&vpfe1_ep>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
};
&i2c2 {
@ -964,7 +985,7 @@ &vpfe1 {
port {
vpfe1_ep: endpoint {
/* remote-endpoint = <&sensor>; add once we have it */
remote-endpoint = <&ov2659_1>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;

54
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -704,6 +704,60 @@ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
ti,bit-shift = <8>;
reg = <0x2a48>;
};
clkout1_osc_div_ck: clkout1-osc-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
};
clkout1_src2_mux_ck: clkout1-src2-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
};
clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4100>;
};
clkout1_mux_ck: clkout1-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
clkout1_ck: clkout1-ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
};
};
&prcm {

59
arch/arm/boot/dts/am57xx-idk-common.dtsi
View File

@ -9,6 +9,7 @@ / {
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
display0 = &hdmi0;
};
chosen {
@ -96,6 +97,48 @@ led-out7 {
default-state = "off";
};
};
hdmi0: connector@0 {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder@0 {
compatible = "ti,tpd12s016", "ti,tpd12s015";
gpios = <0>, /* optional CT_CP_HPD */
<0>, /* optional LS_OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint@0 {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint@0 {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&dra7_pmx_core {
@ -485,3 +528,19 @@ partition@6 {
&cpu0 {
vdd-supply = <&smps12_reg>;
};
&hdmi {
status = "okay";
vdda-supply = <&ldo4_reg>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&dss {
status = "okay";
};

115
arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts Normal file
View File

@ -0,0 +1,115 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "armada-385-clearfog-gtr.dtsi"
/ {
model = "SolidRun Clearfog GTR L8";
};
&mdio {
switch0: switch0@4 {
compatible = "marvell,mv88e6190";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan8";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan7";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan6";
phy-handle = <&switch0phy2>;
};
port@4 {
reg = <4>;
label = "lan5";
phy-handle = <&switch0phy3>;
};
port@5 {
reg = <5>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
port@6 {
reg = <6>;
label = "lan3";
phy-handle = <&switch0phy5>;
};
port@7 {
reg = <7>;
label = "lan2";
phy-handle = <&switch0phy6>;
};
port@8 {
reg = <8>;
label = "lan1";
phy-handle = <&switch0phy7>;
};
port@10 {
reg = <10>;
label = "cpu";
ethernet = <&eth1>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@1 {
reg = <0x1>;
};
switch0phy1: switch0phy1@2 {
reg = <0x2>;
};
switch0phy2: switch0phy2@3 {
reg = <0x3>;
};
switch0phy3: switch0phy3@4 {
reg = <0x4>;
};
switch0phy4: switch0phy4@5 {
reg = <0x5>;
};
switch0phy5: switch0phy5@6 {
reg = <0x6>;
};
switch0phy6: switch0phy6@7 {
reg = <0x7>;
};
switch0phy7: switch0phy7@8 {
reg = <0x8>;
};
};
};
};

79
arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts Normal file
View File

@ -0,0 +1,79 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "armada-385-clearfog-gtr.dtsi"
/ {
model = "SolidRun Clearfog GTR S4";
};
&sfp0 {
tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};
&mdio {
switch0: switch0@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&eth1>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
};
};

450
arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi Normal file
View File

@ -0,0 +1,450 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
*
* Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
*/
/*
SERDES mapping -
0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
1. 6141 switch (2.5Gbps capable)
2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
3. USB 3.0 Host
4. mini PCIe CON2 - PCIe2
5. SFP connector, or optionally SGMII Ethernet 1512 PHY
USB 2.0 mapping -
0. USB 2.0 - 0 USB pins header CON12
1. USB 2.0 - 1 mini PCIe CON2
2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
Pin mapping -
0,1 - console UART
2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
front panel and PSE controller
4,5 - MDC/MDIO
6..17 - RGMII
18 - Topaz switch reset (active low)
19 - 1512 phy reset
20 - 1512 phy reset (eth2, optional)
21,28,37,38,39,40 - SD0
22 - USB 3.0 current limiter enable (active high)
24 - SFP TX fault (input active high)
25 - SFP present (input active low)
26,27 - I2C1 - connected to SFP
29 - Fan PWM
30 - CON4 mini PCIe wifi disable
31 - CON3 mini PCIe wifi disable
32 - Fuse programming power toggle (1.8v)
33 - CON4 mini PCIe reset
34 - CON2 mini PCIe wifi disable
35 - CON3 mini PCIe reset
36 - Rear button (GPIO active low)
41 - CON1 front panel connector
42 - Front LED1, or front panel CON1
43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
44 - CON2 mini PCIe reset
45 - TPM PIRQ signal, or front panel CON1
46 - SFP TX disable
47 - Control isolation of boot sensitive SAR signals
48 - PSE reset
49 - PSE OSS signal
50 - PSE interrupt
52 - Front LED2, or front panel
53 - Front button
54 - SFP LOS (input active high)
55 - Fan sense
56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"
/ {
compatible = "marvell,armada385", "marvell,armada380";
aliases {
/* So that mvebu u-boot can update the MAC addresses */
ethernet1 = &eth0;
ethernet2 = &eth1;
ethernet3 = &eth2;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
v_usb3_con: regulator-v-usb3-con {
compatible = "regulator-fixed";
gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "v_usb3_con";
vin-supply = <&reg_5p0v>;
regulator-boot-on;
regulator-always-on;
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {
rtc@a3800 {
status = "okay";
};
i2c@11000 { /* ROM, temp sensor and front panel */
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
};
i2c@11100 { /* SFP (CON5/CON6) */
pinctrl-0 = <&cf_gtr_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
pinctrl@18000 {
cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
marvell,pins = "mpp18";
marvell,function = "gpio";
};
cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
marvell,pins = "mpp22";
marvell,function = "gpio";
};
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
cf_gtr_i2c1_pins: i2c1-pins {
/* SFP */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
cf_gtr_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp59";
marvell,function = "spi1";
};
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
marvell,pins = "mpp36";
marvell,function = "gpio";
};
};
sdhci@d8000 {
bus-width = <4>;
no-1-8-v;
non-removable;
pinctrl-0 = <&cf_gtr_sdhci_pins>;
pinctrl-names = "default";
status = "okay";
vmmc = <&reg_3p3v>;
wp-inverted;
};
usb@58000 {
status = "okay";
};
usb3@f0000 {
status = "okay";
};
usb3@f8000 {
vbus-supply = <&v_usb3_con>;
status = "okay";
};
};
pcie {
status = "okay";
/*
* The PCIe units are accessible through
* the mini-PCIe connectors on the board.
*/
pcie@1,0 {
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
pcie@2,0 {
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
pcie@3,0 {
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
};
sfp0: sfp {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
pinctrl-names = "default";
button_0 {
label = "Rear Button";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_0>;
};
button_1 {
label = "Front Button";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_1>;
};
};
gpio-leds {
compatible = "gpio-leds";
led1 {
function = LED_FUNCTION_CPU;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
led2 {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
};
};
};
&bm {
status = "okay";
};
&bm_bppi {
status = "okay";
};
&eth0 {
/* ethernet@70000 */
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy_dedicated>;
phy-mode = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <0>;
bm,pool-short = <1>;
status = "okay";
};
&eth1 {
/* ethernet@30000 */
bm,pool-long = <2>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
phys = <&comphy1 1>;
phy-mode = "2500base-x";
status = "okay";
fixed-link {
speed = <2500>;
full-duplex;
};
};
&eth2 {
/* ethernet@34000 */
bm,pool-long = <3>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
managed = "in-band-status";
phys = <&comphy5 1>;
phy-mode = "sgmii";
sfp = <&sfp0>;
status = "okay";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
phy_dedicated: ethernet-phy@0 {
/*
* Annoyingly, the marvell phy driver configures the LED
* register, rather than preserving reset-loaded setting.
* We undo that rubbish here.
*/
marvell,reg-init = <3 16 0 0x1017>;
reg = <0>;
};
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
/*
* CS0: W25Q32 flash
*/
pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
pinctrl-names = "default";
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
status = "okay";
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/* U26 temperature sensor placed near SoC */
temp1: nct75@4c {
compatible = "lm75";
reg = <0x4c>;
};
/* U27 temperature sensor placed near RTC battery */
temp2: nct75@4d {
compatible = "lm75";
reg = <0x4d>;
};
/* 2Kb eeprom */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
};
};
&ahci0 {
status = "okay";
};
&ahci1 {
status = "okay";
};
&gpio0 {
pinctrl-0 = <&cf_gtr_fan_pwm>;
pinctrl-names = "default";
wifi-disable {
gpio-hog;
gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
output-low;
line-name = "wifi-disable";
};
};
&gpio1 {
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
pinctrl-names = "default";
lte-disable {
gpio-hog;
gpios = <2 GPIO_ACTIVE_LOW>;
output-low;
line-name = "lte-disable";
};
/*
* This signal, when asserted, isolates Armada 38x sample at reset pins
* from control of external devices. Should be de-asserted after reset.
*/
sar-isolation {
gpio-hog;
gpios = <15 GPIO_ACTIVE_LOW>;
output-low;
line-name = "sar-isolation";
};
poe-reset {
gpio-hog;
gpios = <16 GPIO_ACTIVE_LOW>;
output-low;
line-name = "poe-reset";
};
};

11
arch/arm/boot/dts/armada-388-clearfog.dtsi
View File

@ -111,11 +111,6 @@ &eth2 {
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
@ -183,6 +178,12 @@ mikrobus_adc: mcp3021@4c {
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
};
&i2c1 {

5
arch/arm/boot/dts/armada-388-helios4.dts
View File

@ -140,11 +140,6 @@ usb3_phy: usb3-phy {
soc {
internal-regs {
i2c@11000 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-Board Revision bit 0 #

13
arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
View File

@ -71,6 +71,19 @@ phy_dedicated: ethernet-phy@0 {
};
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&pinctrl {
microsom_phy_clk_pins: microsom-phy-clk-pins {
marvell,pins = "mpp45";

1
arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
View File

@ -76,7 +76,6 @@ &uart5 {
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};

1
arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
View File

@ -75,7 +75,6 @@ &uart5 {
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};

1
arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts
View File

@ -35,7 +35,6 @@ &uart2 {
&mac0 {
status = "okay";
use-ncsi;
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,

20
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
View File

@ -97,22 +97,22 @@ &i2c3 {
status = "okay";
power-supply@68 {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x68>;
};
power-supply@69 {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x69>;
};
power-supply@6a {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x6a>;
};
power-supply@6b {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x6b>;
};
};
@ -352,18 +352,8 @@ eeprom@51 {
&i2c8 {
status = "okay";
ucd90320@b {
compatible = "ti,ucd90160";
reg = <0x0b>;
};
ucd90320@c {
compatible = "ti,ucd90160";
reg = <0x0c>;
};
ucd90320@11 {
compatible = "ti,ucd90160";
compatible = "ti,ucd90320";
reg = <0x11>;
};

2
arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
View File

@ -94,8 +94,6 @@ ps1-presence {
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {

2
arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
View File

@ -82,8 +82,6 @@ iio-hwmon-battery {
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
scm0-presence {

18
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
View File

@ -14,7 +14,7 @@ chosen {
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
@ -107,10 +107,7 @@ flash@0 {
&mac0 {
status = "okay";
use-ncsi;
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
@ -236,3 +233,16 @@ &vuart {
&wdt2 {
aspeed,alt-boot;
};
&sdmmc {
status = "okay";
};
&sdhci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
cd-inverted;
disable-wp;
};

2
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
View File

@ -77,8 +77,6 @@ iio-hwmon-battery {
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {

21
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -179,18 +179,21 @@ syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2400-pinctrl";
};
p2a: p2a-control {
p2a: p2a-control@2c {
reg = <0x2c 0x4>;
compatible = "aspeed,ast2400-p2a-ctrl";
status = "disabled";
};
pinctrl: pinctrl@80 {
reg = <0x80 0x18>, <0xa0 0x10>;
compatible = "aspeed,ast2400-pinctrl";
};
};
rng: hwrng@1e6e2078 {
@ -346,14 +349,14 @@ lpc_host: lpc-host@80 {
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2400-lpc-ctrl";
reg = <0x0 0x80>;
reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2400-lpc-snoop";
reg = <0x0 0x80>;
reg = <0x10 0x8>;
interrupts = <8>;
status = "disabled";
};

49
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -47,13 +47,6 @@ memory@80000000 {
reg = <0x80000000 0>;
};
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2500-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <0>;
status = "disabled";
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -213,23 +206,32 @@ apb {
#size-cells = <1>;
ranges;
edac: memory-controller@1e6e0000 {
compatible = "aspeed,ast2500-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <0>;
status = "disabled";
};
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
p2a: p2a-control@2c {
compatible = "aspeed,ast2500-p2a-ctrl";
reg = <0x2c 0x4>;
status = "disabled";
};
p2a: p2a-control {
compatible = "aspeed,ast2500-p2a-ctrl";
status = "disabled";
pinctrl: pinctrl@80 {
compatible = "aspeed,ast2500-pinctrl";
reg = <0x80 0x18>, <0xa0 0x10>;
aspeed,external-nodes = <&gfx>, <&lhc>;
};
};
@ -460,29 +462,30 @@ kcs4: kcs4@0 {
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2500-lpc-snoop";
reg = <0x0 0x80>;
reg = <0x10 0x8>;
interrupts = <8>;
status = "disabled";
};
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
};
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
ibt: ibt@c0 {
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0xc0 0x18>;

2
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -365,7 +365,7 @@ wdt3: watchdog@1e785080 {
status = "disabled";
};
wdt4: watchdog@1e7850C0 {
wdt4: watchdog@1e7850c0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
status = "disabled";

1
arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi
View File

@ -71,7 +71,6 @@ flash1@0 {
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};

172
arch/arm/boot/dts/at91-kizbox.dts
View File

@ -28,85 +28,6 @@ main_xtal {
};
};
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};
usart3: serial@fffd0000 {
status = "okay";
};
dbgu: serial@fffff200 {
status = "okay";
};
watchdog@fffffd40 {
timeout-sec = <15>;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
status = "okay";
};
};
usb0: ohci@500000 {
num-ports = <1>;
status = "okay";
};
ebi: ebi@10000000 {
status = "okay";
nand_controller: nand-controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@ -127,15 +48,6 @@ user {
};
};
i2c-gpio-0 {
status = "okay";
rtc: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
pwm_leds {
compatible = "pwm-leds";
@ -179,3 +91,87 @@ &pinctrl_tcb1_tioa2
&pinctrl_tcb1_tiob0>;
};
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
&ebi {
status = "okay";
};
&nand_controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
&macb0 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};
&usart3 {
status = "okay";
};
&dbgu {
status = "okay";
};
&watchdog {
timeout-sec = <15>;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
status = "okay";
};
&usb0 {
num-ports = <1>;
status = "okay";
};
&i2c_gpio0 {
status = "okay";
rtc: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};

24
arch/arm/boot/dts/at91-kizboxmini-base.dts Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini
* base board
*
* Copyright (C) 2015 Overkiz SAS
* Author: Antoine Aubert <a.aubert@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini";
compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
};
&pinctrl_usart0 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
};

165
arch/arm/boot/dts/at91-kizboxmini.dts → arch/arm/boot/dts/at91-kizboxmini-common.dtsi
View File

@ -1,17 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// SPDX-License-Identifier: GPL-2.0
/*
* at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
*
* Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
* Copyright (C) 2014-2018 Overkiz SAS
* Author: Antoine Aubert <a.aubert@overkiz.com>
* Gaël Portay <g.portay@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
* Dorian Rocipon <d.rocipon@overkiz.com>
*/
/dts-v1/;
#include "at91sam9g25.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Overkiz Kizbox mini";
compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
bootargs = "ubi.mtd=ubi";
stdout-path = &dbgu;
@ -22,24 +21,16 @@ memory {
};
clocks {
main_xtal {
clock-frequency = <12000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
adc_op_clk {
status = "disabled";
};
};
@ -63,17 +54,25 @@ reset {
};
};
pwm_leds {
leds: pwm_leds {
compatible = "pwm-leds";
green {
led_blue: pwm_blue {
label = "pwm:blue:user";
pwms = <&pwm0 2 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "none";
status = "disabled";
};
led_green: pwm_green {
label = "pwm:green:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
red {
led_red: pwm_red {
label = "pwm:red:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;
@ -82,53 +81,12 @@ red {
};
};
&dbgu {
&usart0 {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
nand-controller {
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
};
&macb0 {
phy-mode = "rmii";
status = "okay";
@ -137,26 +95,70 @@ &macb0 {
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1
&pinctrl_pwm0_pwm1_1>;
&pinctrl_pwm0_pwm1_1
&pinctrl_pwm0_pwm2_1>;
status = "okay";
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
&dbgu {
status = "okay";
};
&usart0 {
&watchdog {
status = "okay";
};
&adc0 {
status = "disabled";
};
&rtc {
status = "disabled";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
};
&nand_controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
&usb0 {
num-ports = <1>;
status = "okay";
@ -166,6 +168,3 @@ &usb1 {
status = "okay";
};
&watchdog {
status = "okay";
};

26
arch/arm/boot/dts/at91-kizboxmini-mb.dts Normal file
View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2018 Overkiz SAS
* Author: Mickael Gardet <m.gardet@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini Mother Board";
compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
};
&usb0 {
num-ports = <2>;
};
&rtc {
status = "okay";
};
&led_blue {
status = "okay";
};

49
arch/arm/boot/dts/at91-kizboxmini-rd.dts Normal file
View File

@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2018 Overkiz SAS
* Author: Mickael Gardet <m.gardet@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini RailDIN";
compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
clocks {
adc_op_clk {
status = "okay";
};
};
};
&pinctrl {
adc0 {
pinctrl_adc0_ad5: adc0_ad5-0 {
/* pull-up disable */
atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
&usart0 {
status = "disabled";
};
&rtc {
status = "okay";
};
&led_blue {
status = "okay";
};
&adc0 {
atmel,adc-vref = <2500>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_ad5>;
atmel,adc-channels-used = <0x0020>;
status = "okay";
};

1
arch/arm/boot/dts/at91-nattis-2-natte-2.dts
View File

@ -8,7 +8,6 @@
*/
/dts-v1/;
#include "at91-linea.dtsi"
#include "sama5d3_lcd.dtsi"
#include "at91-natte.dtsi"
/ {

647
arch/arm/boot/dts/at91-sam9x60ek.dts Normal file
View File

@ -0,0 +1,647 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
*/
/dts-v1/;
#include "sam9x60.dtsi"
/ {
model = "Microchip SAM9X60-EK";
compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
regulators: regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_1v8: fixed-regulator-vdd_1v8@0 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
status = "okay";
};
vdd_1v5: fixed-regulator-vdd_1v5@1 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
status = "okay";
};
vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
compatible = "regulator-fixed";
regulator-name = "VDD1_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
compatible = "regulator-fixed";
regulator-name = "VDD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
status = "okay";
sw1 {
label = "SW1";
gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
linux,code=<0x104>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
status = "okay"; /* Conflict with pwm0. */
red {
label = "red";
gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
};
green {
label = "green";
gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
};
blue {
label = "blue";
gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&adc {
vddana-supply = <&vdd1_3v3>;
vref-supply = <&vdd1_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
status = "okay";
};
&can0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
status = "disabled"; /* Conflict with dbgu. */
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
status = "okay";
};
&classd {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_classd_default>;
atmel,pwm-type = "diff";
atmel,non-overlap-time = <10>;
status = "okay";
};
&dbgu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
status = "okay"; /* Conflict with can0. */
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
status = "okay";
nand_controller: nand-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
uboot@40000 {
label = "u-boot";
reg = <0x40000 0xc0000>;
};
ubootenvred@100000 {
label = "U-Boot Env Redundant";
reg = <0x100000 0x40000>;
};
ubootenv@140000 {
label = "U-Boot Env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x1f800000>;
};
};
};
};
};
&flx0 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c0: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
eeprom@53 {
compatible = "atmel,24c32";
reg = <0x53>;
pagesize = <16>;
size = <128>;
status = "okay";
};
};
};
&flx4 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "disabled";
spi0: spi@400 {
compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
&flx5 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart1: serial@200 {
compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "usart";
pinctrl-0 = <&pinctrl_flx5_default>;
pinctrl-names = "default";
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
};
&flx6 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c1: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx6_default>;
atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
gpio_exp: mcp23008@20 {
compatible = "microchip,mcp23008";
reg = <0x20>;
};
};
};
&i2s {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s_default>;
#sound-dai-cells = <0>;
status = "disabled"; /* Conflict with QSPI. */
};
&macb0 {
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "okay";
ethernet-phy@0 {
reg = <0x0>;
};
};
&pinctrl {
atmel,mux-mask = <
/* A B C */
0xFFFFFE7F 0xC0E0397F 0xEF00019D /* pioA */
0x03FFFFFF 0x02FC7E68 0x00780000 /* pioB */
0xffffffff 0xF83FFFFF 0xB800F3FC /* pioC */
0x003FFFFF 0x003F8000 0x00000000 /* pioD */
>;
adc {
pinctrl_adc_default: adc_default {
atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adtrg_default: adtrg_default {
atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
};
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
i2s {
pinctrl_i2s_default: i2s {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SCK */
AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SWS */
AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDIN */
AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDOUT */
AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* I2SMCK */
};
};
qspi {
pinctrl_qspi: qspi {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
};
};
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_ebi_data_0_15: ebi-data-msb-0 {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_ebi_addr_nand: ebi-addr-0 {
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
};
flexcom {
pinctrl_flx0_default: flx0_twi {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_flx4_default: flx4_spi {
atmel,pins =
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_flx5_default: flx_uart {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_flx6_default: flx6_twi {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
};
classd {
pinctrl_classd_default: classd {
atmel,pins =
<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
};
};
can0 {
pinctrl_can0_rx_tx: can0_rx_tx {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0 */
AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX0 */
AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN0 mux */
AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
};
};
can1 {
pinctrl_can1_rx_tx: can1_rx_tx {
atmel,pins =
<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1 RXD1 */
AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX1 TXD1 */
AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN1 mux */
AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
};
pwm0 {
pinctrl_pwm0_0: pwm0_0 {
atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_1: pwm0_1 {
atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_2: pwm0_2 {
atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_3: pwm0_3 {
atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
sdmmc0 {
pinctrl_sdmmc0_default: sdmmc0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA17 CK periph A with pullup */
AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD periph A with pullup */
AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA15 DAT0 periph A */
AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA18 DAT1 periph A with pullup */
AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA19 DAT2 periph A with pullup */
AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA20 DAT3 periph A with pullup */
};
};
gpio_keys {
pinctrl_key_gpio_default: pinctrl_key_gpio {
atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
}; /* pinctrl */
&pmc {
atmel,osc-bypass;
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
status = "disabled"; /* Conflict with leds. */
};
&sdmmc0 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
disable-wp;
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay"; /* Conflict with i2s. */
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
m25p,fast-read;
at91bootstrap@0 {
label = "qspi: at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "qspi: bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenvred@100000 {
label = "qspi: bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "qspi: bootloader env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "qspi: device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "qspi: kernel";
reg = <0x200000 0x600000>;
};
};
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
status = "okay";
input@0 {
reg = <0>;
};
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioD 15 GPIO_ACTIVE_HIGH
&pioD 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usb2 {
status = "okay";
};

4
arch/arm/boot/dts/at91-sama5d27_som1.dtsi
View File

@ -24,6 +24,10 @@ main_xtal {
};
ahb {
sdmmc0: sdio-host@a0000000 {
microchip,sdcal-inverted;
};
apb {
qspi1: spi@f0024000 {
pinctrl-names = "default";

6
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -131,6 +131,9 @@ i2c2: i2c@600 {
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
dma-names = "tx", "rx";
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
@ -246,6 +249,9 @@ i2c3: i2c@600 {
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";

304
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi Normal file
View File

@ -0,0 +1,304 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
* Author: Eugen Hristev <eugen.hristev@microcihp.com>
*/
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/pinctrl/at91.h>
/ {
model = "Microchip SAMA5D27 WLSOM1";
compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
};
&flx1 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
uart6: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(13))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(14))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "usart";
pinctrl-0 = <&pinctrl_flx1_default>;
pinctrl-names = "default";
};
};
&i2c0 {
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
mcp16502@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
status = "okay";
lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vddio_ddr: VDD_DDR {
regulator-name = "VDD_DDR";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1850000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1200000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1200000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
};
vdd_core: VDD_CORE {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1850000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vdd_ddr: VDD_OTHER {
regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
};
LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&macb0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default>;
phy-mode = "rmii";
ethernet-phy@0 {
reg = <0x0>;
interrupt-parent = <&pioA>;
interrupts = <PIN_PB24 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_phy_irq>;
};
};
&pmc {
atmel,osc-bypass;
};
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
status = "disabled";
qspi1_flash: spi_flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
status = "disabled";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenvred@100000 {
label = "bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "bootloader env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
};
};
&pioA {
pinctrl_flx1_default: flx1_usart_default {
pinmux = <PIN_PA24__FLEXCOM1_IO0>,
<PIN_PA23__FLEXCOM1_IO1>,
<PIN_PA25__FLEXCOM1_IO3>,
<PIN_PA26__FLEXCOM1_IO4>;
bias-disable;
};
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD19__TWD1>,
<PIN_PD20__TWCK1>;
bias-disable;
};
pinctrl_macb0_default: macb0_default {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_qspi1_default: qspi1_default {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>,
<PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
};

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