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Merge branch 'pci/qcom'

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- Add support for SM8250 PCIe SF TBU clock (Dmitry Baryshkov)

- Use PHY_REFCLK_USE_PAD only for qcom ipq8064 (Ansuel Smith)

* pci/qcom:
  PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064
  PCI: qcom: Add support for ddrss_sf_tbu clock
  dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for sm8250
This commit is contained in:
Bjorn Helgaas
2021-02-24 14:59:23 -06:00
parent 2ef38d7e2b 2cfef1971a
commit 9da5366938
2 changed files with 31 additions and 8 deletions
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17
Documentation/devicetree/bindings/pci/qcom,pcie.txt
View File

@ -132,8 +132,8 @@
- "master_bus" AXI Master clock - "master_bus" AXI Master clock
- "slave_bus" AXI Slave clock - "slave_bus" AXI Slave clock
-clock-names: - clock-names:
Usage: required for sdm845 and sm8250 Usage: required for sdm845
Value type: <stringlist> Value type: <stringlist>
Definition: Should contain the following entries Definition: Should contain the following entries
- "aux" Auxiliary clock - "aux" Auxiliary clock
@ -144,6 +144,19 @@
- "tbu" PCIe TBU clock - "tbu" PCIe TBU clock
- "pipe" PIPE clock - "pipe" PIPE clock
- clock-names:
Usage: required for sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "aux" Auxiliary clock
- "cfg" Configuration clock
- "bus_master" Master AXI clock
- "bus_slave" Slave AXI clock
- "slave_q2a" Slave Q2A clock
- "tbu" PCIe TBU clock
- "ddrss_sf_tbu" PCIe SF TBU clock
- "pipe" PIPE clock
- resets: - resets:
Usage: required Usage: required
Value type: <prop-encoded-array> Value type: <prop-encoded-array>

22
drivers/pci/controller/dwc/pcie-qcom.c
View File

@ -159,8 +159,10 @@ struct qcom_pcie_resources_2_3_3 {
struct reset_control *rst[7]; struct reset_control *rst[7];
}; };
/* 6 clocks typically, 7 for sm8250 */
struct qcom_pcie_resources_2_7_0 { struct qcom_pcie_resources_2_7_0 {
struct clk_bulk_data clks[6]; struct clk_bulk_data clks[7];
int num_clks;
struct regulator_bulk_data supplies[2]; struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset; struct reset_control *pci_reset;
struct clk *pipe_clk; struct clk *pipe_clk;
@ -398,7 +400,9 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
/* enable external reference clock */ /* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
val &= ~PHY_REFCLK_USE_PAD; /* USE_PAD is required only for ipq806x */
if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
val &= ~PHY_REFCLK_USE_PAD;
val |= PHY_REFCLK_SSP_EN; val |= PHY_REFCLK_SSP_EN;
writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
@ -1152,8 +1156,14 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
res->clks[3].id = "bus_slave"; res->clks[3].id = "bus_slave";
res->clks[4].id = "slave_q2a"; res->clks[4].id = "slave_q2a";
res->clks[5].id = "tbu"; res->clks[5].id = "tbu";
if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) {
res->clks[6].id = "ddrss_sf_tbu";
res->num_clks = 7;
} else {
res->num_clks = 6;
}
ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
if (ret < 0) if (ret < 0)
return ret; return ret;
@ -1175,7 +1185,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
return ret; return ret;
} }
ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
if (ret < 0) if (ret < 0)
goto err_disable_regulators; goto err_disable_regulators;
@ -1227,7 +1237,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
return 0; return 0;
err_disable_clocks: err_disable_clocks:
clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); clk_bulk_disable_unprepare(res->num_clks, res->clks);
err_disable_regulators: err_disable_regulators:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
@ -1238,7 +1248,7 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
{ {
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); clk_bulk_disable_unprepare(res->num_clks, res->clks);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
} }