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dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with generic names

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[ Upstream commit f5f185bf7c42f6ca885202fefc40fc871d08a722 ]

The DMA-related nodes RDMA/WROT in MDP3 should be changed to generic names.
In addition, fix improper space indent in example.

Fixes: 4ad7b39623 ("media: dt-binding: mediatek: add bindings for MediaTek MDP3 components")
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Moudy Ho 2023-10-31 16:33:42 +08:00 committed by Greg Kroah-Hartman
parent ba5e58dacf
commit 9c91f58498
2 changed files with 31 additions and 21 deletions
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29
Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
View File

@ -61,6 +61,9 @@ properties:
- description: used for 1st data pipe from RDMA
- description: used for 2nd data pipe from RDMA
'#dma-cells':
const: 1
required:
- compatible
- reg
@ -70,6 +73,7 @@ required:
- clocks
- iommus
- mboxes
- '#dma-cells'
additionalProperties: false
@ -80,16 +84,17 @@ examples:
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
mdp3_rdma0: mdp3-rdma0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0x14001000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
<CMDQ_EVENT_MDP_RDMA0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MDP_RSZ1>;
iommus = <&iommu>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
dma-controller@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0x14001000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
<CMDQ_EVENT_MDP_RDMA0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MDP_RSZ1>;
iommus = <&iommu>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
#dma-cells = <1>;
};

23
Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
View File

@ -50,6 +50,9 @@ properties:
iommus:
maxItems: 1
'#dma-cells':
const: 1
required:
- compatible
- reg
@ -58,6 +61,7 @@ required:
- power-domains
- clocks
- iommus
- '#dma-cells'
additionalProperties: false
@ -68,13 +72,14 @@ examples:
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
mdp3_wrot0: mdp3-wrot0@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0x14005000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
<CMDQ_EVENT_MDP_WROT0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu>;
dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0x14005000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
<CMDQ_EVENT_MDP_WROT0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu>;
#dma-cells = <1>;
};