ARM: 7459/1: irda/pxa: use readl_relaxed() to access OSCR register
After c00184f9ab4 "ARM: sa11x0/pxa: convert OS timer registers to IOMEM", magician_defconfig and a few others fail to build because the OSCR register is accessed by the drivers/net/irda/pxaficp_ir.c but has turned into a pointer that needs to be read using readl. There are other registers in the same driver that eventually should be converted, and it's unclear whether we would want a better interface to access the OSCR from a device driver. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -289,7 +289,7 @@ static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id)
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}
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lsr = STLSR;
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}
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si->last_oscr = OSCR;
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si->last_oscr = readl_relaxed(OSCR);
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break;
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case 0x04: /* Received Data Available */
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@ -300,7 +300,7 @@ static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id)
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dev->stats.rx_bytes++;
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, STRBR);
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} while (STLSR & LSR_DR);
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si->last_oscr = OSCR;
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si->last_oscr = readl_relaxed(OSCR);
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break;
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case 0x02: /* Transmit FIFO Data Request */
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@ -316,7 +316,7 @@ static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id)
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/* We need to ensure that the transmitter has finished. */
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while ((STLSR & LSR_TEMT) == 0)
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cpu_relax();
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si->last_oscr = OSCR;
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si->last_oscr = readl_relaxed(OSCR);
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/*
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* Ok, we've finished transmitting. Now enable
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@ -370,7 +370,7 @@ static void pxa_irda_fir_dma_tx_irq(int channel, void *data)
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while (ICSR1 & ICSR1_TBY)
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cpu_relax();
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si->last_oscr = OSCR;
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si->last_oscr = readl_relaxed(OSCR);
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/*
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* HACK: It looks like the TBY bit is dropped too soon.
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@ -470,7 +470,7 @@ static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id)
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/* stop RX DMA */
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DCSR(si->rxdma) &= ~DCSR_RUN;
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si->last_oscr = OSCR;
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si->last_oscr = readl_relaxed(OSCR);
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icsr0 = ICSR0;
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if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) {
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@ -546,7 +546,7 @@ static int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
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skb_copy_from_linear_data(skb, si->dma_tx_buff, skb->len);
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if (mtt)
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while ((unsigned)(OSCR - si->last_oscr)/4 < mtt)
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while ((unsigned)(readl_relaxed(OSCR) - si->last_oscr)/4 < mtt)
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cpu_relax();
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/* stop RX DMA, disable FICP */
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