common: DMA-mapping: add WRITE_COMBINE attribute
DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be buffered to improve performance. It will be used by the replacement for ARM/ARV32 specific dma_alloc_writecombine() function. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
parent
9adc537452
commit
8a4134322b
@ -31,3 +31,13 @@ may be weakly ordered, that is that reads and writes may pass each other.
|
|||||||
Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
|
Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
|
||||||
those that do not will simply ignore the attribute and exhibit default
|
those that do not will simply ignore the attribute and exhibit default
|
||||||
behavior.
|
behavior.
|
||||||
|
|
||||||
|
DMA_ATTR_WRITE_COMBINE
|
||||||
|
----------------------
|
||||||
|
|
||||||
|
DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
|
||||||
|
buffered to improve performance.
|
||||||
|
|
||||||
|
Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
|
||||||
|
those that do not will simply ignore the attribute and exhibit default
|
||||||
|
behavior.
|
||||||
|
@ -13,6 +13,7 @@
|
|||||||
enum dma_attr {
|
enum dma_attr {
|
||||||
DMA_ATTR_WRITE_BARRIER,
|
DMA_ATTR_WRITE_BARRIER,
|
||||||
DMA_ATTR_WEAK_ORDERING,
|
DMA_ATTR_WEAK_ORDERING,
|
||||||
|
DMA_ATTR_WRITE_COMBINE,
|
||||||
DMA_ATTR_MAX,
|
DMA_ATTR_MAX,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user