mtd: spi-nor: add SFDP fixups for Quad Page Program
[ Upstream commit 1799cd8540b67b88514c82f5fae1c75b986bcbd8 ] SFDP table of some flash chips do not advertise support of Quad Input Page Program even though it has support. Use flags and add hardware cap for these chips. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com> [tudor.ambarus@microchip.com: move pp setting in spi_nor_init_default_params] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220920184808.44876-2-sudip.mukherjee@sifive.com Stable-dep-of: 9fd0945fe6fa ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash") Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -2578,6 +2578,12 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
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params->hwcaps.mask |= SNOR_HWCAPS_PP;
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spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
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SPINOR_OP_PP, SNOR_PROTO_1_1_1);
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if (info->flags & SPI_NOR_QUAD_PP) {
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params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
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spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
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SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
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}
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}
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/**
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@ -458,6 +458,7 @@ struct spi_nor_fixups {
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* SPI_NOR_NO_ERASE: no erase command needed.
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* NO_CHIP_ERASE: chip does not support chip erase.
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* SPI_NOR_NO_FR: can't do fastread.
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* SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
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*
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* @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
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* Used when SFDP tables are not defined in the flash. These
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@ -507,6 +508,7 @@ struct flash_info {
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#define SPI_NOR_NO_ERASE BIT(6)
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#define NO_CHIP_ERASE BIT(7)
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#define SPI_NOR_NO_FR BIT(8)
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#define SPI_NOR_QUAD_PP BIT(9)
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u8 no_sfdp_flags;
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#define SPI_NOR_SKIP_SFDP BIT(0)
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@ -73,6 +73,7 @@ static const struct flash_info issi_nor_parts[] = {
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{ "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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FLAGS(SPI_NOR_QUAD_PP)
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.fixups = &is25lp256_fixups },
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/* PMC */
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