Merge ee96dd9614 ("Merge tag 'libnvdimm-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm") into android-mainline
Steps on the way to 5.18-rc1 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I4346c3d87bc97d67d15790157fa4c018dd4135c2
This commit is contained in:
Greg Kroah-Hartman
commit
87b45951b4
@ -6,3 +6,38 @@ Description:
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The libnvdimm sub-system implements a common sysfs interface for
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platform nvdimm resources. See Documentation/driver-api/nvdimm/.
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What: /sys/bus/event_source/devices/nmemX/format
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Date: February 2022
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KernelVersion: 5.18
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Contact: Kajol Jain <kjain@linux.ibm.com>
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Description: (RO) Attribute group to describe the magic bits
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that go into perf_event_attr.config for a particular pmu.
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(See ABI/testing/sysfs-bus-event_source-devices-format).
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Each attribute under this group defines a bit range of the
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perf_event_attr.config. Supported attribute is listed
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below::
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event = "config:0-4" - event ID
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For example::
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ctl_res_cnt = "event=0x1"
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What: /sys/bus/event_source/devices/nmemX/events
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Date: February 2022
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KernelVersion: 5.18
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Contact: Kajol Jain <kjain@linux.ibm.com>
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Description: (RO) Attribute group to describe performance monitoring events
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for the nvdimm memory device. Each attribute in this group
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describes a single performance monitoring event supported by
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this nvdimm pmu. The name of the file is the name of the event.
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(See ABI/testing/sysfs-bus-event_source-devices-events). A
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listing of the events supported by a given nvdimm provider type
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can be found in Documentation/driver-api/nvdimm/$provider.
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What: /sys/bus/event_source/devices/nmemX/cpumask
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Date: February 2022
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KernelVersion: 5.18
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Contact: Kajol Jain <kjain@linux.ibm.com>
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Description: (RO) This sysfs file exposes the cpumask which is designated to
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to retrieve nvdimm pmu event counter data.
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@ -19,7 +19,7 @@ Linux kernel. The new mechanism is based on Collaborative Processor
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Performance Control (CPPC) which provides finer grain frequency management
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than legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
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the ACPI P-states driver to manage CPU frequency and clocks with switching
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only in 3 P-states. CPPC replaces the ACPI P-states controls, allows a
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only in 3 P-states. CPPC replaces the ACPI P-states controls and allows a
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flexible, low-latency interface for the Linux kernel to directly
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communicate the performance hints to hardware.
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@ -27,7 +27,7 @@ communicate the performance hints to hardware.
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``ondemand``, etc. to manage the performance hints which are provided by
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CPPC hardware functionality that internally follows the hardware
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specification (for details refer to AMD64 Architecture Programmer's Manual
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Volume 2: System Programming [1]_). Currently ``amd-pstate`` supports basic
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Volume 2: System Programming [1]_). Currently, ``amd-pstate`` supports basic
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frequency control function according to kernel governors on some of the
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Zen2 and Zen3 processors, and we will implement more AMD specific functions
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in future after we verify them on the hardware and SBIOS.
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@ -41,9 +41,9 @@ continuous, abstract, and unit-less performance value in a scale that is
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not tied to a specific performance state / frequency. This is an ACPI
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standard [2]_ which software can specify application performance goals and
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hints as a relative target to the infrastructure limits. AMD processors
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provides the low latency register model (MSR) instead of AML code
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provide the low latency register model (MSR) instead of an AML code
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interpreter for performance adjustments. ``amd-pstate`` will initialize a
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``struct cpufreq_driver`` instance ``amd_pstate_driver`` with the callbacks
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``struct cpufreq_driver`` instance, ``amd_pstate_driver``, with the callbacks
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to manage each performance update behavior. ::
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Highest Perf ------>+-----------------------+ +-----------------------+
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@ -91,26 +91,26 @@ AMD CPPC Performance Capability
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Highest Performance (RO)
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.........................
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It is the absolute maximum performance an individual processor may reach,
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This is the absolute maximum performance an individual processor may reach,
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assuming ideal conditions. This performance level may not be sustainable
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for long durations and may only be achievable if other platform components
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are in a specific state; for example, it may require other processors be in
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are in a specific state; for example, it may require other processors to be in
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an idle state. This would be equivalent to the highest frequencies
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supported by the processor.
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Nominal (Guaranteed) Performance (RO)
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......................................
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It is the maximum sustained performance level of the processor, assuming
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ideal operating conditions. In absence of an external constraint (power,
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thermal, etc.) this is the performance level the processor is expected to
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This is the maximum sustained performance level of the processor, assuming
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ideal operating conditions. In the absence of an external constraint (power,
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thermal, etc.), this is the performance level the processor is expected to
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be able to maintain continuously. All cores/processors are expected to be
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able to sustain their nominal performance state simultaneously.
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Lowest non-linear Performance (RO)
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...................................
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It is the lowest performance level at which nonlinear power savings are
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This is the lowest performance level at which nonlinear power savings are
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achieved, for example, due to the combined effects of voltage and frequency
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scaling. Above this threshold, lower performance levels should be generally
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more energy efficient than higher performance levels. This register
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@ -119,7 +119,7 @@ effectively conveys the most efficient performance level to ``amd-pstate``.
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Lowest Performance (RO)
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........................
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It is the absolute lowest performance level of the processor. Selecting a
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This is the absolute lowest performance level of the processor. Selecting a
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performance level lower than the lowest nonlinear performance level may
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cause an efficiency penalty but should reduce the instantaneous power
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consumption of the processor.
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@ -149,14 +149,14 @@ a relative number. This can be expressed as percentage of nominal
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performance (infrastructure max). Below the nominal sustained performance
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level, desired performance expresses the average performance level of the
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processor subject to hardware. Above the nominal performance level,
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processor must provide at least nominal performance requested and go higher
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the processor must provide at least nominal performance requested and go higher
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if current operating conditions allow.
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Energy Performance Preference (EPP) (RW)
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.........................................
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Provides a hint to the hardware if software wants to bias toward performance
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(0x0) or energy efficiency (0xff).
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This attribute provides a hint to the hardware if software wants to bias
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toward performance (0x0) or energy efficiency (0xff).
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Key Governors Support
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@ -173,35 +173,34 @@ operating frequencies supported by the hardware. Users can check the
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``amd-pstate`` mainly supports ``schedutil`` and ``ondemand`` for dynamic
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frequency control. It is to fine tune the processor configuration on
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``amd-pstate`` to the ``schedutil`` with CPU CFS scheduler. ``amd-pstate``
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registers adjust_perf callback to implement the CPPC similar performance
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update behavior. It is initialized by ``sugov_start`` and then populate the
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CPU's update_util_data pointer to assign ``sugov_update_single_perf`` as
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the utilization update callback function in CPU scheduler. CPU scheduler
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will call ``cpufreq_update_util`` and assign the target performance
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according to the ``struct sugov_cpu`` that utilization update belongs to.
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Then ``amd-pstate`` updates the desired performance according to the CPU
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registers the adjust_perf callback to implement performance update behavior
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similar to CPPC. It is initialized by ``sugov_start`` and then populates the
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CPU's update_util_data pointer to assign ``sugov_update_single_perf`` as the
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utilization update callback function in the CPU scheduler. The CPU scheduler
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will call ``cpufreq_update_util`` and assigns the target performance according
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to the ``struct sugov_cpu`` that the utilization update belongs to.
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Then, ``amd-pstate`` updates the desired performance according to the CPU
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scheduler assigned.
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Processor Support
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=======================
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The ``amd-pstate`` initialization will fail if the _CPC in ACPI SBIOS is
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not existed at the detected processor, and it uses ``acpi_cpc_valid`` to
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check the _CPC existence. All Zen based processors support legacy ACPI
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hardware P-States function, so while the ``amd-pstate`` fails to be
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initialized, the kernel will fall back to initialize ``acpi-cpufreq``
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driver.
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The ``amd-pstate`` initialization will fail if the ``_CPC`` entry in the ACPI
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SBIOS does not exist in the detected processor. It uses ``acpi_cpc_valid``
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to check the existence of ``_CPC``. All Zen based processors support the legacy
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ACPI hardware P-States function, so when ``amd-pstate`` fails initialization,
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the kernel will fall back to initialize the ``acpi-cpufreq`` driver.
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There are two types of hardware implementations for ``amd-pstate``: one is
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`Full MSR Support <perf_cap_>`_ and another is `Shared Memory Support
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<perf_cap_>`_. It can use :c:macro:`X86_FEATURE_CPPC` feature flag (for
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details refer to Processor Programming Reference (PPR) for AMD Family
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19h Model 51h, Revision A1 Processors [3]_) to indicate the different
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types. ``amd-pstate`` is to register different ``static_call`` instances
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for different hardware implementations.
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<perf_cap_>`_. It can use the :c:macro:`X86_FEATURE_CPPC` feature flag to
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indicate the different types. (For details, refer to the Processor Programming
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Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors [3]_.)
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``amd-pstate`` is to register different ``static_call`` instances for different
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hardware implementations.
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Currently, some of Zen2 and Zen3 processors support ``amd-pstate``. In the
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Currently, some of the Zen2 and Zen3 processors support ``amd-pstate``. In the
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future, it will be supported on more and more AMD processors.
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Full MSR Support
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@ -210,18 +209,18 @@ Full MSR Support
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Some new Zen3 processors such as Cezanne provide the MSR registers directly
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while the :c:macro:`X86_FEATURE_CPPC` CPU feature flag is set.
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``amd-pstate`` can handle the MSR register to implement the fast switch
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function in ``CPUFreq`` that can shrink latency of frequency control on the
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interrupt context. The functions with ``pstate_xxx`` prefix represent the
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operations of MSR registers.
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function in ``CPUFreq`` that can reduce the latency of frequency control in
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interrupt context. The functions with a ``pstate_xxx`` prefix represent the
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operations on MSR registers.
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Shared Memory Support
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----------------------
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If :c:macro:`X86_FEATURE_CPPC` CPU feature flag is not set, that means the
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processor supports shared memory solution. In this case, ``amd-pstate``
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If the :c:macro:`X86_FEATURE_CPPC` CPU feature flag is not set, the
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processor supports the shared memory solution. In this case, ``amd-pstate``
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uses the ``cppc_acpi`` helper methods to implement the callback functions
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that defined on ``static_call``. The functions with ``cppc_xxx`` prefix
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represent the operations of acpi cppc helpers for shared memory solution.
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that are defined on ``static_call``. The functions with the ``cppc_xxx`` prefix
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represent the operations of ACPI CPPC helpers for the shared memory solution.
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AMD P-States and ACPI hardware P-States always can be supported in one
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@ -234,7 +233,7 @@ User Space Interface in ``sysfs``
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==================================
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``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to
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control its functionality at the system level. They located in the
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control its functionality at the system level. They are located in the
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``/sys/devices/system/cpu/cpufreq/policyX/`` directory and affect all CPUs. ::
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root@hr-test1:/home/ray# ls /sys/devices/system/cpu/cpufreq/policy0/*amd*
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@ -246,38 +245,38 @@ control its functionality at the system level. They located in the
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``amd_pstate_highest_perf / amd_pstate_max_freq``
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Maximum CPPC performance and CPU frequency that the driver is allowed to
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set in percent of the maximum supported CPPC performance level (the highest
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set, in percent of the maximum supported CPPC performance level (the highest
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performance supported in `AMD CPPC Performance Capability <perf_cap_>`_).
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In some of ASICs, the highest CPPC performance is not the one in the _CPC
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table, so we need to expose it to sysfs. If boost is not active but
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supported, this maximum frequency will be larger than the one in
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In some ASICs, the highest CPPC performance is not the one in the ``_CPC``
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table, so we need to expose it to sysfs. If boost is not active, but
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still supported, this maximum frequency will be larger than the one in
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``cpuinfo``.
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This attribute is read-only.
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``amd_pstate_lowest_nonlinear_freq``
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The lowest non-linear CPPC CPU frequency that the driver is allowed to set
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in percent of the maximum supported CPPC performance level (Please see the
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The lowest non-linear CPPC CPU frequency that the driver is allowed to set,
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in percent of the maximum supported CPPC performance level. (Please see the
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lowest non-linear performance in `AMD CPPC Performance Capability
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<perf_cap_>`_).
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<perf_cap_>`_.)
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This attribute is read-only.
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For other performance and frequency values, we can read them back from
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Other performance and frequency values can be read back from
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``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.
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``amd-pstate`` vs ``acpi-cpufreq``
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======================================
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On majority of AMD platforms supported by ``acpi-cpufreq``, the ACPI tables
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provided by the platform firmware used for CPU performance scaling, but
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only provides 3 P-states on AMD processors.
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However, on modern AMD APU and CPU series, it provides the collaborative
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processor performance control according to ACPI protocol and customize this
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for AMD platforms. That is fine-grain and continuous frequency range
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On the majority of AMD platforms supported by ``acpi-cpufreq``, the ACPI tables
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provided by the platform firmware are used for CPU performance scaling, but
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only provide 3 P-states on AMD processors.
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However, on modern AMD APU and CPU series, hardware provides the Collaborative
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Processor Performance Control according to the ACPI protocol and customizes this
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for AMD platforms. That is, fine-grained and continuous frequency ranges
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instead of the legacy hardware P-states. ``amd-pstate`` is the kernel
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module which supports the new AMD P-States mechanism on most of future AMD
|
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platforms. The AMD P-States mechanism will be the more performance and energy
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module which supports the new AMD P-States mechanism on most of the future AMD
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platforms. The AMD P-States mechanism is the more performance and energy
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efficiency frequency management method on AMD processors.
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Kernel Module Options for ``amd-pstate``
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@ -287,25 +286,25 @@ Kernel Module Options for ``amd-pstate``
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Use a module param (shared_mem) to enable related processors manually with
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**amd_pstate.shared_mem=1**.
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Due to the performance issue on the processors with `Shared Memory Support
|
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<perf_cap_>`_, so we disable it for the moment and will enable this by default
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once we address performance issue on this solution.
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<perf_cap_>`_, we disable it presently and will re-enable this by default
|
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once we address performance issue with this solution.
|
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The way to check whether current processor is `Full MSR Support <perf_cap_>`_
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To check whether the current processor is using `Full MSR Support <perf_cap_>`_
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or `Shared Memory Support <perf_cap_>`_ : ::
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ray@hr-test1:~$ lscpu | grep cppc
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Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
|
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|
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If CPU Flags have cppc, then this processor supports `Full MSR Support
|
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<perf_cap_>`_. Otherwise it supports `Shared Memory Support <perf_cap_>`_.
|
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If the CPU flags have ``cppc``, then this processor supports `Full MSR Support
|
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<perf_cap_>`_. Otherwise, it supports `Shared Memory Support <perf_cap_>`_.
|
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|
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|
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``cpupower`` tool support for ``amd-pstate``
|
||||
===============================================
|
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|
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``amd-pstate`` is supported on ``cpupower`` tool that can be used to dump the frequency
|
||||
information. And it is in progress to support more and more operations for new
|
||||
``amd-pstate`` module with this tool. ::
|
||||
``amd-pstate`` is supported by the ``cpupower`` tool, which can be used to dump
|
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frequency information. Development is in progress to support more and more
|
||||
operations for the new ``amd-pstate`` module with this tool. ::
|
||||
|
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root@hr-test1:/home/ray# cpupower frequency-info
|
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analyzing CPU 0:
|
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@ -336,10 +335,10 @@ Trace Events
|
||||
--------------
|
||||
|
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There are two static trace events that can be used for ``amd-pstate``
|
||||
diagnostics. One of them is the cpu_frequency trace event generally used
|
||||
diagnostics. One of them is the ``cpu_frequency`` trace event generally used
|
||||
by ``CPUFreq``, and the other one is the ``amd_pstate_perf`` trace event
|
||||
specific to ``amd-pstate``. The following sequence of shell commands can
|
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be used to enable them and see their output (if the kernel is generally
|
||||
be used to enable them and see their output (if the kernel is
|
||||
configured to support event tracing). ::
|
||||
|
||||
root@hr-test1:/home/ray# cd /sys/kernel/tracing/
|
||||
@ -364,7 +363,7 @@ configured to support event tracing). ::
|
||||
<idle>-0 [003] d.s.. 4995.980971: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=3 changed=false fast_switch=true
|
||||
<idle>-0 [011] d.s.. 4995.980996: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=11 changed=false fast_switch=true
|
||||
|
||||
The cpu_frequency trace event will be triggered either by the ``schedutil`` scaling
|
||||
The ``cpu_frequency`` trace event will be triggered either by the ``schedutil`` scaling
|
||||
governor (for the policies it is attached to), or by the ``CPUFreq`` core (for the
|
||||
policies with other scaling governors).
|
||||
|
||||
|
||||
@ -42,7 +42,7 @@ patternProperties:
|
||||
description:
|
||||
The individual power management domains within this controller
|
||||
type: object
|
||||
$ref: /power/apple,pmgr-pwrstate.yaml#
|
||||
$ref: /schemas/power/apple,pmgr-pwrstate.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -1,172 +0,0 @@
|
||||
Qualcomm Technologies, Inc. CPUFREQ Bindings
|
||||
|
||||
CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
|
||||
SoCs to manage frequency in hardware. It is capable of controlling frequency
|
||||
for multiple clusters.
|
||||
|
||||
Properties:
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
|
||||
|
||||
- clocks
|
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Usage: required
|
||||
Value type: <phandle> From common clock binding.
|
||||
Definition: clock handle for XO clock and GPLL0 clock.
|
||||
|
||||
- clock-names
|
||||
Usage: required
|
||||
Value type: <string> From common clock binding.
|
||||
Definition: must be "xo", "alternate".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Addresses and sizes for the memory of the HW bases in
|
||||
each frequency domain.
|
||||
- reg-names
|
||||
Usage: Optional
|
||||
Value type: <string>
|
||||
Definition: Frequency domain name i.e.
|
||||
"freq-domain0", "freq-domain1".
|
||||
|
||||
- #freq-domain-cells:
|
||||
Usage: required.
|
||||
Definition: Number of cells in a freqency domain specifier.
|
||||
|
||||
* Property qcom,freq-domain
|
||||
Devices supporting freq-domain must set their "qcom,freq-domain" property with
|
||||
phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch
|
||||
DCVS state together.
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
L3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
cpufreq_hw: cpufreq@17d43000 {
|
||||
compatible = "qcom,cpufreq-hw";
|
||||
reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
|
||||
reg-names = "freq-domain0", "freq-domain1";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#freq-domain-cells = <1>;
|
||||
};
|
||||
}
|
||||
201
Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
Normal file
201
Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
Normal file
@ -0,0 +1,201 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. CPUFREQ
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description: |
|
||||
|
||||
CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
|
||||
SoCs to manage frequency in hardware. It is capable of controlling frequency
|
||||
for multiple clusters.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: v1 of CPUFREQ HW
|
||||
items:
|
||||
- const: qcom,cpufreq-hw
|
||||
|
||||
- description: v2 of CPUFREQ HW (EPSS)
|
||||
items:
|
||||
- enum:
|
||||
- qcom,sm8250-cpufreq-epss
|
||||
- const: qcom,cpufreq-epss
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: Frequency domain 0 register region
|
||||
- description: Frequency domain 1 register region
|
||||
- description: Frequency domain 2 register region
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: freq-domain0
|
||||
- const: freq-domain1
|
||||
- const: freq-domain2
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO Clock
|
||||
- description: GPLL0 Clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: alternate
|
||||
|
||||
'#freq-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#freq-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
// Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
|
||||
// switch DCVS state together.
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
L3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpufreq@17d43000 {
|
||||
compatible = "qcom,cpufreq-hw";
|
||||
reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
|
||||
reg-names = "freq-domain0", "freq-domain1";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#freq-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,166 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
|
||||
|
||||
maintainers:
|
||||
- Ilia Lin <ilia.lin@kernel.org>
|
||||
|
||||
description: |
|
||||
In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
|
||||
voltage is dynamically configured by Core Power Reduction (CPR) depending on
|
||||
current CPU frequency and efuse values.
|
||||
CPR provides a power domain with multiple levels that are selected depending
|
||||
on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
|
||||
according to the required OPPs defined in the CPU OPP tables.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcs404
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
cpus:
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
'cpu@[0-9a-f]+':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: cpr
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
|
||||
patternProperties:
|
||||
'^opp-table(-[a-z0-9]+)?$':
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-kryo-cpu
|
||||
then:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. QCS404";
|
||||
compatible = "qcom,qcs404";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU1: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU2: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU3: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: opp-table-cpu {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
opp-shared;
|
||||
|
||||
opp-1094400000 {
|
||||
opp-hz = /bits/ 64 <1094400000>;
|
||||
required-opps = <&cpr_opp1>;
|
||||
};
|
||||
opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
required-opps = <&cpr_opp2>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
required-opps = <&cpr_opp3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpr_opp_table: opp-table-cpr {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -66,12 +66,21 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
|
||||
aal@14015000 {
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aal@14015000 {
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -65,12 +65,21 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
|
||||
#include <dt-bindings/power/mt8183-power.h>
|
||||
#include <dt-bindings/gce/mt8183-gce.h>
|
||||
|
||||
ccorr0: ccorr@1400f000 {
|
||||
compatible = "mediatek,mt8183-disp-ccorr";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ccorr0: ccorr@1400f000 {
|
||||
compatible = "mediatek,mt8183-disp-ccorr";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -75,12 +75,21 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
|
||||
color0: color@14013000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14013000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
color0: color@14013000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14013000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -65,12 +65,21 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
|
||||
#include <dt-bindings/power/mt8183-power.h>
|
||||
#include <dt-bindings/gce/mt8183-gce.h>
|
||||
|
||||
dither0: dither@14012000 {
|
||||
compatible = "mediatek,mt8183-disp-dither";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dither0: dither@14012000 {
|
||||
compatible = "mediatek,mt8183-disp-dither";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -70,8 +70,7 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
compatible = "mediatek,mt8173-dpi";
|
||||
reg = <0x1401d000 0x1000>;
|
||||
|
||||
@ -60,12 +60,21 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
#include <dt-bindings/power/mt8195-power.h>
|
||||
#include <dt-bindings/gce/mt8195-gce.h>
|
||||
|
||||
dsc0: disp_dsc_wrap@1c009000 {
|
||||
compatible = "mediatek,mt8195-disp-dsc";
|
||||
reg = <0 0x1c009000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
|
||||
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dsc0: disp_dsc_wrap@1c009000 {
|
||||
compatible = "mediatek,mt8195-disp-dsc";
|
||||
reg = <0 0x1c009000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
|
||||
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,147 +0,0 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek Ethdr Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
ETHDR is designed for HDR video and graphics conversion in the external display path.
|
||||
It handles multiple HDR input types and performs tone mapping, color space/color
|
||||
format conversion, and then combine different layers, output the required HDR or
|
||||
SDR signal to the subsequent display path. This engine is composed of two video
|
||||
frontends, two graphic frontends, one video backend and a mixer. ETHDR has two
|
||||
DMA function blocks, DS and ADL. These two function blocks read the pre-programmed
|
||||
registers from DRAM and set them to HW in the v-blanking period.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: mediatek,mt8195-disp-ethdr
|
||||
reg:
|
||||
maxItems: 7
|
||||
reg-names:
|
||||
items:
|
||||
- const: mixer
|
||||
- const: vdo_fe0
|
||||
- const: vdo_fe1
|
||||
- const: gfx_fe0
|
||||
- const: gfx_fe1
|
||||
- const: vdo_be
|
||||
- const: adl_ds
|
||||
interrupts:
|
||||
minItems: 1
|
||||
iommus:
|
||||
description: The compatible property is DMA function blocks.
|
||||
Should point to the respective IOMMU block with master port as argument,
|
||||
see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
|
||||
details.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
clocks:
|
||||
items:
|
||||
- description: mixer clock
|
||||
- description: video frontend 0 clock
|
||||
- description: video frontend 1 clock
|
||||
- description: graphic frontend 0 clock
|
||||
- description: graphic frontend 1 clock
|
||||
- description: video backend clock
|
||||
- description: autodownload and menuload clock
|
||||
- description: video frontend 0 async clock
|
||||
- description: video frontend 1 async clock
|
||||
- description: graphic frontend 0 async clock
|
||||
- description: graphic frontend 1 async clock
|
||||
- description: video backend async clock
|
||||
- description: ethdr top clock
|
||||
clock-names:
|
||||
items:
|
||||
- const: mixer
|
||||
- const: vdo_fe0
|
||||
- const: vdo_fe1
|
||||
- const: gfx_fe0
|
||||
- const: gfx_fe1
|
||||
- const: vdo_be
|
||||
- const: adl_ds
|
||||
- const: vdo_fe0_async
|
||||
- const: vdo_fe1_async
|
||||
- const: gfx_fe0_async
|
||||
- const: gfx_fe1_async
|
||||
- const: vdo_be_async
|
||||
- const: ethdr_top
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
resets:
|
||||
maxItems: 5
|
||||
mediatek,gce-client-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: The register of display function block to be set by gce.
|
||||
There are 4 arguments in this property, gce node, subsys id, offset and
|
||||
register size. The subsys id is defined in the gce header of each chips
|
||||
include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
|
||||
display function block.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
disp_ethdr@1c114000 {
|
||||
compatible = "mediatek,mt8195-disp-ethdr";
|
||||
reg = <0 0x1c114000 0 0x1000>,
|
||||
<0 0x1c115000 0 0x1000>,
|
||||
<0 0x1c117000 0 0x1000>,
|
||||
<0 0x1c119000 0 0x1000>,
|
||||
<0 0x1c11A000 0 0x1000>,
|
||||
<0 0x1c11B000 0 0x1000>,
|
||||
<0 0x1c11C000 0 0x1000>;
|
||||
reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
|
||||
"vdo_be", "adl_ds";
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xA000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xB000 0x1000>,
|
||||
<&gce0 SUBSYS_1c11XXXX 0xC000 0x1000>;
|
||||
clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_BE>,
|
||||
<&vdosys1 CLK_VDO1_26M_SLOW>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
|
||||
<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
|
||||
<&topckgen CLK_TOP_ETHDR_SEL>;
|
||||
clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
|
||||
"vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
|
||||
"gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
|
||||
"ethdr_top";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
|
||||
<&iommu_vpp M4U_PORT_L3_HDR_ADL>;
|
||||
interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
|
||||
<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -66,12 +66,21 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
|
||||
gamma@14016000 {
|
||||
compatible = "mediatek,mt8173-disp-gamma";
|
||||
reg = <0 0x14016000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
gamma@14016000 {
|
||||
compatible = "mediatek,mt8173-disp-gamma";
|
||||
reg = <0 0x14016000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -38,18 +38,16 @@ properties:
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: MERGE Clock
|
||||
- description: MERGE Async Clock
|
||||
Controlling the synchronous process between MERGE and other display
|
||||
function blocks cross clock domain.
|
||||
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: merge
|
||||
- const: merge_async
|
||||
oneOf:
|
||||
- items:
|
||||
- const: merge
|
||||
- items:
|
||||
- const: merge
|
||||
- const: merge_async
|
||||
|
||||
mediatek,merge-fifo-en:
|
||||
description:
|
||||
@ -88,23 +86,20 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
|
||||
merge@14017000 {
|
||||
compatible = "mediatek,mt8173-disp-merge";
|
||||
reg = <0 0x14017000 0 0x1000>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_MERGE>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
merge@14017000 {
|
||||
compatible = "mediatek,mt8173-disp-merge";
|
||||
reg = <0 0x14017000 0 0x1000>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_MERGE>;
|
||||
clock-names = "merge";
|
||||
};
|
||||
};
|
||||
|
||||
merge5: disp_vpp_merge5@1c110000 {
|
||||
compatible = "mediatek,mt8195-disp-merge";
|
||||
reg = <0 0x1c110000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
|
||||
<&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
|
||||
clock-names = "merge","merge_async";
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
|
||||
mediatek,merge-fifo-en = <1>;
|
||||
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
|
||||
};
|
||||
|
||||
@ -58,7 +58,7 @@ properties:
|
||||
The event id which is mapping to the specific hardware event signal
|
||||
to gce. The event id is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -71,13 +71,22 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
|
||||
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
|
||||
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -45,9 +45,15 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -66,13 +66,23 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
|
||||
#include <dt-bindings/power/mt8183-power.h>
|
||||
#include <dt-bindings/gce/mt8183-gce.h>
|
||||
#include <dt-bindings/memory/mt8183-larb-port.h>
|
||||
|
||||
ovl_2l0: ovl@14009000 {
|
||||
compatible = "mediatek,mt8183-disp-ovl-2l";
|
||||
reg = <0 0x14009000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
|
||||
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ovl_2l0: ovl@14009000 {
|
||||
compatible = "mediatek,mt8183-disp-ovl-2l";
|
||||
reg = <0 0x14009000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
|
||||
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -75,19 +75,29 @@ required:
|
||||
- interrupts
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommu
|
||||
- iommus
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
#include <dt-bindings/memory/mt8173-larb-port.h>
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -58,12 +58,21 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8192-clk.h>
|
||||
#include <dt-bindings/power/mt8192-power.h>
|
||||
#include <dt-bindings/gce/mt8192-gce.h>
|
||||
|
||||
postmask0: postmask@1400d000 {
|
||||
compatible = "mediatek,mt8192-disp-postmask";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
postmask0: postmask@1400d000 {
|
||||
compatible = "mediatek,mt8192-disp-postmask";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -94,14 +94,24 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
#include <dt-bindings/memory/mt8173-larb-port.h>
|
||||
|
||||
rdma0: rdma@1400e000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
||||
mediatek,rdma-fifosize = <8192>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rdma0: rdma@1400e000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
||||
mediatek,rdma-fifo-size = <8192>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -49,10 +49,17 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
|
||||
split0: split@14018000 {
|
||||
compatible = "mediatek,mt8173-disp-split";
|
||||
reg = <0 0x14018000 0 0x1000>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
split0: split@14018000 {
|
||||
compatible = "mediatek,mt8173-disp-split";
|
||||
reg = <0 0x14018000 0 0x1000>;
|
||||
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -51,11 +51,18 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ufoe@1401a000 {
|
||||
compatible = "mediatek,mt8173-disp-ufoe";
|
||||
reg = <0 0x1401a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
ufoe@1401a000 {
|
||||
compatible = "mediatek,mt8173-disp-ufoe";
|
||||
reg = <0 0x1401a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -64,13 +64,23 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
#include <dt-bindings/memory/mt8173-larb-port.h>
|
||||
|
||||
wdma0: wdma@14011000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14011000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
wdma0: wdma@14011000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14011000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -51,10 +51,16 @@ additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
performance: performance-controller@12340000 {
|
||||
compatible = "qcom,cpufreq-hw";
|
||||
reg = <0x12340000 0x1000>;
|
||||
#performance-domain-cells = <1>;
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
performance: performance-controller@11bc00 {
|
||||
compatible = "mediatek,cpufreq-hw";
|
||||
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
|
||||
|
||||
#performance-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
// The node above defines a performance controller that is a performance
|
||||
|
||||
@ -72,10 +72,10 @@ properties:
|
||||
Describes the physical address space of IOMMU maps to memory.
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
const: 2
|
||||
|
||||
ranges: true
|
||||
|
||||
@ -205,61 +205,67 @@ examples:
|
||||
#include <dt-bindings/clock/mt8192-clk.h>
|
||||
#include <dt-bindings/power/mt8192-power.h>
|
||||
|
||||
video-codec@16000000 {
|
||||
compatible = "mediatek,mt8192-vcodec-dec";
|
||||
mediatek,scp = <&scp>;
|
||||
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
|
||||
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x16000000 0x40000>;
|
||||
reg = <0x16000000 0x1000>; /* VDEC_SYS */
|
||||
vcodec-lat@10000 {
|
||||
compatible = "mediatek,mtk-vcodec-lat";
|
||||
reg = <0x10000 0x800>;
|
||||
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
|
||||
<&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
|
||||
};
|
||||
bus@16000000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0x16000000 0x16000000 0 0x40000>;
|
||||
|
||||
vcodec-core@25000 {
|
||||
compatible = "mediatek,mtk-vcodec-core";
|
||||
reg = <0x25000 0x1000>;
|
||||
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
|
||||
<&vdecsys CLK_VDEC_VDEC>,
|
||||
<&vdecsys CLK_VDEC_LAT>,
|
||||
<&vdecsys CLK_VDEC_LARB1>,
|
||||
<&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
|
||||
video-codec@16000000 {
|
||||
compatible = "mediatek,mt8192-vcodec-dec";
|
||||
mediatek,scp = <&scp>;
|
||||
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
|
||||
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0 0 0x16000000 0 0x40000>;
|
||||
reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
|
||||
vcodec-lat@10000 {
|
||||
compatible = "mediatek,mtk-vcodec-lat";
|
||||
reg = <0 0x10000 0 0x800>;
|
||||
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
|
||||
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
|
||||
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
|
||||
<&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
|
||||
};
|
||||
|
||||
vcodec-core@25000 {
|
||||
compatible = "mediatek,mtk-vcodec-core";
|
||||
reg = <0 0x25000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
|
||||
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
|
||||
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
|
||||
<&vdecsys CLK_VDEC_VDEC>,
|
||||
<&vdecsys CLK_VDEC_LAT>,
|
||||
<&vdecsys CLK_VDEC_LARB1>,
|
||||
<&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
|
||||
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
|
||||
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -15,7 +15,7 @@ description:
|
||||
Ethernet switch port Description
|
||||
|
||||
allOf:
|
||||
- $ref: "http://devicetree.org/schemas/net/ethernet-controller.yaml#"
|
||||
- $ref: /schemas/net/ethernet-controller.yaml#
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
||||
@ -340,21 +340,21 @@ allOf:
|
||||
description:
|
||||
Programmable Burst Length (tx and rx)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [2, 4, 8]
|
||||
enum: [1, 2, 4, 8, 16, 32]
|
||||
|
||||
snps,txpbl:
|
||||
description:
|
||||
Tx Programmable Burst Length. If set, DMA tx will use this
|
||||
value rather than snps,pbl.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [2, 4, 8]
|
||||
enum: [1, 2, 4, 8, 16, 32]
|
||||
|
||||
snps,rxpbl:
|
||||
description:
|
||||
Rx Programmable Burst Length. If set, DMA rx will use this
|
||||
value rather than snps,pbl.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [2, 4, 8]
|
||||
enum: [1, 2, 4, 8, 16, 32]
|
||||
|
||||
snps,no-pbl-x8:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
@ -93,6 +93,21 @@ patternProperties:
|
||||
minItems: 1
|
||||
maxItems: 8 # Should be enough regulators
|
||||
|
||||
opp-microwatt:
|
||||
description: |
|
||||
The power for the OPP in micro-Watts.
|
||||
|
||||
Entries for multiple regulators shall be provided in the same field
|
||||
separated by angular brackets <>. If current values aren't required
|
||||
for a regulator, then it shall be filled with 0. If power values
|
||||
aren't required for any of the regulators, then this field is not
|
||||
required. The OPP binding doesn't provide any provisions to relate the
|
||||
values to their power supplies or the order in which the supplies need
|
||||
to be configured and that is left for the implementation specific
|
||||
binding.
|
||||
minItems: 1
|
||||
maxItems: 8 # Should be enough regulators
|
||||
|
||||
opp-level:
|
||||
description:
|
||||
A value representing the performance level of the device.
|
||||
@ -205,6 +220,14 @@ patternProperties:
|
||||
minItems: 1
|
||||
maxItems: 8 # Should be enough regulators
|
||||
|
||||
'^opp-microwatt':
|
||||
description:
|
||||
Named opp-microwatt property. Similar to opp-microamp property,
|
||||
but for microwatt instead.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8 # Should be enough regulators
|
||||
|
||||
dependencies:
|
||||
opp-avg-kBps: [ opp-peak-kBps ]
|
||||
|
||||
|
||||
257
Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
Normal file
257
Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
Normal file
@ -0,0 +1,257 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. NVMEM OPP bindings
|
||||
|
||||
maintainers:
|
||||
- Ilia Lin <ilia.lin@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: opp-v2-base.yaml#
|
||||
|
||||
description: |
|
||||
In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
|
||||
the CPU frequencies subset and voltage value of each OPP varies based on
|
||||
the silicon variant in use.
|
||||
Qualcomm Technologies, Inc. Process Voltage Scaling Tables
|
||||
defines the voltage and frequency value based on the msm-id in SMEM
|
||||
and speedbin blown in the efuse combination.
|
||||
The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
|
||||
to provide the OPP framework with required information (existing HW bitmap).
|
||||
This is used to determine the voltage and frequency value for each OPP of
|
||||
operating-points-v2 table when it is parsed by the OPP framework.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-kryo-cpu
|
||||
|
||||
nvmem-cells:
|
||||
description: |
|
||||
A phandle pointing to a nvmem-cells node representing the
|
||||
efuse registers that has information about the
|
||||
speedbin that is used to select the right frequency/voltage
|
||||
value pair.
|
||||
|
||||
opp-shared: true
|
||||
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
opp-hz: true
|
||||
|
||||
opp-microvolt: true
|
||||
|
||||
opp-supported-hw:
|
||||
description: |
|
||||
A single 32 bit bitmap value, representing compatible HW.
|
||||
Bitmap:
|
||||
0: MSM8996 V3, speedbin 0
|
||||
1: MSM8996 V3, speedbin 1
|
||||
2: MSM8996 V3, speedbin 2
|
||||
3: unused
|
||||
4: MSM8996 SG, speedbin 0
|
||||
5: MSM8996 SG, speedbin 1
|
||||
6: MSM8996 SG, speedbin 2
|
||||
7-31: unused
|
||||
maximum: 0x77
|
||||
|
||||
clock-latency-ns: true
|
||||
|
||||
required-opps: true
|
||||
|
||||
required:
|
||||
- opp-hz
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
if:
|
||||
required:
|
||||
- nvmem-cells
|
||||
then:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
required:
|
||||
- opp-supported-hw
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. DB820c";
|
||||
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&kryocc 0>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&kryocc 0>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&kryocc 1>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&kryocc 1>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x71>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2150400000 {
|
||||
opp-hz = /bits/ 64 <2150400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x31>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2342400000 {
|
||||
opp-hz = /bits/ 64 <2342400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
smem {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
qfprom: qfprom@74000 {
|
||||
compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
|
||||
reg = <0x00074000 0x8ff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
speedbin_efuse: speedbin@133 {
|
||||
reg = <0x133 0x1>;
|
||||
bits = <5 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
60
Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml
Normal file
60
Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm OPP bindings to describe OPP nodes.
|
||||
|
||||
maintainers:
|
||||
- Niklas Cassel <nks@flawful.org>
|
||||
|
||||
allOf:
|
||||
- $ref: opp-v2-base.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-qcom-level
|
||||
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
opp-level: true
|
||||
|
||||
qcom,opp-fuse-level:
|
||||
description: |
|
||||
A positive value representing the fuse corner/level associated with
|
||||
this OPP node. Sometimes several corners/levels shares a certain fuse
|
||||
corner/level. A fuse corner/level contains e.g. ref uV, min uV,
|
||||
and max uV.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- opp-level
|
||||
- qcom,opp-fuse-level
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpr_opp_table: opp-table-cpr {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
@ -1,796 +0,0 @@
|
||||
Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
|
||||
===================================
|
||||
|
||||
In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
|
||||
the CPU frequencies subset and voltage value of each OPP varies based on
|
||||
the silicon variant in use.
|
||||
Qualcomm Technologies, Inc. Process Voltage Scaling Tables
|
||||
defines the voltage and frequency value based on the msm-id in SMEM
|
||||
and speedbin blown in the efuse combination.
|
||||
The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
|
||||
to provide the OPP framework with required information (existing HW bitmap).
|
||||
This is used to determine the voltage and frequency value for each OPP of
|
||||
operating-points-v2 table when it is parsed by the OPP framework.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
In 'cpu' nodes:
|
||||
- operating-points-v2: Phandle to the operating-points-v2 table to use.
|
||||
|
||||
In 'operating-points-v2' table:
|
||||
- compatible: Should be
|
||||
- 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
|
||||
apq8064, ipq8064, msm8960 and ipq8074.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
In 'cpu' nodes:
|
||||
- power-domains: A phandle pointing to the PM domain specifier which provides
|
||||
the performance states available for active state management.
|
||||
Please refer to the power-domains bindings
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
and also examples below.
|
||||
- power-domain-names: Should be
|
||||
- 'cpr' for qcs404.
|
||||
|
||||
In 'operating-points-v2' table:
|
||||
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
|
||||
efuse registers that has information about the
|
||||
speedbin that is used to select the right frequency/voltage
|
||||
value pair.
|
||||
Please refer the for nvmem-cells
|
||||
bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
|
||||
and also examples below.
|
||||
|
||||
In every OPP node:
|
||||
- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
|
||||
Bitmap:
|
||||
0: MSM8996 V3, speedbin 0
|
||||
1: MSM8996 V3, speedbin 1
|
||||
2: MSM8996 V3, speedbin 2
|
||||
3: unused
|
||||
4: MSM8996 SG, speedbin 0
|
||||
5: MSM8996 SG, speedbin 1
|
||||
6: MSM8996 SG, speedbin 2
|
||||
7-31: unused
|
||||
|
||||
Example 1:
|
||||
---------
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
clocks = <&kryocc 0>;
|
||||
cpu-supply = <&pm8994_s11_saw>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
clocks = <&kryocc 0>;
|
||||
cpu-supply = <&pm8994_s11_saw>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
clocks = <&kryocc 1>;
|
||||
cpu-supply = <&pm8994_s11_saw>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
clocks = <&kryocc 1>;
|
||||
cpu-supply = <&pm8994_s11_saw>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-422400000 {
|
||||
opp-hz = /bits/ 64 <422400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-460800000 {
|
||||
opp-hz = /bits/ 64 <460800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-480000000 {
|
||||
opp-hz = /bits/ 64 <480000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-537600000 {
|
||||
opp-hz = /bits/ 64 <537600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-556800000 {
|
||||
opp-hz = /bits/ 64 <556800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-652800000 {
|
||||
opp-hz = /bits/ 64 <652800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-691200000 {
|
||||
opp-hz = /bits/ 64 <691200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-729600000 {
|
||||
opp-hz = /bits/ 64 <729600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-768000000 {
|
||||
opp-hz = /bits/ 64 <768000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-844800000 {
|
||||
opp-hz = /bits/ 64 <844800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-902400000 {
|
||||
opp-hz = /bits/ 64 <902400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-960000000 {
|
||||
opp-hz = /bits/ 64 <960000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-979200000 {
|
||||
opp-hz = /bits/ 64 <979200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1036800000 {
|
||||
opp-hz = /bits/ 64 <1036800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1113600000 {
|
||||
opp-hz = /bits/ 64 <1113600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1132800000 {
|
||||
opp-hz = /bits/ 64 <1132800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1209600000 {
|
||||
opp-hz = /bits/ 64 <1209600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1228800000 {
|
||||
opp-hz = /bits/ 64 <1228800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1286400000 {
|
||||
opp-hz = /bits/ 64 <1286400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1324800000 {
|
||||
opp-hz = /bits/ 64 <1324800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x5>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1363200000 {
|
||||
opp-hz = /bits/ 64 <1363200000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x72>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x5>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1440000000 {
|
||||
opp-hz = /bits/ 64 <1440000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1478400000 {
|
||||
opp-hz = /bits/ 64 <1478400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1497600000 {
|
||||
opp-hz = /bits/ 64 <1497600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x4>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1516800000 {
|
||||
opp-hz = /bits/ 64 <1516800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x71>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1996800000 {
|
||||
opp-hz = /bits/ 64 <1996800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x20>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-403200000 {
|
||||
opp-hz = /bits/ 64 <403200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-460800000 {
|
||||
opp-hz = /bits/ 64 <460800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-480000000 {
|
||||
opp-hz = /bits/ 64 <480000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-537600000 {
|
||||
opp-hz = /bits/ 64 <537600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-556800000 {
|
||||
opp-hz = /bits/ 64 <556800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-652800000 {
|
||||
opp-hz = /bits/ 64 <652800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-691200000 {
|
||||
opp-hz = /bits/ 64 <691200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-729600000 {
|
||||
opp-hz = /bits/ 64 <729600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-748800000 {
|
||||
opp-hz = /bits/ 64 <748800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-806400000 {
|
||||
opp-hz = /bits/ 64 <806400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-825600000 {
|
||||
opp-hz = /bits/ 64 <825600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-883200000 {
|
||||
opp-hz = /bits/ 64 <883200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-902400000 {
|
||||
opp-hz = /bits/ 64 <902400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-940800000 {
|
||||
opp-hz = /bits/ 64 <940800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-979200000 {
|
||||
opp-hz = /bits/ 64 <979200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1036800000 {
|
||||
opp-hz = /bits/ 64 <1036800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1113600000 {
|
||||
opp-hz = /bits/ 64 <1113600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1132800000 {
|
||||
opp-hz = /bits/ 64 <1132800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1209600000 {
|
||||
opp-hz = /bits/ 64 <1209600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1286400000 {
|
||||
opp-hz = /bits/ 64 <1286400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1324800000 {
|
||||
opp-hz = /bits/ 64 <1324800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1363200000 {
|
||||
opp-hz = /bits/ 64 <1363200000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1440000000 {
|
||||
opp-hz = /bits/ 64 <1440000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1478400000 {
|
||||
opp-hz = /bits/ 64 <1478400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1516800000 {
|
||||
opp-hz = /bits/ 64 <1516800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1555200000 {
|
||||
opp-hz = /bits/ 64 <1555200000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1632000000 {
|
||||
opp-hz = /bits/ 64 <1632000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1670400000 {
|
||||
opp-hz = /bits/ 64 <1670400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1708800000 {
|
||||
opp-hz = /bits/ 64 <1708800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1747200000 {
|
||||
opp-hz = /bits/ 64 <1747200000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1785600000 {
|
||||
opp-hz = /bits/ 64 <1785600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1804800000 {
|
||||
opp-hz = /bits/ 64 <1804800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x6>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1824000000 {
|
||||
opp-hz = /bits/ 64 <1824000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x71>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1900800000 {
|
||||
opp-hz = /bits/ 64 <1900800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x74>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1920000000 {
|
||||
opp-hz = /bits/ 64 <1920000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1977600000 {
|
||||
opp-hz = /bits/ 64 <1977600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1996800000 {
|
||||
opp-hz = /bits/ 64 <1996800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2054400000 {
|
||||
opp-hz = /bits/ 64 <2054400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2073600000 {
|
||||
opp-hz = /bits/ 64 <2073600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2150400000 {
|
||||
opp-hz = /bits/ 64 <2150400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x31>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2246400000 {
|
||||
opp-hz = /bits/ 64 <2246400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2342400000 {
|
||||
opp-hz = /bits/ 64 <2342400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
....
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
....
|
||||
smem_mem: smem-mem@86000000 {
|
||||
reg = <0x0 0x86000000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
....
|
||||
};
|
||||
|
||||
smem {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
....
|
||||
qfprom: qfprom@74000 {
|
||||
compatible = "qcom,qfprom";
|
||||
reg = <0x00074000 0x8ff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
....
|
||||
speedbin_efuse: speedbin@133 {
|
||||
reg = <0x133 0x1>;
|
||||
bits = <5 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example 2:
|
||||
---------
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
....
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU1: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
....
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU2: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
....
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU3: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
....
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: cpu-opp-table {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
opp-shared;
|
||||
|
||||
opp-1094400000 {
|
||||
opp-hz = /bits/ 64 <1094400000>;
|
||||
required-opps = <&cpr_opp1>;
|
||||
};
|
||||
opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
required-opps = <&cpr_opp2>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
required-opps = <&cpr_opp3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpr_opp_table: cpr-opp-table {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
....
|
||||
|
||||
soc {
|
||||
....
|
||||
cpr: power-controller@b018000 {
|
||||
compatible = "qcom,qcs404-cpr", "qcom,cpr";
|
||||
reg = <0x0b018000 0x1000>;
|
||||
....
|
||||
vdd-apc-supply = <&pms405_s3>;
|
||||
#power-domain-cells = <0>;
|
||||
operating-points-v2 = <&cpr_opp_table>;
|
||||
....
|
||||
};
|
||||
};
|
||||
@ -1,19 +0,0 @@
|
||||
Qualcomm OPP bindings to describe OPP nodes
|
||||
|
||||
The bindings are based on top of the operating-points-v2 bindings
|
||||
described in Documentation/devicetree/bindings/opp/opp-v2-base.yaml
|
||||
Additional properties are described below.
|
||||
|
||||
* OPP Table Node
|
||||
|
||||
Required properties:
|
||||
- compatible: Allow OPPs to express their compatibility. It should be:
|
||||
"operating-points-v2-qcom-level"
|
||||
|
||||
* OPP Node
|
||||
|
||||
Required properties:
|
||||
- qcom,opp-fuse-level: A positive value representing the fuse corner/level
|
||||
associated with this OPP node. Sometimes several corners/levels shares
|
||||
a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,
|
||||
min uV, and max uV.
|
||||
@ -1,130 +0,0 @@
|
||||
QCOM CPR (Core Power Reduction)
|
||||
|
||||
CPR (Core Power Reduction) is a technology to reduce core power on a CPU
|
||||
or other device. Each OPP of a device corresponds to a "corner" that has
|
||||
a range of valid voltages for a particular frequency. While the device is
|
||||
running at a particular frequency, CPR monitors dynamic factors such as
|
||||
temperature, etc. and suggests adjustments to the voltage to save power
|
||||
and meet silicon characteristic requirements.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: base address and size of the rbcpr register region
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the CPR interrupt
|
||||
|
||||
- clocks:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: phandle to the reference clock
|
||||
|
||||
- clock-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: must be "ref"
|
||||
|
||||
- vdd-apc-supply:
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: phandle to the vdd-apc-supply regulator
|
||||
|
||||
- #power-domain-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: should be 0
|
||||
|
||||
- operating-points-v2:
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: A phandle to the OPP table containing the
|
||||
performance states supported by the CPR
|
||||
power domain
|
||||
|
||||
- acc-syscon:
|
||||
Usage: optional
|
||||
Value type: <phandle>
|
||||
Definition: phandle to syscon for writing ACC settings
|
||||
|
||||
- nvmem-cells:
|
||||
Usage: required
|
||||
Value type: <phandle>
|
||||
Definition: phandle to nvmem cells containing the data
|
||||
that makes up a fuse corner, for each fuse corner.
|
||||
As well as the CPR fuse revision.
|
||||
|
||||
- nvmem-cell-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2",
|
||||
"cpr_quotient_offset3", "cpr_init_voltage1",
|
||||
"cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1",
|
||||
"cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1",
|
||||
"cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision"
|
||||
for qcs404.
|
||||
|
||||
Example:
|
||||
|
||||
cpr_opp_table: cpr-opp-table {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
power-controller@b018000 {
|
||||
compatible = "qcom,qcs404-cpr", "qcom,cpr";
|
||||
reg = <0x0b018000 0x1000>;
|
||||
interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "ref";
|
||||
vdd-apc-supply = <&pms405_s3>;
|
||||
#power-domain-cells = <0>;
|
||||
operating-points-v2 = <&cpr_opp_table>;
|
||||
acc-syscon = <&tcsr>;
|
||||
|
||||
nvmem-cells = <&cpr_efuse_quot_offset1>,
|
||||
<&cpr_efuse_quot_offset2>,
|
||||
<&cpr_efuse_quot_offset3>,
|
||||
<&cpr_efuse_init_voltage1>,
|
||||
<&cpr_efuse_init_voltage2>,
|
||||
<&cpr_efuse_init_voltage3>,
|
||||
<&cpr_efuse_quot1>,
|
||||
<&cpr_efuse_quot2>,
|
||||
<&cpr_efuse_quot3>,
|
||||
<&cpr_efuse_ring1>,
|
||||
<&cpr_efuse_ring2>,
|
||||
<&cpr_efuse_ring3>,
|
||||
<&cpr_efuse_revision>;
|
||||
nvmem-cell-names = "cpr_quotient_offset1",
|
||||
"cpr_quotient_offset2",
|
||||
"cpr_quotient_offset3",
|
||||
"cpr_init_voltage1",
|
||||
"cpr_init_voltage2",
|
||||
"cpr_init_voltage3",
|
||||
"cpr_quotient1",
|
||||
"cpr_quotient2",
|
||||
"cpr_quotient3",
|
||||
"cpr_ring_osc1",
|
||||
"cpr_ring_osc2",
|
||||
"cpr_ring_osc3",
|
||||
"cpr_fuse_revision";
|
||||
};
|
||||
160
Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
Normal file
160
Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
Normal file
@ -0,0 +1,160 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Core Power Reduction (CPR) bindings
|
||||
|
||||
maintainers:
|
||||
- Niklas Cassel <nks@flawful.org>
|
||||
|
||||
description: |
|
||||
CPR (Core Power Reduction) is a technology to reduce core power on a CPU
|
||||
or other device. Each OPP of a device corresponds to a "corner" that has
|
||||
a range of valid voltages for a particular frequency. While the device is
|
||||
running at a particular frequency, CPR monitors dynamic factors such as
|
||||
temperature, etc. and suggests adjustments to the voltage to save power
|
||||
and meet silicon characteristic requirements.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qcs404-cpr
|
||||
- const: qcom,cpr
|
||||
|
||||
reg:
|
||||
description: Base address and size of the RBCPR register region.
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Reference clock.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
|
||||
vdd-apc-supply:
|
||||
description: APC regulator supply.
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
|
||||
operating-points-v2:
|
||||
description: |
|
||||
A phandle to the OPP table containing the performance states
|
||||
supported by the CPR power domain.
|
||||
|
||||
acc-syscon:
|
||||
description: A phandle to the syscon used for writing ACC settings.
|
||||
|
||||
nvmem-cells:
|
||||
items:
|
||||
- description: Corner 1 quotient offset
|
||||
- description: Corner 2 quotient offset
|
||||
- description: Corner 3 quotient offset
|
||||
- description: Corner 1 initial voltage
|
||||
- description: Corner 2 initial voltage
|
||||
- description: Corner 3 initial voltage
|
||||
- description: Corner 1 quotient
|
||||
- description: Corner 2 quotient
|
||||
- description: Corner 3 quotient
|
||||
- description: Corner 1 ring oscillator
|
||||
- description: Corner 2 ring oscillator
|
||||
- description: Corner 3 ring oscillator
|
||||
- description: Fuse revision
|
||||
|
||||
nvmem-cell-names:
|
||||
items:
|
||||
- const: cpr_quotient_offset1
|
||||
- const: cpr_quotient_offset2
|
||||
- const: cpr_quotient_offset3
|
||||
- const: cpr_init_voltage1
|
||||
- const: cpr_init_voltage2
|
||||
- const: cpr_init_voltage3
|
||||
- const: cpr_quotient1
|
||||
- const: cpr_quotient2
|
||||
- const: cpr_quotient3
|
||||
- const: cpr_ring_osc1
|
||||
- const: cpr_ring_osc2
|
||||
- const: cpr_ring_osc3
|
||||
- const: cpr_fuse_revision
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- vdd-apc-supply
|
||||
- '#power-domain-cells'
|
||||
- operating-points-v2
|
||||
- nvmem-cells
|
||||
- nvmem-cell-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
cpr_opp_table: opp-table-cpr {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
power-controller@b018000 {
|
||||
compatible = "qcom,qcs404-cpr", "qcom,cpr";
|
||||
reg = <0x0b018000 0x1000>;
|
||||
interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "ref";
|
||||
vdd-apc-supply = <&pms405_s3>;
|
||||
#power-domain-cells = <0>;
|
||||
operating-points-v2 = <&cpr_opp_table>;
|
||||
acc-syscon = <&tcsr>;
|
||||
|
||||
nvmem-cells = <&cpr_efuse_quot_offset1>,
|
||||
<&cpr_efuse_quot_offset2>,
|
||||
<&cpr_efuse_quot_offset3>,
|
||||
<&cpr_efuse_init_voltage1>,
|
||||
<&cpr_efuse_init_voltage2>,
|
||||
<&cpr_efuse_init_voltage3>,
|
||||
<&cpr_efuse_quot1>,
|
||||
<&cpr_efuse_quot2>,
|
||||
<&cpr_efuse_quot3>,
|
||||
<&cpr_efuse_ring1>,
|
||||
<&cpr_efuse_ring2>,
|
||||
<&cpr_efuse_ring3>,
|
||||
<&cpr_efuse_revision>;
|
||||
nvmem-cell-names = "cpr_quotient_offset1",
|
||||
"cpr_quotient_offset2",
|
||||
"cpr_quotient_offset3",
|
||||
"cpr_init_voltage1",
|
||||
"cpr_init_voltage2",
|
||||
"cpr_init_voltage3",
|
||||
"cpr_quotient1",
|
||||
"cpr_quotient2",
|
||||
"cpr_quotient3",
|
||||
"cpr_ring_osc1",
|
||||
"cpr_ring_osc2",
|
||||
"cpr_ring_osc3",
|
||||
"cpr_fuse_revision";
|
||||
};
|
||||
@ -103,7 +103,7 @@ patternProperties:
|
||||
supports up to 50MHz, up to four chip selects, programmable
|
||||
data path from 4 bits to 32 bits and numerous protocol
|
||||
variants.
|
||||
$ref: /spi/spi-controller.yaml#
|
||||
$ref: /schemas/spi/spi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -18,7 +18,7 @@ description: |
|
||||
capability of this controller.
|
||||
|
||||
allOf:
|
||||
- $ref: /spi/spi-controller.yaml#
|
||||
- $ref: /schemas/spi/spi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -16,7 +16,7 @@ description: The QSPI controller allows SPI protocol communication in single,
|
||||
as NOR flash.
|
||||
|
||||
allOf:
|
||||
- $ref: /spi/spi-controller.yaml#
|
||||
- $ref: /schemas/spi/spi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -44,7 +44,7 @@ description: |
|
||||
compatibility.
|
||||
|
||||
allOf:
|
||||
- $ref: /spi/spi-controller.yaml#
|
||||
- $ref: /schemas/spi/spi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -132,7 +132,7 @@ properties:
|
||||
default: host
|
||||
|
||||
connector:
|
||||
$ref: /connector/usb-connector.yaml#
|
||||
$ref: /schemas/connector/usb-connector.yaml#
|
||||
description:
|
||||
Connector for dual role switch, especially for "gpio-usb-b-connector"
|
||||
type: object
|
||||
@ -191,7 +191,7 @@ properties:
|
||||
patternProperties:
|
||||
"^usb@[0-9a-f]+$":
|
||||
type: object
|
||||
$ref: /usb/mediatek,mtk-xhci.yaml#
|
||||
$ref: /schemas/usb/mediatek,mtk-xhci.yaml#
|
||||
description:
|
||||
The xhci should be added as subnode to mtu3 as shown in the following
|
||||
example if the host mode is enabled.
|
||||
|
||||
@ -63,7 +63,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
connector:
|
||||
$ref: /connector/usb-connector.yaml#
|
||||
$ref: /schemas/connector/usb-connector.yaml#
|
||||
description: Connector for dual role switch
|
||||
type: object
|
||||
|
||||
|
||||
@ -14,10 +14,8 @@ Version 13
|
||||
Overview
|
||||
Supporting Documents
|
||||
Git Trees
|
||||
LIBNVDIMM PMEM and BLK
|
||||
Why BLK?
|
||||
PMEM vs BLK
|
||||
BLK-REGIONs, PMEM-REGIONs, Atomic Sectors, and DAX
|
||||
LIBNVDIMM PMEM
|
||||
PMEM-REGIONs, Atomic Sectors, and DAX
|
||||
Example NVDIMM Platform
|
||||
LIBNVDIMM Kernel Device Model and LIBNDCTL Userspace API
|
||||
LIBNDCTL: Context
|
||||
@ -53,19 +51,12 @@ PMEM:
|
||||
block device composed of PMEM is capable of DAX. A PMEM address range
|
||||
may span an interleave of several DIMMs.
|
||||
|
||||
BLK:
|
||||
A set of one or more programmable memory mapped apertures provided
|
||||
by a DIMM to access its media. This indirection precludes the
|
||||
performance benefit of interleaving, but enables DIMM-bounded failure
|
||||
modes.
|
||||
|
||||
DPA:
|
||||
DIMM Physical Address, is a DIMM-relative offset. With one DIMM in
|
||||
the system there would be a 1:1 system-physical-address:DPA association.
|
||||
Once more DIMMs are added a memory controller interleave must be
|
||||
decoded to determine the DPA associated with a given
|
||||
system-physical-address. BLK capacity always has a 1:1 relationship
|
||||
with a single-DIMM's DPA range.
|
||||
system-physical-address.
|
||||
|
||||
DAX:
|
||||
File system extensions to bypass the page cache and block layer to
|
||||
@ -84,30 +75,30 @@ BTT:
|
||||
Block Translation Table: Persistent memory is byte addressable.
|
||||
Existing software may have an expectation that the power-fail-atomicity
|
||||
of writes is at least one sector, 512 bytes. The BTT is an indirection
|
||||
table with atomic update semantics to front a PMEM/BLK block device
|
||||
table with atomic update semantics to front a PMEM block device
|
||||
driver and present arbitrary atomic sector sizes.
|
||||
|
||||
LABEL:
|
||||
Metadata stored on a DIMM device that partitions and identifies
|
||||
(persistently names) storage between PMEM and BLK. It also partitions
|
||||
BLK storage to host BTTs with different parameters per BLK-partition.
|
||||
Note that traditional partition tables, GPT/MBR, are layered on top of a
|
||||
BLK or PMEM device.
|
||||
(persistently names) capacity allocated to different PMEM namespaces. It
|
||||
also indicates whether an address abstraction like a BTT is applied to
|
||||
the namepsace. Note that traditional partition tables, GPT/MBR, are
|
||||
layered on top of a PMEM namespace, or an address abstraction like BTT
|
||||
if present, but partition support is deprecated going forward.
|
||||
|
||||
|
||||
Overview
|
||||
========
|
||||
|
||||
The LIBNVDIMM subsystem provides support for three types of NVDIMMs, namely,
|
||||
PMEM, BLK, and NVDIMM devices that can simultaneously support both PMEM
|
||||
and BLK mode access. These three modes of operation are described by
|
||||
the "NVDIMM Firmware Interface Table" (NFIT) in ACPI 6. While the LIBNVDIMM
|
||||
implementation is generic and supports pre-NFIT platforms, it was guided
|
||||
by the superset of capabilities need to support this ACPI 6 definition
|
||||
for NVDIMM resources. The bulk of the kernel implementation is in place
|
||||
to handle the case where DPA accessible via PMEM is aliased with DPA
|
||||
accessible via BLK. When that occurs a LABEL is needed to reserve DPA
|
||||
for exclusive access via one mode a time.
|
||||
The LIBNVDIMM subsystem provides support for PMEM described by platform
|
||||
firmware or a device driver. On ACPI based systems the platform firmware
|
||||
conveys persistent memory resource via the ACPI NFIT "NVDIMM Firmware
|
||||
Interface Table" in ACPI 6. While the LIBNVDIMM subsystem implementation
|
||||
is generic and supports pre-NFIT platforms, it was guided by the
|
||||
superset of capabilities need to support this ACPI 6 definition for
|
||||
NVDIMM resources. The original implementation supported the
|
||||
block-window-aperture capability described in the NFIT, but that support
|
||||
has since been abandoned and never shipped in a product.
|
||||
|
||||
Supporting Documents
|
||||
--------------------
|
||||
@ -125,107 +116,38 @@ Git Trees
|
||||
---------
|
||||
|
||||
LIBNVDIMM:
|
||||
https://git.kernel.org/cgit/linux/kernel/git/djbw/nvdimm.git
|
||||
https://git.kernel.org/cgit/linux/kernel/git/nvdimm/nvdimm.git
|
||||
LIBNDCTL:
|
||||
https://github.com/pmem/ndctl.git
|
||||
PMEM:
|
||||
https://github.com/01org/prd
|
||||
|
||||
|
||||
LIBNVDIMM PMEM and BLK
|
||||
======================
|
||||
LIBNVDIMM PMEM
|
||||
==============
|
||||
|
||||
Prior to the arrival of the NFIT, non-volatile memory was described to a
|
||||
system in various ad-hoc ways. Usually only the bare minimum was
|
||||
provided, namely, a single system-physical-address range where writes
|
||||
are expected to be durable after a system power loss. Now, the NFIT
|
||||
specification standardizes not only the description of PMEM, but also
|
||||
BLK and platform message-passing entry points for control and
|
||||
configuration.
|
||||
platform message-passing entry points for control and configuration.
|
||||
|
||||
For each NVDIMM access method (PMEM, BLK), LIBNVDIMM provides a block
|
||||
device driver:
|
||||
PMEM (nd_pmem.ko): Drives a system-physical-address range. This range is
|
||||
contiguous in system memory and may be interleaved (hardware memory controller
|
||||
striped) across multiple DIMMs. When interleaved the platform may optionally
|
||||
provide details of which DIMMs are participating in the interleave.
|
||||
|
||||
1. PMEM (nd_pmem.ko): Drives a system-physical-address range. This
|
||||
range is contiguous in system memory and may be interleaved (hardware
|
||||
memory controller striped) across multiple DIMMs. When interleaved the
|
||||
platform may optionally provide details of which DIMMs are participating
|
||||
in the interleave.
|
||||
It is worth noting that when the labeling capability is detected (a EFI
|
||||
namespace label index block is found), then no block device is created
|
||||
by default as userspace needs to do at least one allocation of DPA to
|
||||
the PMEM range. In contrast ND_NAMESPACE_IO ranges, once registered,
|
||||
can be immediately attached to nd_pmem. This latter mode is called
|
||||
label-less or "legacy".
|
||||
|
||||
Note that while LIBNVDIMM describes system-physical-address ranges that may
|
||||
alias with BLK access as ND_NAMESPACE_PMEM ranges and those without
|
||||
alias as ND_NAMESPACE_IO ranges, to the nd_pmem driver there is no
|
||||
distinction. The different device-types are an implementation detail
|
||||
that userspace can exploit to implement policies like "only interface
|
||||
with address ranges from certain DIMMs". It is worth noting that when
|
||||
aliasing is present and a DIMM lacks a label, then no block device can
|
||||
be created by default as userspace needs to do at least one allocation
|
||||
of DPA to the PMEM range. In contrast ND_NAMESPACE_IO ranges, once
|
||||
registered, can be immediately attached to nd_pmem.
|
||||
PMEM-REGIONs, Atomic Sectors, and DAX
|
||||
-------------------------------------
|
||||
|
||||
2. BLK (nd_blk.ko): This driver performs I/O using a set of platform
|
||||
defined apertures. A set of apertures will access just one DIMM.
|
||||
Multiple windows (apertures) allow multiple concurrent accesses, much like
|
||||
tagged-command-queuing, and would likely be used by different threads or
|
||||
different CPUs.
|
||||
|
||||
The NFIT specification defines a standard format for a BLK-aperture, but
|
||||
the spec also allows for vendor specific layouts, and non-NFIT BLK
|
||||
implementations may have other designs for BLK I/O. For this reason
|
||||
"nd_blk" calls back into platform-specific code to perform the I/O.
|
||||
|
||||
One such implementation is defined in the "Driver Writer's Guide" and "DSM
|
||||
Interface Example".
|
||||
|
||||
|
||||
Why BLK?
|
||||
========
|
||||
|
||||
While PMEM provides direct byte-addressable CPU-load/store access to
|
||||
NVDIMM storage, it does not provide the best system RAS (recovery,
|
||||
availability, and serviceability) model. An access to a corrupted
|
||||
system-physical-address address causes a CPU exception while an access
|
||||
to a corrupted address through an BLK-aperture causes that block window
|
||||
to raise an error status in a register. The latter is more aligned with
|
||||
the standard error model that host-bus-adapter attached disks present.
|
||||
|
||||
Also, if an administrator ever wants to replace a memory it is easier to
|
||||
service a system at DIMM module boundaries. Compare this to PMEM where
|
||||
data could be interleaved in an opaque hardware specific manner across
|
||||
several DIMMs.
|
||||
|
||||
PMEM vs BLK
|
||||
-----------
|
||||
|
||||
BLK-apertures solve these RAS problems, but their presence is also the
|
||||
major contributing factor to the complexity of the ND subsystem. They
|
||||
complicate the implementation because PMEM and BLK alias in DPA space.
|
||||
Any given DIMM's DPA-range may contribute to one or more
|
||||
system-physical-address sets of interleaved DIMMs, *and* may also be
|
||||
accessed in its entirety through its BLK-aperture. Accessing a DPA
|
||||
through a system-physical-address while simultaneously accessing the
|
||||
same DPA through a BLK-aperture has undefined results. For this reason,
|
||||
DIMMs with this dual interface configuration include a DSM function to
|
||||
store/retrieve a LABEL. The LABEL effectively partitions the DPA-space
|
||||
into exclusive system-physical-address and BLK-aperture accessible
|
||||
regions. For simplicity a DIMM is allowed a PMEM "region" per each
|
||||
interleave set in which it is a member. The remaining DPA space can be
|
||||
carved into an arbitrary number of BLK devices with discontiguous
|
||||
extents.
|
||||
|
||||
BLK-REGIONs, PMEM-REGIONs, Atomic Sectors, and DAX
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
One of the few
|
||||
reasons to allow multiple BLK namespaces per REGION is so that each
|
||||
BLK-namespace can be configured with a BTT with unique atomic sector
|
||||
sizes. While a PMEM device can host a BTT the LABEL specification does
|
||||
not provide for a sector size to be specified for a PMEM namespace.
|
||||
|
||||
This is due to the expectation that the primary usage model for PMEM is
|
||||
via DAX, and the BTT is incompatible with DAX. However, for the cases
|
||||
where an application or filesystem still needs atomic sector update
|
||||
guarantees it can register a BTT on a PMEM device or partition. See
|
||||
For the cases where an application or filesystem still needs atomic sector
|
||||
update guarantees it can register a BTT on a PMEM device or partition. See
|
||||
LIBNVDIMM/NDCTL: Block Translation Table "btt"
|
||||
|
||||
|
||||
@ -236,51 +158,40 @@ For the remainder of this document the following diagram will be
|
||||
referenced for any example sysfs layouts::
|
||||
|
||||
|
||||
(a) (b) DIMM BLK-REGION
|
||||
(a) (b) DIMM
|
||||
+-------------------+--------+--------+--------+
|
||||
+------+ | pm0.0 | blk2.0 | pm1.0 | blk2.1 | 0 region2
|
||||
+------+ | pm0.0 | free | pm1.0 | free | 0
|
||||
| imc0 +--+- - - region0- - - +--------+ +--------+
|
||||
+--+---+ | pm0.0 | blk3.0 | pm1.0 | blk3.1 | 1 region3
|
||||
+--+---+ | pm0.0 | free | pm1.0 | free | 1
|
||||
| +-------------------+--------v v--------+
|
||||
+--+---+ | |
|
||||
| cpu0 | region1
|
||||
+--+---+ | |
|
||||
| +----------------------------^ ^--------+
|
||||
+--+---+ | blk4.0 | pm1.0 | blk4.0 | 2 region4
|
||||
+--+---+ | free | pm1.0 | free | 2
|
||||
| imc1 +--+----------------------------| +--------+
|
||||
+------+ | blk5.0 | pm1.0 | blk5.0 | 3 region5
|
||||
+------+ | free | pm1.0 | free | 3
|
||||
+----------------------------+--------+--------+
|
||||
|
||||
In this platform we have four DIMMs and two memory controllers in one
|
||||
socket. Each unique interface (BLK or PMEM) to DPA space is identified
|
||||
by a region device with a dynamically assigned id (REGION0 - REGION5).
|
||||
socket. Each PMEM interleave set is identified by a region device with
|
||||
a dynamically assigned id.
|
||||
|
||||
1. The first portion of DIMM0 and DIMM1 are interleaved as REGION0. A
|
||||
single PMEM namespace is created in the REGION0-SPA-range that spans most
|
||||
of DIMM0 and DIMM1 with a user-specified name of "pm0.0". Some of that
|
||||
interleaved system-physical-address range is reclaimed as BLK-aperture
|
||||
accessed space starting at DPA-offset (a) into each DIMM. In that
|
||||
reclaimed space we create two BLK-aperture "namespaces" from REGION2 and
|
||||
REGION3 where "blk2.0" and "blk3.0" are just human readable names that
|
||||
could be set to any user-desired name in the LABEL.
|
||||
interleaved system-physical-address range is left free for
|
||||
another PMEM namespace to be defined.
|
||||
|
||||
2. In the last portion of DIMM0 and DIMM1 we have an interleaved
|
||||
system-physical-address range, REGION1, that spans those two DIMMs as
|
||||
well as DIMM2 and DIMM3. Some of REGION1 is allocated to a PMEM namespace
|
||||
named "pm1.0", the rest is reclaimed in 4 BLK-aperture namespaces (for
|
||||
each DIMM in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
|
||||
"blk5.0".
|
||||
|
||||
3. The portion of DIMM2 and DIMM3 that do not participate in the REGION1
|
||||
interleaved system-physical-address range (i.e. the DPA address past
|
||||
offset (b) are also included in the "blk4.0" and "blk5.0" namespaces.
|
||||
Note, that this example shows that BLK-aperture namespaces don't need to
|
||||
be contiguous in DPA-space.
|
||||
named "pm1.0".
|
||||
|
||||
This bus is provided by the kernel under the device
|
||||
/sys/devices/platform/nfit_test.0 when the nfit_test.ko module from
|
||||
tools/testing/nvdimm is loaded. This not only test LIBNVDIMM but the
|
||||
acpi_nfit.ko driver as well.
|
||||
tools/testing/nvdimm is loaded. This module is a unit test for
|
||||
LIBNVDIMM and the acpi_nfit.ko driver.
|
||||
|
||||
|
||||
LIBNVDIMM Kernel Device Model and LIBNDCTL Userspace API
|
||||
@ -469,17 +380,14 @@ identified by an "nfit_handle" a 32-bit value where:
|
||||
LIBNVDIMM/LIBNDCTL: Region
|
||||
--------------------------
|
||||
|
||||
A generic REGION device is registered for each PMEM range or BLK-aperture
|
||||
set. Per the example there are 6 regions: 2 PMEM and 4 BLK-aperture
|
||||
sets on the "nfit_test.0" bus. The primary role of regions are to be a
|
||||
container of "mappings". A mapping is a tuple of <DIMM,
|
||||
DPA-start-offset, length>.
|
||||
A generic REGION device is registered for each PMEM interleave-set /
|
||||
range. Per the example there are 2 PMEM regions on the "nfit_test.0"
|
||||
bus. The primary role of regions are to be a container of "mappings". A
|
||||
mapping is a tuple of <DIMM, DPA-start-offset, length>.
|
||||
|
||||
LIBNVDIMM provides a built-in driver for these REGION devices. This driver
|
||||
is responsible for reconciling the aliased DPA mappings across all
|
||||
regions, parsing the LABEL, if present, and then emitting NAMESPACE
|
||||
devices with the resolved/exclusive DPA-boundaries for the nd_pmem or
|
||||
nd_blk device driver to consume.
|
||||
LIBNVDIMM provides a built-in driver for REGION devices. This driver
|
||||
is responsible for all parsing LABELs, if present, and then emitting NAMESPACE
|
||||
devices for the nd_pmem driver to consume.
|
||||
|
||||
In addition to the generic attributes of "mapping"s, "interleave_ways"
|
||||
and "size" the REGION device also exports some convenience attributes.
|
||||
@ -493,8 +401,6 @@ LIBNVDIMM: region::
|
||||
|
||||
struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus,
|
||||
struct nd_region_desc *ndr_desc);
|
||||
struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus,
|
||||
struct nd_region_desc *ndr_desc);
|
||||
|
||||
::
|
||||
|
||||
@ -527,8 +433,9 @@ LIBNDCTL: region enumeration example
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Sample region retrieval routines based on NFIT-unique data like
|
||||
"spa_index" (interleave set id) for PMEM and "nfit_handle" (dimm id) for
|
||||
BLK::
|
||||
"spa_index" (interleave set id).
|
||||
|
||||
::
|
||||
|
||||
static struct ndctl_region *get_pmem_region_by_spa_index(struct ndctl_bus *bus,
|
||||
unsigned int spa_index)
|
||||
@ -544,139 +451,23 @@ BLK::
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct ndctl_region *get_blk_region_by_dimm_handle(struct ndctl_bus *bus,
|
||||
unsigned int handle)
|
||||
{
|
||||
struct ndctl_region *region;
|
||||
|
||||
ndctl_region_foreach(bus, region) {
|
||||
struct ndctl_mapping *map;
|
||||
|
||||
if (ndctl_region_get_type(region) != ND_DEVICE_REGION_BLOCK)
|
||||
continue;
|
||||
ndctl_mapping_foreach(region, map) {
|
||||
struct ndctl_dimm *dimm = ndctl_mapping_get_dimm(map);
|
||||
|
||||
if (ndctl_dimm_get_handle(dimm) == handle)
|
||||
return region;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
Why Not Encode the Region Type into the Region Name?
|
||||
----------------------------------------------------
|
||||
|
||||
At first glance it seems since NFIT defines just PMEM and BLK interface
|
||||
types that we should simply name REGION devices with something derived
|
||||
from those type names. However, the ND subsystem explicitly keeps the
|
||||
REGION name generic and expects userspace to always consider the
|
||||
region-attributes for four reasons:
|
||||
|
||||
1. There are already more than two REGION and "namespace" types. For
|
||||
PMEM there are two subtypes. As mentioned previously we have PMEM where
|
||||
the constituent DIMM devices are known and anonymous PMEM. For BLK
|
||||
regions the NFIT specification already anticipates vendor specific
|
||||
implementations. The exact distinction of what a region contains is in
|
||||
the region-attributes not the region-name or the region-devtype.
|
||||
|
||||
2. A region with zero child-namespaces is a possible configuration. For
|
||||
example, the NFIT allows for a DCR to be published without a
|
||||
corresponding BLK-aperture. This equates to a DIMM that can only accept
|
||||
control/configuration messages, but no i/o through a descendant block
|
||||
device. Again, this "type" is advertised in the attributes ('mappings'
|
||||
== 0) and the name does not tell you much.
|
||||
|
||||
3. What if a third major interface type arises in the future? Outside
|
||||
of vendor specific implementations, it's not difficult to envision a
|
||||
third class of interface type beyond BLK and PMEM. With a generic name
|
||||
for the REGION level of the device-hierarchy old userspace
|
||||
implementations can still make sense of new kernel advertised
|
||||
region-types. Userspace can always rely on the generic region
|
||||
attributes like "mappings", "size", etc and the expected child devices
|
||||
named "namespace". This generic format of the device-model hierarchy
|
||||
allows the LIBNVDIMM and LIBNDCTL implementations to be more uniform and
|
||||
future-proof.
|
||||
|
||||
4. There are more robust mechanisms for determining the major type of a
|
||||
region than a device name. See the next section, How Do I Determine the
|
||||
Major Type of a Region?
|
||||
|
||||
How Do I Determine the Major Type of a Region?
|
||||
----------------------------------------------
|
||||
|
||||
Outside of the blanket recommendation of "use libndctl", or simply
|
||||
looking at the kernel header (/usr/include/linux/ndctl.h) to decode the
|
||||
"nstype" integer attribute, here are some other options.
|
||||
|
||||
1. module alias lookup
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The whole point of region/namespace device type differentiation is to
|
||||
decide which block-device driver will attach to a given LIBNVDIMM namespace.
|
||||
One can simply use the modalias to lookup the resulting module. It's
|
||||
important to note that this method is robust in the presence of a
|
||||
vendor-specific driver down the road. If a vendor-specific
|
||||
implementation wants to supplant the standard nd_blk driver it can with
|
||||
minimal impact to the rest of LIBNVDIMM.
|
||||
|
||||
In fact, a vendor may also want to have a vendor-specific region-driver
|
||||
(outside of nd_region). For example, if a vendor defined its own LABEL
|
||||
format it would need its own region driver to parse that LABEL and emit
|
||||
the resulting namespaces. The output from module resolution is more
|
||||
accurate than a region-name or region-devtype.
|
||||
|
||||
2. udev
|
||||
^^^^^^^
|
||||
|
||||
The kernel "devtype" is registered in the udev database::
|
||||
|
||||
# udevadm info --path=/devices/platform/nfit_test.0/ndbus0/region0
|
||||
P: /devices/platform/nfit_test.0/ndbus0/region0
|
||||
E: DEVPATH=/devices/platform/nfit_test.0/ndbus0/region0
|
||||
E: DEVTYPE=nd_pmem
|
||||
E: MODALIAS=nd:t2
|
||||
E: SUBSYSTEM=nd
|
||||
|
||||
# udevadm info --path=/devices/platform/nfit_test.0/ndbus0/region4
|
||||
P: /devices/platform/nfit_test.0/ndbus0/region4
|
||||
E: DEVPATH=/devices/platform/nfit_test.0/ndbus0/region4
|
||||
E: DEVTYPE=nd_blk
|
||||
E: MODALIAS=nd:t3
|
||||
E: SUBSYSTEM=nd
|
||||
|
||||
...and is available as a region attribute, but keep in mind that the
|
||||
"devtype" does not indicate sub-type variations and scripts should
|
||||
really be understanding the other attributes.
|
||||
|
||||
3. type specific attributes
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
As it currently stands a BLK-aperture region will never have a
|
||||
"nfit/spa_index" attribute, but neither will a non-NFIT PMEM region. A
|
||||
BLK region with a "mappings" value of 0 is, as mentioned above, a DIMM
|
||||
that does not allow I/O. A PMEM region with a "mappings" value of zero
|
||||
is a simple system-physical-address range.
|
||||
|
||||
|
||||
LIBNVDIMM/LIBNDCTL: Namespace
|
||||
-----------------------------
|
||||
|
||||
A REGION, after resolving DPA aliasing and LABEL specified boundaries,
|
||||
surfaces one or more "namespace" devices. The arrival of a "namespace"
|
||||
device currently triggers either the nd_blk or nd_pmem driver to load
|
||||
and register a disk/block device.
|
||||
A REGION, after resolving DPA aliasing and LABEL specified boundaries, surfaces
|
||||
one or more "namespace" devices. The arrival of a "namespace" device currently
|
||||
triggers the nd_pmem driver to load and register a disk/block device.
|
||||
|
||||
LIBNVDIMM: namespace
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Here is a sample layout from the three major types of NAMESPACE where
|
||||
namespace0.0 represents DIMM-info-backed PMEM (note that it has a 'uuid'
|
||||
attribute), namespace2.0 represents a BLK namespace (note it has a
|
||||
'sector_size' attribute) that, and namespace6.0 represents an anonymous
|
||||
PMEM namespace (note that has no 'uuid' attribute due to not support a
|
||||
LABEL)::
|
||||
Here is a sample layout from the 2 major types of NAMESPACE where namespace0.0
|
||||
represents DIMM-info-backed PMEM (note that it has a 'uuid' attribute), and
|
||||
namespace1.0 represents an anonymous PMEM namespace (note that has no 'uuid'
|
||||
attribute due to not support a LABEL)
|
||||
|
||||
::
|
||||
|
||||
/sys/devices/platform/nfit_test.0/ndbus0/region0/namespace0.0
|
||||
|-- alt_name
|
||||
@ -691,20 +482,7 @@ LABEL)::
|
||||
|-- type
|
||||
|-- uevent
|
||||
`-- uuid
|
||||
/sys/devices/platform/nfit_test.0/ndbus0/region2/namespace2.0
|
||||
|-- alt_name
|
||||
|-- devtype
|
||||
|-- dpa_extents
|
||||
|-- force_raw
|
||||
|-- modalias
|
||||
|-- numa_node
|
||||
|-- sector_size
|
||||
|-- size
|
||||
|-- subsystem -> ../../../../../../bus/nd
|
||||
|-- type
|
||||
|-- uevent
|
||||
`-- uuid
|
||||
/sys/devices/platform/nfit_test.1/ndbus1/region6/namespace6.0
|
||||
/sys/devices/platform/nfit_test.1/ndbus1/region1/namespace1.0
|
||||
|-- block
|
||||
| `-- pmem0
|
||||
|-- devtype
|
||||
@ -786,9 +564,9 @@ Why the Term "namespace"?
|
||||
LIBNVDIMM/LIBNDCTL: Block Translation Table "btt"
|
||||
-------------------------------------------------
|
||||
|
||||
A BTT (design document: https://pmem.io/2014/09/23/btt.html) is a stacked
|
||||
block device driver that fronts either the whole block device or a
|
||||
partition of a block device emitted by either a PMEM or BLK NAMESPACE.
|
||||
A BTT (design document: https://pmem.io/2014/09/23/btt.html) is a
|
||||
personality driver for a namespace that fronts entire namespace as an
|
||||
'address abstraction'.
|
||||
|
||||
LIBNVDIMM: btt layout
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
@ -815,7 +593,9 @@ LIBNDCTL: btt creation example
|
||||
Similar to namespaces an idle BTT device is automatically created per
|
||||
region. Each time this "seed" btt device is configured and enabled a new
|
||||
seed is created. Creating a BTT configuration involves two steps of
|
||||
finding and idle BTT and assigning it to consume a PMEM or BLK namespace::
|
||||
finding and idle BTT and assigning it to consume a namespace.
|
||||
|
||||
::
|
||||
|
||||
static struct ndctl_btt *get_idle_btt(struct ndctl_region *region)
|
||||
{
|
||||
@ -863,25 +643,15 @@ For the given example above, here is the view of the objects as seen by the
|
||||
LIBNDCTL API::
|
||||
|
||||
+---+
|
||||
|CTX| +---------+ +--------------+ +---------------+
|
||||
+-+-+ +-> REGION0 +---> NAMESPACE0.0 +--> PMEM8 "pm0.0" |
|
||||
| | +---------+ +--------------+ +---------------+
|
||||
+-------+ | | +---------+ +--------------+ +---------------+
|
||||
| DIMM0 <-+ | +-> REGION1 +---> NAMESPACE1.0 +--> PMEM6 "pm1.0" |
|
||||
+-------+ | | | +---------+ +--------------+ +---------------+
|
||||
|CTX|
|
||||
+-+-+
|
||||
|
|
||||
+-------+ |
|
||||
| DIMM0 <-+ | +---------+ +--------------+ +---------------+
|
||||
+-------+ | | +-> REGION0 +---> NAMESPACE0.0 +--> PMEM8 "pm0.0" |
|
||||
| DIMM1 <-+ +-v--+ | +---------+ +--------------+ +---------------+
|
||||
+-------+ +-+BUS0+---> REGION2 +-+-> NAMESPACE2.0 +--> ND6 "blk2.0" |
|
||||
| DIMM2 <-+ +----+ | +---------+ | +--------------+ +----------------------+
|
||||
+-------+ | | +-> NAMESPACE2.1 +--> ND5 "blk2.1" | BTT2 |
|
||||
| DIMM3 <-+ | +--------------+ +----------------------+
|
||||
+-------+ | +---------+ +--------------+ +---------------+
|
||||
+-> REGION3 +-+-> NAMESPACE3.0 +--> ND4 "blk3.0" |
|
||||
| +---------+ | +--------------+ +----------------------+
|
||||
| +-> NAMESPACE3.1 +--> ND3 "blk3.1" | BTT1 |
|
||||
| +--------------+ +----------------------+
|
||||
| +---------+ +--------------+ +---------------+
|
||||
+-> REGION4 +---> NAMESPACE4.0 +--> ND2 "blk4.0" |
|
||||
| +---------+ +--------------+ +---------------+
|
||||
| +---------+ +--------------+ +----------------------+
|
||||
+-> REGION5 +---> NAMESPACE5.0 +--> ND1 "blk5.0" | BTT0 |
|
||||
+---------+ +--------------+ +---------------+------+
|
||||
+-------+ +-+BUS0+-| +---------+ +--------------+ +----------------------+
|
||||
| DIMM2 <-+ +----+ +-> REGION1 +---> NAMESPACE1.0 +--> PMEM6 "pm1.0" | BTT1 |
|
||||
+-------+ | | +---------+ +--------------+ +---------------+------+
|
||||
| DIMM3 <-+
|
||||
+-------+
|
||||
|
||||
@ -113,6 +113,16 @@ to: return warning/error, stop working or panic.
|
||||
See Section 3. for an example of driver implementing this
|
||||
callback, or Section 2.4 for further documentation on this API
|
||||
|
||||
Registration of EM using DT
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
The EM can also be registered using OPP framework and information in DT
|
||||
"operating-points-v2". Each OPP entry in DT can be extended with a property
|
||||
"opp-microwatt" containing micro-Watts power value. This OPP DT property
|
||||
allows a platform to register EM power values which are reflecting total power
|
||||
(static + dynamic). These power values might be coming directly from
|
||||
experiments and measurements.
|
||||
|
||||
Registration of 'simple' EM
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
||||
23
MAINTAINERS
23
MAINTAINERS
@ -5880,7 +5880,7 @@ F: include/linux/dma-map-ops.h
|
||||
F: kernel/dma/
|
||||
|
||||
DMA MAPPING BENCHMARK
|
||||
M: Barry Song <song.bao.hua@hisilicon.com>
|
||||
M: Xiang Chen <chenxiang66@hisilicon.com>
|
||||
L: iommu@lists.linux-foundation.org
|
||||
F: kernel/dma/map_benchmark.c
|
||||
F: tools/testing/selftests/dma/
|
||||
@ -10086,6 +10086,7 @@ INTEL UNCORE FREQUENCY CONTROL
|
||||
M: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst
|
||||
F: drivers/platform/x86/intel/uncore-frequency/
|
||||
|
||||
INTEL VENDOR SPECIFIC EXTENDED CAPABILITIES DRIVER
|
||||
@ -11127,17 +11128,6 @@ F: drivers/ata/
|
||||
F: include/linux/ata.h
|
||||
F: include/linux/libata.h
|
||||
|
||||
LIBNVDIMM BLK: MMIO-APERTURE DRIVER
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
M: Vishal Verma <vishal.l.verma@intel.com>
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
L: nvdimm@lists.linux.dev
|
||||
S: Supported
|
||||
Q: https://patchwork.kernel.org/project/linux-nvdimm/list/
|
||||
P: Documentation/nvdimm/maintainer-entry-profile.rst
|
||||
F: drivers/nvdimm/blk.c
|
||||
F: drivers/nvdimm/region_devs.c
|
||||
|
||||
LIBNVDIMM BTT: BLOCK TRANSLATION TABLE
|
||||
M: Vishal Verma <vishal.l.verma@intel.com>
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
@ -15937,7 +15927,6 @@ F: arch/*/ptrace*.c
|
||||
F: include/asm-generic/syscall.h
|
||||
F: include/linux/ptrace.h
|
||||
F: include/linux/regset.h
|
||||
F: include/linux/tracehook.h
|
||||
F: include/uapi/linux/ptrace.h
|
||||
F: include/uapi/linux/ptrace.h
|
||||
F: kernel/ptrace.c
|
||||
@ -16257,14 +16246,15 @@ M: Niklas Cassel <nks@flawful.org>
|
||||
L: linux-pm@vger.kernel.org
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
|
||||
F: Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
|
||||
F: drivers/soc/qcom/cpr.c
|
||||
|
||||
QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
|
||||
M: Ilia Lin <ilia.lin@kernel.org>
|
||||
L: linux-pm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
|
||||
F: Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
|
||||
F: Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
|
||||
F: drivers/cpufreq/qcom-cpufreq-nvmem.c
|
||||
|
||||
QUALCOMM CRYPTO DRIVERS
|
||||
@ -16297,8 +16287,9 @@ F: drivers/misc/fastrpc.c
|
||||
F: include/uapi/misc/fastrpc.h
|
||||
|
||||
QUALCOMM HEXAGON ARCHITECTURE
|
||||
M: Brian Cain <bcain@codeaurora.org>
|
||||
M: Brian Cain <bcain@quicinc.com>
|
||||
L: linux-hexagon@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bcain/linux.git
|
||||
S: Supported
|
||||
F: arch/hexagon/
|
||||
|
||||
|
||||
@ -217,9 +217,8 @@ config TRACE_IRQFLAGS_SUPPORT
|
||||
# asm/syscall.h supplying asm-generic/syscall.h interface
|
||||
# linux/regset.h user_regset interfaces
|
||||
# CORE_DUMP_USE_REGSET #define'd in linux/elf.h
|
||||
# TIF_SYSCALL_TRACE calls tracehook_report_syscall_{entry,exit}
|
||||
# TIF_NOTIFY_RESUME calls tracehook_notify_resume()
|
||||
# signal delivery calls tracehook_signal_handler()
|
||||
# TIF_SYSCALL_TRACE calls ptrace_report_syscall_{entry,exit}
|
||||
# TIF_NOTIFY_RESUME calls resume_user_mode_work()
|
||||
#
|
||||
config HAVE_ARCH_TRACEHOOK
|
||||
bool
|
||||
|
||||
@ -43,17 +43,18 @@ alpha_fd_dma_setup(char *addr, unsigned long size, int mode, int io)
|
||||
static int prev_dir;
|
||||
int dir;
|
||||
|
||||
dir = (mode != DMA_MODE_READ) ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE;
|
||||
dir = (mode != DMA_MODE_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
|
||||
|
||||
if (bus_addr
|
||||
&& (addr != prev_addr || size != prev_size || dir != prev_dir)) {
|
||||
/* different from last time -- unmap prev */
|
||||
pci_unmap_single(isa_bridge, bus_addr, prev_size, prev_dir);
|
||||
dma_unmap_single(&isa_bridge->dev, bus_addr, prev_size,
|
||||
prev_dir);
|
||||
bus_addr = 0;
|
||||
}
|
||||
|
||||
if (!bus_addr) /* need to map it */
|
||||
bus_addr = pci_map_single(isa_bridge, addr, size, dir);
|
||||
bus_addr = dma_map_single(&isa_bridge->dev, addr, size, dir);
|
||||
|
||||
/* remember this one as prev */
|
||||
prev_addr = addr;
|
||||
|
||||
@ -333,7 +333,7 @@ static dma_addr_t alpha_pci_map_page(struct device *dev, struct page *page,
|
||||
struct pci_dev *pdev = alpha_gendev_to_pci(dev);
|
||||
int dac_allowed;
|
||||
|
||||
BUG_ON(dir == PCI_DMA_NONE);
|
||||
BUG_ON(dir == DMA_NONE);
|
||||
|
||||
dac_allowed = pdev ? pci_dac_dma_supported(pdev, pdev->dma_mask) : 0;
|
||||
return pci_map_single_1(pdev, (char *)page_address(page) + offset,
|
||||
@ -356,7 +356,7 @@ static void alpha_pci_unmap_page(struct device *dev, dma_addr_t dma_addr,
|
||||
struct pci_iommu_arena *arena;
|
||||
long dma_ofs, npages;
|
||||
|
||||
BUG_ON(dir == PCI_DMA_NONE);
|
||||
BUG_ON(dir == DMA_NONE);
|
||||
|
||||
if (dma_addr >= __direct_map_base
|
||||
&& dma_addr < __direct_map_base + __direct_map_size) {
|
||||
@ -460,7 +460,7 @@ static void alpha_pci_free_coherent(struct device *dev, size_t size,
|
||||
unsigned long attrs)
|
||||
{
|
||||
struct pci_dev *pdev = alpha_gendev_to_pci(dev);
|
||||
pci_unmap_single(pdev, dma_addr, size, PCI_DMA_BIDIRECTIONAL);
|
||||
dma_unmap_single(&pdev->dev, dma_addr, size, DMA_BIDIRECTIONAL);
|
||||
free_pages((unsigned long)cpu_addr, get_order(size));
|
||||
|
||||
DBGA2("pci_free_consistent: [%llx,%zx] from %ps\n",
|
||||
@ -639,7 +639,7 @@ static int alpha_pci_map_sg(struct device *dev, struct scatterlist *sg,
|
||||
dma_addr_t max_dma;
|
||||
int dac_allowed;
|
||||
|
||||
BUG_ON(dir == PCI_DMA_NONE);
|
||||
BUG_ON(dir == DMA_NONE);
|
||||
|
||||
dac_allowed = dev ? pci_dac_dma_supported(pdev, pdev->dma_mask) : 0;
|
||||
|
||||
@ -702,7 +702,7 @@ static int alpha_pci_map_sg(struct device *dev, struct scatterlist *sg,
|
||||
/* Some allocation failed while mapping the scatterlist
|
||||
entries. Unmap them now. */
|
||||
if (out > start)
|
||||
pci_unmap_sg(pdev, start, out - start, dir);
|
||||
dma_unmap_sg(&pdev->dev, start, out - start, dir);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
@ -722,7 +722,7 @@ static void alpha_pci_unmap_sg(struct device *dev, struct scatterlist *sg,
|
||||
dma_addr_t max_dma;
|
||||
dma_addr_t fbeg, fend;
|
||||
|
||||
BUG_ON(dir == PCI_DMA_NONE);
|
||||
BUG_ON(dir == DMA_NONE);
|
||||
|
||||
if (! alpha_mv.mv_pci_tbi)
|
||||
return;
|
||||
|
||||
@ -15,7 +15,6 @@
|
||||
#include <linux/user.h>
|
||||
#include <linux/security.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/audit.h>
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
@ -323,7 +322,7 @@ asmlinkage unsigned long syscall_trace_enter(void)
|
||||
unsigned long ret = 0;
|
||||
struct pt_regs *regs = current_pt_regs();
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE) &&
|
||||
tracehook_report_syscall_entry(current_pt_regs()))
|
||||
ptrace_report_syscall_entry(current_pt_regs()))
|
||||
ret = -1UL;
|
||||
audit_syscall_entry(regs->r0, regs->r16, regs->r17, regs->r18, regs->r19);
|
||||
return ret ?: current_pt_regs()->r0;
|
||||
@ -334,5 +333,5 @@ syscall_trace_leave(void)
|
||||
{
|
||||
audit_syscall_exit(current_pt_regs());
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(current_pt_regs(), 0);
|
||||
ptrace_report_syscall_exit(current_pt_regs(), 0);
|
||||
}
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
#include <linux/binfmts.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/sigcontext.h>
|
||||
@ -531,7 +531,7 @@ do_work_pending(struct pt_regs *regs, unsigned long thread_flags,
|
||||
do_signal(regs, r0, r19);
|
||||
r0 = 0;
|
||||
} else {
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
}
|
||||
local_irq_disable();
|
||||
|
||||
@ -4,7 +4,6 @@
|
||||
*/
|
||||
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/sched/task_stack.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/unistd.h>
|
||||
@ -258,7 +257,7 @@ long arch_ptrace(struct task_struct *child, long request,
|
||||
|
||||
asmlinkage int syscall_trace_entry(struct pt_regs *regs)
|
||||
{
|
||||
if (tracehook_report_syscall_entry(regs))
|
||||
if (ptrace_report_syscall_entry(regs))
|
||||
return ULONG_MAX;
|
||||
|
||||
return regs->r8;
|
||||
@ -266,5 +265,5 @@ asmlinkage int syscall_trace_entry(struct pt_regs *regs)
|
||||
|
||||
asmlinkage void syscall_trace_exit(struct pt_regs *regs)
|
||||
{
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
}
|
||||
|
||||
@ -49,7 +49,7 @@
|
||||
#include <linux/personality.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <linux/sched/task_stack.h>
|
||||
|
||||
#include <asm/ucontext.h>
|
||||
@ -438,5 +438,5 @@ void do_notify_resume(struct pt_regs *regs)
|
||||
* user mode
|
||||
*/
|
||||
if (test_thread_flag(TIF_NOTIFY_RESUME))
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
@ -49,7 +49,7 @@ config ARM
|
||||
select DMA_DECLARE_COHERENT
|
||||
select DMA_GLOBAL_POOL if !MMU
|
||||
select DMA_OPS
|
||||
select DMA_REMAP if MMU
|
||||
select DMA_NONCOHERENT_MMAP if MMU
|
||||
select EDAC_SUPPORT
|
||||
select EDAC_ATOMIC_SCRUB
|
||||
select GENERIC_ALLOCATOR
|
||||
|
||||
@ -76,6 +76,22 @@ cpu0: cpu@0 {
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks IMX7D_CLK_ARM>;
|
||||
cpu-idle-states = <&cpu_sleep_wait>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
#cooling-cells = <2>;
|
||||
nvmem-cells = <&fuse_grade>;
|
||||
nvmem-cell-names = "speed_grade";
|
||||
};
|
||||
};
|
||||
|
||||
cpu0_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-792000000 {
|
||||
opp-hz = /bits/ 64 <792000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-supported-hw = <0xf>, <0xf>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -22,7 +22,6 @@
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/audit.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/unistd.h>
|
||||
|
||||
#include <asm/syscall.h>
|
||||
@ -831,8 +830,7 @@ enum ptrace_syscall_dir {
|
||||
PTRACE_SYSCALL_EXIT,
|
||||
};
|
||||
|
||||
static void tracehook_report_syscall(struct pt_regs *regs,
|
||||
enum ptrace_syscall_dir dir)
|
||||
static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir)
|
||||
{
|
||||
unsigned long ip;
|
||||
|
||||
@ -844,8 +842,8 @@ static void tracehook_report_syscall(struct pt_regs *regs,
|
||||
regs->ARM_ip = dir;
|
||||
|
||||
if (dir == PTRACE_SYSCALL_EXIT)
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
else if (tracehook_report_syscall_entry(regs))
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
else if (ptrace_report_syscall_entry(regs))
|
||||
current_thread_info()->abi_syscall = -1;
|
||||
|
||||
regs->ARM_ip = ip;
|
||||
@ -856,7 +854,7 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs)
|
||||
int scno;
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall(regs, PTRACE_SYSCALL_ENTER);
|
||||
report_syscall(regs, PTRACE_SYSCALL_ENTER);
|
||||
|
||||
/* Do seccomp after ptrace; syscall may have changed. */
|
||||
#ifdef CONFIG_HAVE_ARCH_SECCOMP_FILTER
|
||||
@ -897,5 +895,5 @@ asmlinkage void syscall_trace_exit(struct pt_regs *regs)
|
||||
trace_sys_exit(regs, regs_return_value(regs));
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall(regs, PTRACE_SYSCALL_EXIT);
|
||||
report_syscall(regs, PTRACE_SYSCALL_EXIT);
|
||||
}
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
#include <linux/signal.h>
|
||||
#include <linux/personality.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <linux/uprobes.h>
|
||||
#include <linux/syscalls.h>
|
||||
|
||||
@ -627,7 +627,7 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
|
||||
} else if (thread_flags & _TIF_UPROBE) {
|
||||
uprobe_notify_resume(regs);
|
||||
} else {
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
}
|
||||
local_irq_disable();
|
||||
|
||||
@ -27,7 +27,6 @@
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/elf.h>
|
||||
|
||||
#include <asm/compat.h>
|
||||
@ -1792,8 +1791,7 @@ enum ptrace_syscall_dir {
|
||||
PTRACE_SYSCALL_EXIT,
|
||||
};
|
||||
|
||||
static void tracehook_report_syscall(struct pt_regs *regs,
|
||||
enum ptrace_syscall_dir dir)
|
||||
static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir)
|
||||
{
|
||||
int regno;
|
||||
unsigned long saved_reg;
|
||||
@ -1819,11 +1817,11 @@ static void tracehook_report_syscall(struct pt_regs *regs,
|
||||
regs->regs[regno] = dir;
|
||||
|
||||
if (dir == PTRACE_SYSCALL_ENTER) {
|
||||
if (tracehook_report_syscall_entry(regs))
|
||||
if (ptrace_report_syscall_entry(regs))
|
||||
forget_syscall(regs);
|
||||
regs->regs[regno] = saved_reg;
|
||||
} else if (!test_thread_flag(TIF_SINGLESTEP)) {
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
regs->regs[regno] = saved_reg;
|
||||
} else {
|
||||
regs->regs[regno] = saved_reg;
|
||||
@ -1833,7 +1831,7 @@ static void tracehook_report_syscall(struct pt_regs *regs,
|
||||
* tracer modifications to the registers may have rewound the
|
||||
* state machine.
|
||||
*/
|
||||
tracehook_report_syscall_exit(regs, 1);
|
||||
ptrace_report_syscall_exit(regs, 1);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1842,7 +1840,7 @@ int syscall_trace_enter(struct pt_regs *regs)
|
||||
unsigned long flags = read_thread_flags();
|
||||
|
||||
if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) {
|
||||
tracehook_report_syscall(regs, PTRACE_SYSCALL_ENTER);
|
||||
report_syscall(regs, PTRACE_SYSCALL_ENTER);
|
||||
if (flags & _TIF_SYSCALL_EMU)
|
||||
return NO_SYSCALL;
|
||||
}
|
||||
@ -1870,7 +1868,7 @@ void syscall_trace_exit(struct pt_regs *regs)
|
||||
trace_sys_exit(regs, syscall_get_return_value(current, regs));
|
||||
|
||||
if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP))
|
||||
tracehook_report_syscall(regs, PTRACE_SYSCALL_EXIT);
|
||||
report_syscall(regs, PTRACE_SYSCALL_EXIT);
|
||||
|
||||
rseq_syscall(regs);
|
||||
}
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <linux/ratelimit.h>
|
||||
#include <linux/syscalls.h>
|
||||
|
||||
@ -942,7 +942,7 @@ void do_notify_resume(struct pt_regs *regs, unsigned long thread_flags)
|
||||
do_signal(regs);
|
||||
|
||||
if (thread_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
|
||||
if (thread_flags & _TIF_FOREIGN_FPSTATE)
|
||||
fpsimd_restore_current_state();
|
||||
|
||||
@ -12,7 +12,6 @@
|
||||
#include <linux/sched/task_stack.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/user.h>
|
||||
|
||||
@ -321,7 +320,7 @@ long arch_ptrace(struct task_struct *child, long request,
|
||||
asmlinkage int syscall_trace_enter(struct pt_regs *regs)
|
||||
{
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
if (tracehook_report_syscall_entry(regs))
|
||||
if (ptrace_report_syscall_entry(regs))
|
||||
return -1;
|
||||
|
||||
if (secure_computing() == -1)
|
||||
@ -339,7 +338,7 @@ asmlinkage void syscall_trace_exit(struct pt_regs *regs)
|
||||
audit_syscall_exit(regs);
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
|
||||
trace_sys_exit(regs, syscall_get_return_value(current, regs));
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
#include <linux/signal.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <asm/traps.h>
|
||||
#include <asm/ucontext.h>
|
||||
@ -265,5 +265,5 @@ asmlinkage void do_notify_resume(struct pt_regs *regs,
|
||||
do_signal(regs);
|
||||
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
@ -12,7 +12,6 @@
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/audit.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/elf.h>
|
||||
|
||||
@ -174,7 +173,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
|
||||
long ret = 0;
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE) &&
|
||||
tracehook_report_syscall_entry(regs))
|
||||
ptrace_report_syscall_entry(regs))
|
||||
/*
|
||||
* Tracing decided this syscall should not happen.
|
||||
* We'll return a bogus call number to get an ENOSYS
|
||||
@ -196,5 +195,5 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
|
||||
|
||||
step = test_thread_flag(TIF_SINGLESTEP);
|
||||
if (step || test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, step);
|
||||
ptrace_report_syscall_exit(regs, step);
|
||||
}
|
||||
|
||||
@ -39,7 +39,7 @@
|
||||
#include <linux/personality.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/binfmts.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <linux/uaccess.h>
|
||||
@ -283,5 +283,5 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags)
|
||||
do_signal(regs);
|
||||
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
#include <linux/tick.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
/*
|
||||
* Program thread launch. Often defined as a macro in processor.h,
|
||||
@ -177,7 +177,7 @@ int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
|
||||
}
|
||||
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME) {
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
@ -7,7 +7,6 @@
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/sched/task_stack.h>
|
||||
|
||||
#include <asm/registers.h>
|
||||
|
||||
@ -14,7 +14,7 @@
|
||||
#include <linux/kdebug.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/vm_fault.h>
|
||||
#include <asm/syscall.h>
|
||||
@ -348,7 +348,7 @@ void do_trap0(struct pt_regs *regs)
|
||||
|
||||
/* allow strace to catch syscall args */
|
||||
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACE) &&
|
||||
tracehook_report_syscall_entry(regs)))
|
||||
ptrace_report_syscall_entry(regs)))
|
||||
return; /* return -ENOSYS somewhere? */
|
||||
|
||||
/* Interrupts should be re-enabled for syscall processing */
|
||||
@ -386,7 +386,7 @@ void do_trap0(struct pt_regs *regs)
|
||||
|
||||
/* allow strace to get the syscall return state */
|
||||
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACE)))
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
|
||||
break;
|
||||
case TRAP_DEBUG:
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kdebug.h>
|
||||
#include <linux/utsname.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <linux/rcupdate.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
@ -179,7 +179,7 @@ do_notify_resume_user(sigset_t *unused, struct sigscratch *scr, long in_syscall)
|
||||
|
||||
if (test_thread_flag(TIF_NOTIFY_RESUME)) {
|
||||
local_irq_enable(); /* force interrupt enable */
|
||||
tracehook_notify_resume(&scr->pt);
|
||||
resume_user_mode_work(&scr->pt);
|
||||
}
|
||||
|
||||
/* copy user rbs to kernel rbs */
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
#include <linux/signal.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/elf.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/ptrace_offsets.h>
|
||||
@ -1217,7 +1217,7 @@ syscall_trace_enter (long arg0, long arg1, long arg2, long arg3,
|
||||
struct pt_regs regs)
|
||||
{
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
if (tracehook_report_syscall_entry(®s))
|
||||
if (ptrace_report_syscall_entry(®s))
|
||||
return -ENOSYS;
|
||||
|
||||
/* copy user rbs to kernel rbs */
|
||||
@ -1243,7 +1243,7 @@ syscall_trace_leave (long arg0, long arg1, long arg2, long arg3,
|
||||
|
||||
step = test_thread_flag(TIF_SINGLESTEP);
|
||||
if (step || test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(®s, step);
|
||||
ptrace_report_syscall_exit(®s, step);
|
||||
|
||||
/* copy user rbs to kernel rbs */
|
||||
if (test_thread_flag(TIF_RESTORE_RSE))
|
||||
|
||||
@ -12,7 +12,6 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
@ -19,7 +19,6 @@
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/tracehook.h>
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/page.h>
|
||||
@ -282,13 +281,13 @@ asmlinkage int syscall_trace_enter(void)
|
||||
int ret = 0;
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
ret = tracehook_report_syscall_entry(task_pt_regs(current));
|
||||
ret = ptrace_report_syscall_entry(task_pt_regs(current));
|
||||
return ret;
|
||||
}
|
||||
|
||||
asmlinkage void syscall_trace_leave(void)
|
||||
{
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(task_pt_regs(current), 0);
|
||||
ptrace_report_syscall_exit(task_pt_regs(current), 0);
|
||||
}
|
||||
#endif /* CONFIG_COLDFIRE */
|
||||
|
||||
@ -43,7 +43,7 @@
|
||||
#include <linux/tty.h>
|
||||
#include <linux/binfmts.h>
|
||||
#include <linux/extable.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <linux/uaccess.h>
|
||||
@ -1109,5 +1109,5 @@ void do_notify_resume(struct pt_regs *regs)
|
||||
do_signal(regs);
|
||||
|
||||
if (test_thread_flag(TIF_NOTIFY_RESUME))
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
@ -61,10 +61,6 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
|
||||
extern void pcibios_resource_survey(void);
|
||||
|
||||
struct file;
|
||||
extern pgprot_t pci_phys_mem_access_prot(struct file *file,
|
||||
unsigned long pfn,
|
||||
unsigned long size,
|
||||
pgprot_t prot);
|
||||
|
||||
/* This part of code was originally in xilinx-pci.h */
|
||||
#ifdef CONFIG_PCI_XILINX
|
||||
|
||||
@ -33,7 +33,6 @@
|
||||
#include <linux/elf.h>
|
||||
#include <linux/audit.h>
|
||||
#include <linux/seccomp.h>
|
||||
#include <linux/tracehook.h>
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <asm/processor.h>
|
||||
@ -140,7 +139,7 @@ asmlinkage unsigned long do_syscall_trace_enter(struct pt_regs *regs)
|
||||
secure_computing_strict(regs->r12);
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE) &&
|
||||
tracehook_report_syscall_entry(regs))
|
||||
ptrace_report_syscall_entry(regs))
|
||||
/*
|
||||
* Tracing decided this syscall should not happen.
|
||||
* We'll return a bogus call number to get an ENOSYS
|
||||
@ -161,7 +160,7 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
|
||||
|
||||
step = test_thread_flag(TIF_SINGLESTEP);
|
||||
if (step || test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, step);
|
||||
ptrace_report_syscall_exit(regs, step);
|
||||
}
|
||||
|
||||
void ptrace_disable(struct task_struct *child)
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
*
|
||||
* 1997-11-28 Modified for POSIX.1b signals by Richard Henderson
|
||||
*
|
||||
* This file was was derived from the sh version, arch/sh/kernel/signal.c
|
||||
* This file was derived from the sh version, arch/sh/kernel/signal.c
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General
|
||||
* Public License. See the file COPYING in the main directory of this
|
||||
@ -31,7 +31,7 @@
|
||||
#include <linux/personality.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <asm/entry.h>
|
||||
#include <asm/ucontext.h>
|
||||
#include <linux/uaccess.h>
|
||||
@ -311,5 +311,5 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, int in_syscall)
|
||||
do_signal(regs, in_syscall);
|
||||
|
||||
if (test_thread_flag(TIF_NOTIFY_RESUME))
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
@ -165,55 +165,6 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This one is used by /dev/mem and fbdev who have no clue about the
|
||||
* PCI device, it tries to find the PCI device first and calls the
|
||||
* above routine
|
||||
*/
|
||||
pgprot_t pci_phys_mem_access_prot(struct file *file,
|
||||
unsigned long pfn,
|
||||
unsigned long size,
|
||||
pgprot_t prot)
|
||||
{
|
||||
struct pci_dev *pdev = NULL;
|
||||
struct resource *found = NULL;
|
||||
resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
|
||||
int i;
|
||||
|
||||
if (page_is_ram(pfn))
|
||||
return prot;
|
||||
|
||||
prot = pgprot_noncached(prot);
|
||||
for_each_pci_dev(pdev) {
|
||||
for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
|
||||
struct resource *rp = &pdev->resource[i];
|
||||
int flags = rp->flags;
|
||||
|
||||
/* Active and same type? */
|
||||
if ((flags & IORESOURCE_MEM) == 0)
|
||||
continue;
|
||||
/* In the range of this resource? */
|
||||
if (offset < (rp->start & PAGE_MASK) ||
|
||||
offset > rp->end)
|
||||
continue;
|
||||
found = rp;
|
||||
break;
|
||||
}
|
||||
if (found)
|
||||
break;
|
||||
}
|
||||
if (found) {
|
||||
if (found->flags & IORESOURCE_PREFETCH)
|
||||
prot = pgprot_noncached_wc(prot);
|
||||
pci_dev_put(pdev);
|
||||
}
|
||||
|
||||
pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
|
||||
(unsigned long long)offset, pgprot_val(prot));
|
||||
|
||||
return prot;
|
||||
}
|
||||
|
||||
/* This provides legacy IO read access on a bus */
|
||||
int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
|
||||
{
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \
|
||||
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)
|
||||
|
||||
static struct of_device_id xilinx_pci_match[] = {
|
||||
static const struct of_device_id xilinx_pci_match[] = {
|
||||
{ .compatible = "xlnx,plbv46-pci-1.03.a", },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -27,7 +27,6 @@
|
||||
#include <linux/smp.h>
|
||||
#include <linux/security.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/audit.h>
|
||||
#include <linux/seccomp.h>
|
||||
#include <linux/ftrace.h>
|
||||
@ -1317,7 +1316,7 @@ asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
|
||||
current_thread_info()->syscall = syscall;
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE)) {
|
||||
if (tracehook_report_syscall_entry(regs))
|
||||
if (ptrace_report_syscall_entry(regs))
|
||||
return -1;
|
||||
syscall = current_thread_info()->syscall;
|
||||
}
|
||||
@ -1376,7 +1375,7 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
|
||||
trace_sys_exit(regs, regs_return_value(regs));
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
|
||||
user_enter();
|
||||
}
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <asm/abi.h>
|
||||
#include <asm/asm.h>
|
||||
@ -915,7 +915,7 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
|
||||
do_signal(regs);
|
||||
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
|
||||
user_enter();
|
||||
}
|
||||
|
||||
@ -15,7 +15,6 @@
|
||||
#include <linux/regset.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/sched/task_stack.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/user.h>
|
||||
|
||||
@ -134,7 +133,7 @@ asmlinkage int do_syscall_trace_enter(void)
|
||||
int ret = 0;
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
ret = tracehook_report_syscall_entry(task_pt_regs(current));
|
||||
ret = ptrace_report_syscall_entry(task_pt_regs(current));
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -142,5 +141,5 @@ asmlinkage int do_syscall_trace_enter(void)
|
||||
asmlinkage void do_syscall_trace_exit(void)
|
||||
{
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(task_pt_regs(current), 0);
|
||||
ptrace_report_syscall_exit(task_pt_regs(current), 0);
|
||||
}
|
||||
|
||||
@ -15,7 +15,7 @@
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/personality.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <asm/ucontext.h>
|
||||
#include <asm/cacheflush.h>
|
||||
@ -321,7 +321,7 @@ asmlinkage int do_notify_resume(struct pt_regs *regs)
|
||||
return restart;
|
||||
}
|
||||
} else if (test_thread_flag(TIF_NOTIFY_RESUME))
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -22,7 +22,6 @@
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/audit.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/elf.h>
|
||||
|
||||
#include <asm/thread_info.h>
|
||||
@ -159,7 +158,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
|
||||
long ret = 0;
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE) &&
|
||||
tracehook_report_syscall_entry(regs))
|
||||
ptrace_report_syscall_entry(regs))
|
||||
/*
|
||||
* Tracing decided this syscall should not happen.
|
||||
* We'll return a bogus call number to get an ENOSYS
|
||||
@ -181,5 +180,5 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
|
||||
|
||||
step = test_thread_flag(TIF_SINGLESTEP);
|
||||
if (step || test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, step);
|
||||
ptrace_report_syscall_exit(regs, step);
|
||||
}
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/syscall.h>
|
||||
@ -309,7 +309,7 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
|
||||
}
|
||||
syscall = 0;
|
||||
} else {
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
}
|
||||
local_irq_disable();
|
||||
|
||||
@ -15,7 +15,6 @@
|
||||
#include <linux/elf.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/personality.h>
|
||||
#include <linux/regset.h>
|
||||
@ -316,7 +315,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
||||
long do_syscall_trace_enter(struct pt_regs *regs)
|
||||
{
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE)) {
|
||||
int rc = tracehook_report_syscall_entry(regs);
|
||||
int rc = ptrace_report_syscall_entry(regs);
|
||||
|
||||
/*
|
||||
* As tracesys_next does not set %r28 to -ENOSYS
|
||||
@ -327,7 +326,7 @@ long do_syscall_trace_enter(struct pt_regs *regs)
|
||||
if (rc) {
|
||||
/*
|
||||
* A nonzero return code from
|
||||
* tracehook_report_syscall_entry() tells us
|
||||
* ptrace_report_syscall_entry() tells us
|
||||
* to prevent the syscall execution. Skip
|
||||
* the syscall call and the syscall restart handling.
|
||||
*
|
||||
@ -381,7 +380,7 @@ void do_syscall_trace_exit(struct pt_regs *regs)
|
||||
#endif
|
||||
|
||||
if (stepping || test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, stepping);
|
||||
ptrace_report_syscall_exit(regs, stepping);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
#include <linux/errno.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/compat.h>
|
||||
@ -585,5 +585,5 @@ void do_notify_resume(struct pt_regs *regs, long in_syscall)
|
||||
do_signal(regs, in_syscall);
|
||||
|
||||
if (test_thread_flag(TIF_NOTIFY_RESUME))
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
@ -48,6 +48,11 @@ struct dev_archdata {
|
||||
|
||||
struct pdev_archdata {
|
||||
u64 dma_mask;
|
||||
/*
|
||||
* Pointer to nvdimm_pmu structure, to handle the unregistering
|
||||
* of pmu device
|
||||
*/
|
||||
void *priv;
|
||||
};
|
||||
|
||||
#endif /* _ASM_POWERPC_DEVICE_H */
|
||||
|
||||
@ -16,7 +16,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/regset.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/audit.h>
|
||||
#include <linux/context_tracking.h>
|
||||
#include <linux/syscalls.h>
|
||||
@ -262,12 +262,12 @@ long do_syscall_trace_enter(struct pt_regs *regs)
|
||||
flags = read_thread_flags() & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE);
|
||||
|
||||
if (flags) {
|
||||
int rc = tracehook_report_syscall_entry(regs);
|
||||
int rc = ptrace_report_syscall_entry(regs);
|
||||
|
||||
if (unlikely(flags & _TIF_SYSCALL_EMU)) {
|
||||
/*
|
||||
* A nonzero return code from
|
||||
* tracehook_report_syscall_entry() tells us to prevent
|
||||
* ptrace_report_syscall_entry() tells us to prevent
|
||||
* the syscall execution, but we are not going to
|
||||
* execute it anyway.
|
||||
*
|
||||
@ -333,7 +333,7 @@ void do_syscall_trace_leave(struct pt_regs *regs)
|
||||
|
||||
step = test_thread_flag(TIF_SINGLESTEP);
|
||||
if (step || test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, step);
|
||||
ptrace_report_syscall_exit(regs, step);
|
||||
}
|
||||
|
||||
void __init pt_regs_check(void);
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
* this archive for more details.
|
||||
*/
|
||||
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/uprobes.h>
|
||||
#include <linux/key.h>
|
||||
@ -294,7 +294,7 @@ void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags)
|
||||
}
|
||||
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
static unsigned long get_tm_stackpointer(struct task_struct *tsk)
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include <asm/papr_pdsm.h>
|
||||
#include <asm/mce.h>
|
||||
#include <asm/unaligned.h>
|
||||
#include <linux/perf_event.h>
|
||||
|
||||
#define BIND_ANY_ADDR (~0ul)
|
||||
|
||||
@ -124,6 +125,8 @@ struct papr_scm_priv {
|
||||
/* The bits which needs to be overridden */
|
||||
u64 health_bitmap_inject_mask;
|
||||
|
||||
/* array to have event_code and stat_id mappings */
|
||||
char **nvdimm_events_map;
|
||||
};
|
||||
|
||||
static int papr_scm_pmem_flush(struct nd_region *nd_region,
|
||||
@ -344,6 +347,225 @@ static ssize_t drc_pmem_query_stats(struct papr_scm_priv *p,
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PERF_EVENTS
|
||||
#define to_nvdimm_pmu(_pmu) container_of(_pmu, struct nvdimm_pmu, pmu)
|
||||
|
||||
static int papr_scm_pmu_get_value(struct perf_event *event, struct device *dev, u64 *count)
|
||||
{
|
||||
struct papr_scm_perf_stat *stat;
|
||||
struct papr_scm_perf_stats *stats;
|
||||
struct papr_scm_priv *p = (struct papr_scm_priv *)dev->driver_data;
|
||||
int rc, size;
|
||||
|
||||
/* Allocate request buffer enough to hold single performance stat */
|
||||
size = sizeof(struct papr_scm_perf_stats) +
|
||||
sizeof(struct papr_scm_perf_stat);
|
||||
|
||||
if (!p || !p->nvdimm_events_map)
|
||||
return -EINVAL;
|
||||
|
||||
stats = kzalloc(size, GFP_KERNEL);
|
||||
if (!stats)
|
||||
return -ENOMEM;
|
||||
|
||||
stat = &stats->scm_statistic[0];
|
||||
memcpy(&stat->stat_id,
|
||||
p->nvdimm_events_map[event->attr.config],
|
||||
sizeof(stat->stat_id));
|
||||
stat->stat_val = 0;
|
||||
|
||||
rc = drc_pmem_query_stats(p, stats, 1);
|
||||
if (rc < 0) {
|
||||
kfree(stats);
|
||||
return rc;
|
||||
}
|
||||
|
||||
*count = be64_to_cpu(stat->stat_val);
|
||||
kfree(stats);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int papr_scm_pmu_event_init(struct perf_event *event)
|
||||
{
|
||||
struct nvdimm_pmu *nd_pmu = to_nvdimm_pmu(event->pmu);
|
||||
struct papr_scm_priv *p;
|
||||
|
||||
if (!nd_pmu)
|
||||
return -EINVAL;
|
||||
|
||||
/* test the event attr type for PMU enumeration */
|
||||
if (event->attr.type != event->pmu->type)
|
||||
return -ENOENT;
|
||||
|
||||
/* it does not support event sampling mode */
|
||||
if (is_sampling_event(event))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
/* no branch sampling */
|
||||
if (has_branch_stack(event))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
p = (struct papr_scm_priv *)nd_pmu->dev->driver_data;
|
||||
if (!p)
|
||||
return -EINVAL;
|
||||
|
||||
/* Invalid eventcode */
|
||||
if (event->attr.config == 0 || event->attr.config > 16)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int papr_scm_pmu_add(struct perf_event *event, int flags)
|
||||
{
|
||||
u64 count;
|
||||
int rc;
|
||||
struct nvdimm_pmu *nd_pmu = to_nvdimm_pmu(event->pmu);
|
||||
|
||||
if (!nd_pmu)
|
||||
return -EINVAL;
|
||||
|
||||
if (flags & PERF_EF_START) {
|
||||
rc = papr_scm_pmu_get_value(event, nd_pmu->dev, &count);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
local64_set(&event->hw.prev_count, count);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void papr_scm_pmu_read(struct perf_event *event)
|
||||
{
|
||||
u64 prev, now;
|
||||
int rc;
|
||||
struct nvdimm_pmu *nd_pmu = to_nvdimm_pmu(event->pmu);
|
||||
|
||||
if (!nd_pmu)
|
||||
return;
|
||||
|
||||
rc = papr_scm_pmu_get_value(event, nd_pmu->dev, &now);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
prev = local64_xchg(&event->hw.prev_count, now);
|
||||
local64_add(now - prev, &event->count);
|
||||
}
|
||||
|
||||
static void papr_scm_pmu_del(struct perf_event *event, int flags)
|
||||
{
|
||||
papr_scm_pmu_read(event);
|
||||
}
|
||||
|
||||
static int papr_scm_pmu_check_events(struct papr_scm_priv *p, struct nvdimm_pmu *nd_pmu)
|
||||
{
|
||||
struct papr_scm_perf_stat *stat;
|
||||
struct papr_scm_perf_stats *stats;
|
||||
char *statid;
|
||||
int index, rc, count;
|
||||
u32 available_events;
|
||||
|
||||
if (!p->stat_buffer_len)
|
||||
return -ENOENT;
|
||||
|
||||
available_events = (p->stat_buffer_len - sizeof(struct papr_scm_perf_stats))
|
||||
/ sizeof(struct papr_scm_perf_stat);
|
||||
|
||||
/* Allocate the buffer for phyp where stats are written */
|
||||
stats = kzalloc(p->stat_buffer_len, GFP_KERNEL);
|
||||
if (!stats) {
|
||||
rc = -ENOMEM;
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Allocate memory to nvdimm_event_map */
|
||||
p->nvdimm_events_map = kcalloc(available_events, sizeof(char *), GFP_KERNEL);
|
||||
if (!p->nvdimm_events_map) {
|
||||
rc = -ENOMEM;
|
||||
goto out_stats;
|
||||
}
|
||||
|
||||
/* Called to get list of events supported */
|
||||
rc = drc_pmem_query_stats(p, stats, 0);
|
||||
if (rc)
|
||||
goto out_nvdimm_events_map;
|
||||
|
||||
for (index = 0, stat = stats->scm_statistic, count = 0;
|
||||
index < available_events; index++, ++stat) {
|
||||
statid = kzalloc(strlen(stat->stat_id) + 1, GFP_KERNEL);
|
||||
if (!statid) {
|
||||
rc = -ENOMEM;
|
||||
goto out_nvdimm_events_map;
|
||||
}
|
||||
|
||||
strcpy(statid, stat->stat_id);
|
||||
p->nvdimm_events_map[count] = statid;
|
||||
count++;
|
||||
}
|
||||
p->nvdimm_events_map[count] = NULL;
|
||||
kfree(stats);
|
||||
return 0;
|
||||
|
||||
out_nvdimm_events_map:
|
||||
kfree(p->nvdimm_events_map);
|
||||
out_stats:
|
||||
kfree(stats);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void papr_scm_pmu_register(struct papr_scm_priv *p)
|
||||
{
|
||||
struct nvdimm_pmu *nd_pmu;
|
||||
int rc, nodeid;
|
||||
|
||||
nd_pmu = kzalloc(sizeof(*nd_pmu), GFP_KERNEL);
|
||||
if (!nd_pmu) {
|
||||
rc = -ENOMEM;
|
||||
goto pmu_err_print;
|
||||
}
|
||||
|
||||
rc = papr_scm_pmu_check_events(p, nd_pmu);
|
||||
if (rc)
|
||||
goto pmu_check_events_err;
|
||||
|
||||
nd_pmu->pmu.task_ctx_nr = perf_invalid_context;
|
||||
nd_pmu->pmu.name = nvdimm_name(p->nvdimm);
|
||||
nd_pmu->pmu.event_init = papr_scm_pmu_event_init;
|
||||
nd_pmu->pmu.read = papr_scm_pmu_read;
|
||||
nd_pmu->pmu.add = papr_scm_pmu_add;
|
||||
nd_pmu->pmu.del = papr_scm_pmu_del;
|
||||
|
||||
nd_pmu->pmu.capabilities = PERF_PMU_CAP_NO_INTERRUPT |
|
||||
PERF_PMU_CAP_NO_EXCLUDE;
|
||||
|
||||
/*updating the cpumask variable */
|
||||
nodeid = numa_map_to_online_node(dev_to_node(&p->pdev->dev));
|
||||
nd_pmu->arch_cpumask = *cpumask_of_node(nodeid);
|
||||
|
||||
rc = register_nvdimm_pmu(nd_pmu, p->pdev);
|
||||
if (rc)
|
||||
goto pmu_register_err;
|
||||
|
||||
/*
|
||||
* Set archdata.priv value to nvdimm_pmu structure, to handle the
|
||||
* unregistering of pmu device.
|
||||
*/
|
||||
p->pdev->archdata.priv = nd_pmu;
|
||||
return;
|
||||
|
||||
pmu_register_err:
|
||||
kfree(p->nvdimm_events_map);
|
||||
pmu_check_events_err:
|
||||
kfree(nd_pmu);
|
||||
pmu_err_print:
|
||||
dev_info(&p->pdev->dev, "nvdimm pmu didn't register rc=%d\n", rc);
|
||||
}
|
||||
|
||||
#else
|
||||
static void papr_scm_pmu_register(struct papr_scm_priv *p) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Issue hcall to retrieve dimm health info and populate papr_scm_priv with the
|
||||
* health information.
|
||||
@ -1320,6 +1542,7 @@ static int papr_scm_probe(struct platform_device *pdev)
|
||||
goto err2;
|
||||
|
||||
platform_set_drvdata(pdev, p);
|
||||
papr_scm_pmu_register(p);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -1338,6 +1561,12 @@ static int papr_scm_remove(struct platform_device *pdev)
|
||||
|
||||
nvdimm_bus_unregister(p->bus);
|
||||
drc_pmem_unbind(p);
|
||||
|
||||
if (pdev->archdata.priv)
|
||||
unregister_nvdimm_pmu(pdev->archdata.priv);
|
||||
|
||||
pdev->archdata.priv = NULL;
|
||||
kfree(p->nvdimm_events_map);
|
||||
kfree(p->bus_desc.provider_name);
|
||||
kfree(p);
|
||||
|
||||
|
||||
@ -17,7 +17,6 @@
|
||||
#include <linux/regset.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/sched/task_stack.h>
|
||||
#include <linux/tracehook.h>
|
||||
|
||||
#define CREATE_TRACE_POINTS
|
||||
#include <trace/events/syscalls.h>
|
||||
@ -241,7 +240,7 @@ long arch_ptrace(struct task_struct *child, long request,
|
||||
__visible int do_syscall_trace_enter(struct pt_regs *regs)
|
||||
{
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
if (tracehook_report_syscall_entry(regs))
|
||||
if (ptrace_report_syscall_entry(regs))
|
||||
return -1;
|
||||
|
||||
/*
|
||||
@ -266,7 +265,7 @@ __visible void do_syscall_trace_exit(struct pt_regs *regs)
|
||||
audit_syscall_exit(regs);
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
|
||||
#ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
#include <linux/signal.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#include <asm/ucontext.h>
|
||||
@ -319,5 +319,5 @@ asmlinkage __visible void do_notify_resume(struct pt_regs *regs,
|
||||
do_signal(regs);
|
||||
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
@ -5,7 +5,6 @@
|
||||
#include <linux/sched.h>
|
||||
#include <linux/audit.h>
|
||||
#include <linux/randomize_kstack.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/processor.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/timex.h>
|
||||
|
||||
@ -21,7 +21,6 @@
|
||||
#include <linux/signal.h>
|
||||
#include <linux/elf.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/seccomp.h>
|
||||
#include <linux/compat.h>
|
||||
#include <trace/syscall.h>
|
||||
|
||||
@ -25,7 +25,6 @@
|
||||
#include <linux/tty.h>
|
||||
#include <linux/personality.h>
|
||||
#include <linux/binfmts.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/syscalls.h>
|
||||
#include <linux/compat.h>
|
||||
#include <asm/ucontext.h>
|
||||
@ -453,7 +452,7 @@ static void handle_signal(struct ksignal *ksig, sigset_t *oldset,
|
||||
* stack-frames in one go after that.
|
||||
*/
|
||||
|
||||
void arch_do_signal_or_restart(struct pt_regs *regs, bool has_signal)
|
||||
void arch_do_signal_or_restart(struct pt_regs *regs)
|
||||
{
|
||||
struct ksignal ksig;
|
||||
sigset_t *oldset = sigmask_to_save();
|
||||
@ -466,7 +465,7 @@ void arch_do_signal_or_restart(struct pt_regs *regs, bool has_signal)
|
||||
current->thread.system_call =
|
||||
test_pt_regs_flag(regs, PIF_SYSCALL) ? regs->int_code : 0;
|
||||
|
||||
if (has_signal && get_signal(&ksig)) {
|
||||
if (get_signal(&ksig)) {
|
||||
/* Whee! Actually deliver the signal. */
|
||||
if (current->thread.system_call) {
|
||||
regs->int_code = current->thread.system_call;
|
||||
|
||||
@ -20,7 +20,6 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/audit.h>
|
||||
#include <linux/seccomp.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/elf.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
@ -456,7 +455,7 @@ long arch_ptrace(struct task_struct *child, long request,
|
||||
asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
|
||||
{
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE) &&
|
||||
tracehook_report_syscall_entry(regs)) {
|
||||
ptrace_report_syscall_entry(regs)) {
|
||||
regs->regs[0] = -ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
@ -484,5 +483,5 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
|
||||
|
||||
step = test_thread_flag(TIF_SINGLESTEP);
|
||||
if (step || test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, step);
|
||||
ptrace_report_syscall_exit(regs, step);
|
||||
}
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
#include <linux/personality.h>
|
||||
#include <linux/binfmts.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <asm/ucontext.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/cacheflush.h>
|
||||
@ -503,5 +503,5 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned int save_r0,
|
||||
do_signal(regs, save_r0);
|
||||
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
@ -309,7 +309,7 @@ arch_initcall(sparc_register_ioport);
|
||||
void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
if (dir != PCI_DMA_TODEVICE &&
|
||||
if (dir != DMA_TO_DEVICE &&
|
||||
sparc_cpu_model == sparc_leon &&
|
||||
!sparc_leon3_snooping_enabled())
|
||||
leon_flush_dcache_all();
|
||||
|
||||
@ -21,7 +21,6 @@
|
||||
#include <linux/signal.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/elf.h>
|
||||
#include <linux/tracehook.h>
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/cacheflush.h>
|
||||
@ -439,9 +438,9 @@ asmlinkage int syscall_trace(struct pt_regs *regs, int syscall_exit_p)
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE)) {
|
||||
if (syscall_exit_p)
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
else
|
||||
ret = tracehook_report_syscall_entry(regs);
|
||||
ret = ptrace_report_syscall_entry(regs);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
@ -25,7 +25,6 @@
|
||||
#include <linux/audit.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <trace/syscall.h>
|
||||
#include <linux/compat.h>
|
||||
#include <linux/elf.h>
|
||||
@ -1095,7 +1094,7 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs)
|
||||
user_exit();
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
ret = tracehook_report_syscall_entry(regs);
|
||||
ret = ptrace_report_syscall_entry(regs);
|
||||
|
||||
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
|
||||
trace_sys_enter(regs, regs->u_regs[UREG_G1]);
|
||||
@ -1118,7 +1117,7 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
|
||||
trace_sys_exit(regs, regs->u_regs[UREG_I0]);
|
||||
|
||||
if (test_thread_flag(TIF_SYSCALL_TRACE))
|
||||
tracehook_report_syscall_exit(regs, 0);
|
||||
ptrace_report_syscall_exit(regs, 0);
|
||||
|
||||
if (test_thread_flag(TIF_NOHZ))
|
||||
user_enter();
|
||||
|
||||
@ -20,7 +20,6 @@
|
||||
#include <linux/binfmts.h>
|
||||
#include <linux/compat.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/tracehook.h>
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
#include <linux/smp.h>
|
||||
#include <linux/binfmts.h> /* do_coredum */
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/ptrace.h>
|
||||
@ -524,7 +524,7 @@ void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0,
|
||||
if (thread_info_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL))
|
||||
do_signal(regs, orig_i0);
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
asmlinkage int do_sys_sigstack(struct sigstack __user *ssptr,
|
||||
|
||||
@ -15,7 +15,7 @@
|
||||
#include <linux/errno.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/tty.h>
|
||||
@ -552,7 +552,7 @@ void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0, unsigned long
|
||||
if (thread_info_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL))
|
||||
do_signal(regs, orig_i0);
|
||||
if (thread_info_flags & _TIF_NOTIFY_RESUME)
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
user_enter();
|
||||
}
|
||||
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/tick.h>
|
||||
#include <linux/threads.h>
|
||||
#include <linux/tracehook.h>
|
||||
#include <linux/resume_user_mode.h>
|
||||
#include <asm/current.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <linux/uaccess.h>
|
||||
@ -104,7 +104,7 @@ void interrupt_end(void)
|
||||
test_thread_flag(TIF_NOTIFY_SIGNAL))
|
||||
do_signal(regs);
|
||||
if (test_thread_flag(TIF_NOTIFY_RESUME))
|
||||
tracehook_notify_resume(regs);
|
||||
resume_user_mode_work(regs);
|
||||
}
|
||||
|
||||
int get_current_pid(void)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user