usb: dwc3: dwc3-msm-core: Switch to UTMI clk during host teardown
After moving the flush_work() call after the usb_phy_notify_disconnect() to address USB type C compliance issues (LFPS generated during host teardown): commit fb3c680116db ("usb: dwc3: dwc3-msm-core: Notify PHY disconnect before doing flush_work") During USB device PIPO, the notify PHY disconnect call to the QMP PHY will cause the PHY to be powered down. As part of the stop host mode routine, the DWC3 core has to be placed back into device/peripheral mode. Some parts of the device mode initialization sequence, such as the core soft reset, requires that the PIPE clk (or controller source clock) be active, otherwise the core soft reset will time out. To mitigate the side effect, temporarily switch to the UTMI as the controller clock source, so that the PIPE clock can be powered off without any consequences. Once the move to DWC3 gadget mode is complete, re-enable the PIPE clock as the controller source. (after flush_work() is complete). Change-Id: I59de803d737581c0037348498b8447f872adb62f Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
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@ -7012,7 +7012,12 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on)
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/*
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* Performing phy disconnect before flush work to
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* address TypeC certification--TD 4.7.4 failure.
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* In order to avoid any controller start/halt
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* sequences, switch to the UTMI as the clk source
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* as the notify_disconnect() callback to the QMP
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* PHY will power down the PIPE clock.
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*/
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dwc3_msm_switch_utmi(mdwc, true);
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if (mdwc->ss_phy->flags & PHY_HOST_MODE) {
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usb_phy_notify_disconnect(mdwc->ss_phy,
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USB_SPEED_SUPER);
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@ -7025,6 +7030,7 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on)
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if (dwc->dr_mode == USB_DR_MODE_OTG)
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flush_work(&dwc->drd_work);
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dwc3_msm_switch_utmi(mdwc, false);
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mdwc->hs_phy->flags &= ~PHY_HOST_MODE;
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usb_unregister_notify(&mdwc->host_nb);
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