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arm64: dts: mediatek: Add cpufreq nodes for MT8192

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[ Upstream commit 9d498cce9298a71e3896e2d1aee24a1a4c531d81 ]

Add the cpufreq nodes for MT8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230317061944.15434-1-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Stable-dep-of: a4366b5695c9 ("arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Allen-KH Cheng 2023-03-17 14:19:44 +08:00 committed by Greg Kroah-Hartman
parent 4e9f1a2367
commit 846c79d2a5
1 changed files with 14 additions and 0 deletions
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14
arch/arm64/boot/dts/mediatek/mt8192.dtsi
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@ -64,6 +64,7 @@ cpu0: cpu@0 {
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};
@ -75,6 +76,7 @@ cpu1: cpu@100 {
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};
@ -86,6 +88,7 @@ cpu2: cpu@200 {
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};
@ -97,6 +100,7 @@ cpu3: cpu@300 {
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <530>;
};
@ -108,6 +112,7 @@ cpu4: cpu@400 {
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
};
@ -119,6 +124,7 @@ cpu5: cpu@500 {
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
};
@ -130,6 +136,7 @@ cpu6: cpu@600 {
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
};
@ -141,6 +148,7 @@ cpu7: cpu@700 {
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
};
@ -257,6 +265,12 @@ soc {
compatible = "simple-bus";
ranges;
performance: performance-controller@11bc10 {
compatible = "mediatek,cpufreq-hw";
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
#performance-domain-cells = <1>;
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;