arm64: dts: qcom: sm8150: add i2c nodes
Tested on the OnePlus 7 Pro (including DMA). Signed-off-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20210321174522.123036-3-caleb@connolly.tech Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Caleb Connolly
Bjorn Andersson
parent
9cf3ebd16e
commit
81bee6953b
@ -588,6 +588,111 @@ qupv3_id_0: geniqup@8c0000 {
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#size-cells = <2>;
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ranges;
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status = "disabled";
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i2c0: i2c@880000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00880000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c0_default>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@884000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00884000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c1_default>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@888000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00888000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c2_default>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@88c000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x0088c000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c3_default>;
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@890000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00890000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c4_default>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c5: i2c@894000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00894000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c5_default>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c6: i2c@898000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00898000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c6_default>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c7: i2c@89c000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x0089c000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c7_default>;
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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qupv3_id_1: geniqup@ac0000 {
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@ -602,6 +707,58 @@ qupv3_id_1: geniqup@ac0000 {
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ranges;
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status = "disabled";
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i2c8: i2c@a80000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00a80000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c8_default>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c9: i2c@a84000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00a84000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c9_default>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c10: i2c@a88000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00a88000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c10_default>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c11: i2c@a8c000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00a8c000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c11_default>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart2: serial@a90000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x00a90000 0x0 0x4000>;
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@ -610,6 +767,32 @@ uart2: serial@a90000 {
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c12: i2c@a90000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00a90000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c12_default>;
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c16: i2c@94000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x0094000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c16_default>;
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interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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qupv3_id_2: geniqup@cc0000 {
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@ -624,6 +807,84 @@ qupv3_id_2: geniqup@cc0000 {
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#size-cells = <2>;
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ranges;
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status = "disabled";
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i2c17: i2c@c80000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00c80000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c17_default>;
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interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c18: i2c@c84000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00c84000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c18_default>;
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interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c19: i2c@c88000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00c88000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c19_default>;
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interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c13: i2c@c8c000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00c8c000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c13_default>;
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interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c14: i2c@c90000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00c90000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c14_default>;
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interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c15: i2c@c94000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00c94000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c15_default>;
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interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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config_noc: interconnect@1500000 {
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@ -947,6 +1208,266 @@ tlmm: pinctrl@3100000 {
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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qup_i2c0_default: qup-i2c0-default {
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mux {
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pins = "gpio0", "gpio1";
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function = "qup0";
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};
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config {
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pins = "gpio0", "gpio1";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c1_default: qup-i2c1-default {
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mux {
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pins = "gpio114", "gpio115";
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function = "qup1";
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};
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config {
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pins = "gpio114", "gpio115";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c2_default: qup-i2c2-default {
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mux {
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pins = "gpio126", "gpio127";
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function = "qup2";
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};
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config {
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pins = "gpio126", "gpio127";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c3_default: qup-i2c3-default {
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mux {
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pins = "gpio144", "gpio145";
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function = "qup3";
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};
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config {
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pins = "gpio144", "gpio145";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c4_default: qup-i2c4-default {
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mux {
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pins = "gpio51", "gpio52";
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function = "qup4";
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};
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config {
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pins = "gpio51", "gpio52";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c5_default: qup-i2c5-default {
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mux {
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pins = "gpio121", "gpio122";
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function = "qup5";
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};
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config {
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pins = "gpio121", "gpio122";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c6_default: qup-i2c6-default {
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mux {
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pins = "gpio6", "gpio7";
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function = "qup6";
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};
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config {
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pins = "gpio6", "gpio7";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c7_default: qup-i2c7-default {
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mux {
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pins = "gpio98", "gpio99";
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function = "qup7";
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};
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config {
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pins = "gpio98", "gpio99";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c8_default: qup-i2c8-default {
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mux {
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pins = "gpio88", "gpio89";
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function = "qup8";
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};
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config {
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pins = "gpio88", "gpio89";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c9_default: qup-i2c9-default {
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mux {
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pins = "gpio39", "gpio40";
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function = "qup9";
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};
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config {
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pins = "gpio39", "gpio40";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c10_default: qup-i2c10-default {
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mux {
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pins = "gpio9", "gpio10";
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function = "qup10";
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};
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config {
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pins = "gpio9", "gpio10";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c11_default: qup-i2c11-default {
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mux {
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pins = "gpio94", "gpio95";
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function = "qup11";
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};
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config {
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pins = "gpio94", "gpio95";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c12_default: qup-i2c12-default {
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mux {
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pins = "gpio83", "gpio84";
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function = "qup12";
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};
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config {
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pins = "gpio83", "gpio84";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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qup_i2c13_default: qup-i2c13-default {
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mux {
|
||||
pins = "gpio43", "gpio44";
|
||||
function = "qup13";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio43", "gpio44";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c14_default: qup-i2c14-default {
|
||||
mux {
|
||||
pins = "gpio47", "gpio48";
|
||||
function = "qup14";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio47", "gpio48";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c15_default: qup-i2c15-default {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28";
|
||||
function = "qup15";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio27", "gpio28";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c16_default: qup-i2c16-default {
|
||||
mux {
|
||||
pins = "gpio86", "gpio85";
|
||||
function = "qup16";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio86", "gpio85";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c17_default: qup-i2c17-default {
|
||||
mux {
|
||||
pins = "gpio55", "gpio56";
|
||||
function = "qup17";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio55", "gpio56";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c18_default: qup-i2c18-default {
|
||||
mux {
|
||||
pins = "gpio23", "gpio24";
|
||||
function = "qup18";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio23", "gpio24";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qup_i2c19_default: qup-i2c19-default {
|
||||
mux {
|
||||
pins = "gpio57", "gpio58";
|
||||
function = "qup19";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio57", "gpio58";
|
||||
drive-strength = <0x02>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
remoteproc_mpss: remoteproc@4080000 {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user