serial: sc16is7xx: remove obsolete loop in sc16is7xx_port_irq()
commit ed647256e8f226241ecff7baaecdb8632ffc7ec1 upstream. Commit8344498721
("sc16is7xx: Fix for multi-channel stall") changed sc16is7xx_port_irq() from looping multiple times when there was still interrupts to serve. It simply changed the do {} while(1) loop to a do {} while(0) loop, which makes the loop itself now obsolete. Clean the code by removing this obsolete do {} while(0) loop. Fixes:8344498721
("sc16is7xx: Fix for multi-channel stall") Cc: <stable@vger.kernel.org> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Link: https://lore.kernel.org/r/20231221231823.2327894-5-hugo@hugovil.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -726,58 +726,55 @@ static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
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static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
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{
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bool rc = true;
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unsigned int iir, rxlen;
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struct uart_port *port = &s->p[portno].port;
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struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
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mutex_lock(&one->efr_lock);
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do {
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unsigned int iir, rxlen;
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iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
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if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
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rc = false;
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goto out_port_irq;
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}
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iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
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if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
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rc = false;
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goto out_port_irq;
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}
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iir &= SC16IS7XX_IIR_ID_MASK;
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iir &= SC16IS7XX_IIR_ID_MASK;
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switch (iir) {
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case SC16IS7XX_IIR_RDI_SRC:
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case SC16IS7XX_IIR_RLSE_SRC:
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case SC16IS7XX_IIR_RTOI_SRC:
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case SC16IS7XX_IIR_XOFFI_SRC:
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rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
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switch (iir) {
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case SC16IS7XX_IIR_RDI_SRC:
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case SC16IS7XX_IIR_RLSE_SRC:
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case SC16IS7XX_IIR_RTOI_SRC:
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case SC16IS7XX_IIR_XOFFI_SRC:
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rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
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/*
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* There is a silicon bug that makes the chip report a
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* time-out interrupt but no data in the FIFO. This is
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* described in errata section 18.1.4.
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*
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* When this happens, read one byte from the FIFO to
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* clear the interrupt.
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*/
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if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
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rxlen = 1;
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/*
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* There is a silicon bug that makes the chip report a
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* time-out interrupt but no data in the FIFO. This is
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* described in errata section 18.1.4.
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*
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* When this happens, read one byte from the FIFO to
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* clear the interrupt.
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*/
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if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
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rxlen = 1;
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if (rxlen)
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sc16is7xx_handle_rx(port, rxlen, iir);
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break;
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if (rxlen)
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sc16is7xx_handle_rx(port, rxlen, iir);
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break;
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/* CTSRTS interrupt comes only when CTS goes inactive */
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case SC16IS7XX_IIR_CTSRTS_SRC:
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case SC16IS7XX_IIR_MSI_SRC:
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sc16is7xx_update_mlines(one);
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break;
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case SC16IS7XX_IIR_THRI_SRC:
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sc16is7xx_handle_tx(port);
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break;
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default:
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dev_err_ratelimited(port->dev,
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"ttySC%i: Unexpected interrupt: %x",
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port->line, iir);
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break;
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}
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} while (0);
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case SC16IS7XX_IIR_CTSRTS_SRC:
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case SC16IS7XX_IIR_MSI_SRC:
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sc16is7xx_update_mlines(one);
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break;
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case SC16IS7XX_IIR_THRI_SRC:
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sc16is7xx_handle_tx(port);
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break;
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default:
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dev_err_ratelimited(port->dev,
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"ttySC%i: Unexpected interrupt: %x",
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port->line, iir);
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break;
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}
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out_port_irq:
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mutex_unlock(&one->efr_lock);
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