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Merge "clk: qcom: gcc-niobe: Add pwm clocks to support pdm_pwm"

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QCTECMDR Service 2024-08-20 06:36:29 -07:00 committed by Gerrit - the friendly Code Review server
commit 7c0ea1fd5b
2 changed files with 22 additions and 1 deletions
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20
drivers/clk/qcom/gcc-niobe.c
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@ -1933,6 +1933,20 @@ static struct clk_regmap_div gcc_pcie_2_pipe_div_clk_src = {
},
};
static struct clk_regmap_div gcc_pwm0_xo512_div_clk_src = {
.reg = 0x33030,
.shift = 0,
.width = 9,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pwm0_xo512_div_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap1_s1_div_clk_src = {
.reg = 0x18148,
.shift = 0,
@ -3011,6 +3025,11 @@ static struct clk_branch gcc_pwm0_xo512_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pwm0_xo512_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pwm0_xo512_div_clk_src.clkr.hw
},
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@ -4280,6 +4299,7 @@ static struct clk_regmap *gcc_niobe_clocks[] = {
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
[GCC_PWM0_XO512_DIV_CLK_SRC] = &gcc_pwm0_xo512_div_clk_src.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,

3
include/dt-bindings/clock/qcom,gcc-niobe.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NIOBE_H
@ -224,6 +224,7 @@
#define GCC_PCIE_1_PHY_AUX_CLK 214
#define GCC_PCIE_1_PHY_AUX_CLK_SRC 215
#define GCC_USB30_PRIM_ATB_CLK 216
#define GCC_PWM0_XO512_DIV_CLK_SRC 217
/* GCC resets */
#define GCC_CAMERA_BCR 0