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pci: msm: Extend sleep time when reset i2c client

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For HSP link down issue on CPE platform, because CPE NTN3 pcie switch
separates pcie link between RC and EP into two pcie buses,
RC0<->USP and DSP<->EP, so we should take care of this case on pcie
link training, make code change as following:
1. do link training RC0<->USP first and then do link training for
   DSP<->EP
2. link training of DSP<->EP need more time to complete.
From test result, 100ms is not enough, 200ms is ok.

Change-Id: I0f36fc19ab1c6b90132596359c7b158fde7d3e22
Signed-off-by: Harrison Meng <quic_hmeng@quicinc.com>
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
This commit is contained in:
Harrison Meng 2022-06-06 16:44:01 +08:00 committed by Joco Zhang
parent 3fcfd9ecc2
commit 7ac6c00b11
1 changed files with 6 additions and 10 deletions
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16
drivers/pci/controller/pci-msm.c
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@ -6137,12 +6137,6 @@ static int msm_pcie_enable_link(struct msm_pcie_dev_t *dev)
dev->i2c_ctrl.client_i2c_de_emphasis_wa(&dev->i2c_ctrl);
msleep(20);
}
/* bring eps out of reset */
if (dev->i2c_ctrl.client && dev->i2c_ctrl.client_i2c_reset
&& !dev->i2c_ctrl.ep_reset_postlinkup) {
dev->i2c_ctrl.client_i2c_reset(&dev->i2c_ctrl, false);
msleep(100);
}
#endif
ret = msm_pcie_link_train(dev);
@ -6306,11 +6300,13 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
}
#if IS_ENABLED(CONFIG_I2C)
/* Bring pine EP out of reset*/
if (dev->i2c_ctrl.client && dev->i2c_ctrl.client_i2c_reset
&& dev->i2c_ctrl.ep_reset_postlinkup) {
/* Bring EP out of reset*/
if (dev->i2c_ctrl.client && dev->i2c_ctrl.client_i2c_reset) {
dev->i2c_ctrl.client_i2c_reset(&dev->i2c_ctrl, false);
msleep(100);
PCIE_DBG(dev,
"PCIe: Bring EPs out of reset and then wait for link training.\n");
msleep(200);
PCIE_DBG(dev, "PCIe: Finish EPs link training wait.\n");
}
#endif
goto out;