Revert "PCI: Add locking to RMW PCI Express Capability Register accessors"
This reverts commit f2d7da8faf
which is
commit 5e70d0acf0825f439079736080350371f8d6699a upstream.
It breaks the Android API and is not needed for any Android-specific
platforms, so it can be dropped for now. If it is needed in the future,
it can be brought back in an abi-safe way.
Bug: 161946584
Change-Id: Ic12bc34085f8c7ecea1899f7e14b6ba2a920beba
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
parent
41aa552887
commit
79dd1a60c7
@ -491,8 +491,8 @@ int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
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}
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EXPORT_SYMBOL(pcie_capability_write_dword);
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int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
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u16 clear, u16 set)
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int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
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u16 clear, u16 set)
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{
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int ret;
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u16 val;
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@ -506,21 +506,7 @@ int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
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return ret;
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}
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EXPORT_SYMBOL(pcie_capability_clear_and_set_word_unlocked);
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int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
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u16 clear, u16 set)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&dev->pcie_cap_lock, flags);
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ret = pcie_capability_clear_and_set_word_unlocked(dev, pos, clear, set);
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spin_unlock_irqrestore(&dev->pcie_cap_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(pcie_capability_clear_and_set_word_locked);
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EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
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int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
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u32 clear, u32 set)
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@ -2313,7 +2313,6 @@ struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
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.end = -1,
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};
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spin_lock_init(&dev->pcie_cap_lock);
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#ifdef CONFIG_PCI_MSI
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raw_spin_lock_init(&dev->msi_lock);
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#endif
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@ -467,7 +467,6 @@ struct pci_dev {
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pci_dev_flags_t dev_flags;
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atomic_t enable_cnt; /* pci_enable_device has been called */
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spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
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u32 saved_config_space[16]; /* Config space saved at suspend time */
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struct hlist_head saved_cap_space;
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int rom_attr_enabled; /* Display of ROM attribute enabled? */
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@ -1234,40 +1233,11 @@ int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
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int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
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int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
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int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
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int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
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u16 clear, u16 set);
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int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
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u16 clear, u16 set);
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int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
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u16 clear, u16 set);
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int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
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u32 clear, u32 set);
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/**
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* pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers
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* @dev: PCI device structure of the PCI Express device
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* @pos: PCI Express Capability Register
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* @clear: Clear bitmask
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* @set: Set bitmask
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*
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* Perform a Read-Modify-Write (RMW) operation using @clear and @set
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* bitmasks on PCI Express Capability Register at @pos. Certain PCI Express
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* Capability Registers are accessed concurrently in RMW fashion, hence
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* require locking which is handled transparently to the caller.
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*/
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static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
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int pos,
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u16 clear, u16 set)
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{
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switch (pos) {
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case PCI_EXP_LNKCTL:
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case PCI_EXP_RTCTL:
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return pcie_capability_clear_and_set_word_locked(dev, pos,
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clear, set);
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default:
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return pcie_capability_clear_and_set_word_unlocked(dev, pos,
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clear, set);
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}
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}
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static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
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u16 set)
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{
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