pinctrl: renesas: sh7264: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 572 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/434c274f626b2eab3539fe2ab80c6eda164e07fa.1649865241.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
parent
256c14196f
commit
78fc20c155
@ -1464,19 +1464,20 @@ static const struct pinmux_func pinmux_func_gpios[] = {
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};
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static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PAIOR0", 0xfffe3812, 16,
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GROUP(-12, 1, 1, 1, 1),
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GROUP(
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/* RESERVED [12] */
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PA3_IN, PA3_OUT,
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PA2_IN, PA2_OUT,
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PA1_IN, PA1_OUT,
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PA0_IN, PA0_OUT ))
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},
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{ PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PBCR5", 0xfffe3824, 16,
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GROUP(-4, 4, 4, 4),
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GROUP(
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/* RESERVED [4] */
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PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
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@ -1525,21 +1526,22 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, PB4MD_01, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
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{ PINMUX_CFG_REG_VAR("PBCR0", 0xfffe382e, 16,
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GROUP(4, 4, 4, -4),
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GROUP(
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0, PB3MD_1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, PB2MD_1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, PB1MD_1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0 ))
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/* RESERVED [4] */ ))
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},
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{ PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0,
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{ PINMUX_CFG_REG_VAR("PBIOR1", 0xfffe3830, 16,
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GROUP(-9, 1, 1, 1, 1, 1, 1, 1),
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GROUP(
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/* RESERVED [9] */
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PB22_IN, PB22_OUT,
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PB21_IN, PB21_OUT,
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PB20_IN, PB20_OUT,
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@ -1568,9 +1570,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0 ))
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},
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{ PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PCCR2", 0xfffe384a, 16,
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GROUP(-4, 4, 4, 4),
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GROUP(
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/* RESERVED [4] */
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PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
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@ -1599,8 +1602,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0, 0, 0, 0, 0, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PCIOR0", 0xfffe3852, 16,
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GROUP(-5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
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GROUP(
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/* RESERVED [5] */
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PC10_IN, PC10_OUT,
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PC9_IN, PC9_OUT,
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PC8_IN, PC8_OUT,
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@ -1675,11 +1680,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PD0_IN, PD0_OUT ))
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},
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{ PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PECR1", 0xfffe388c, 16,
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GROUP(-8, 4, 4),
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GROUP(
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/* RESERVED [8] */
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PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
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@ -1698,10 +1702,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0, 0, 0, 0, 0, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PEIOR0", 0xfffe3892, 16,
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GROUP(-10, 1, 1, 1, 1, 1, 1),
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GROUP(
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/* RESERVED [10] */
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PE5_IN, PE5_OUT,
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PE4_IN, PE4_OUT,
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PE3_IN, PE3_OUT,
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@ -1710,10 +1714,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PE0_IN, PE0_OUT ))
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},
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{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PFCR3", 0xfffe38a8, 16,
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GROUP(-12, 4),
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GROUP(
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/* RESERVED [12] */
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PF12MD_000, PF12MD_001, 0, PF12MD_011,
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PF12MD_100, PF12MD_101, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0 ))
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@ -1780,25 +1784,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PF0_IN, PF0_OUT ))
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},
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{ PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PGCR7", 0xfffe38c0, 16,
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GROUP(-12, 4),
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GROUP(
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/* RESERVED [12] */
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PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
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PG0MD_100, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PGCR6", 0xfffe38c2, 16,
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GROUP(-12, 4),
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GROUP(
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/* RESERVED [12] */
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PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0 ))
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},
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@ -1869,19 +1867,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0 ))
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},
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{ PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4, GROUP(
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{ PINMUX_CFG_REG_VAR("PGCR0", 0xfffe38ce, 16,
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GROUP(4, 4, 4, -4),
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GROUP(
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PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0 ))
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/* RESERVED [4] */ ))
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},
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{ PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1, GROUP(
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0,
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{ PINMUX_CFG_REG_VAR("PGIOR1", 0xfffe38d0, 16,
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GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1),
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GROUP(
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/* RESERVED [7] */
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PG24_IN, PG24_OUT,
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PG23_IN, PG23_OUT,
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PG22_IN, PG22_OUT,
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