Merge f8a52af9d0 ("Merge tag 'i2c-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux") into android-mainline
Steps on the way to 5.19-rc1 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I7a6f4006a216fc4828361ba7ec74e6a8e3849877
This commit is contained in:
Greg Kroah-Hartman
commit
78dcf9434c
218
.clang-format
218
.clang-format
@ -1,6 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# clang-format configuration file. Intended for clang-format >= 4.
|
||||
# clang-format configuration file. Intended for clang-format >= 11.
|
||||
#
|
||||
# For more information, see:
|
||||
#
|
||||
@ -13,7 +13,7 @@ AccessModifierOffset: -4
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||||
AlignAfterOpenBracket: Align
|
||||
AlignConsecutiveAssignments: false
|
||||
AlignConsecutiveDeclarations: false
|
||||
#AlignEscapedNewlines: Left # Unknown to clang-format-4.0
|
||||
AlignEscapedNewlines: Left
|
||||
AlignOperands: true
|
||||
AlignTrailingComments: false
|
||||
AllowAllParametersOfDeclarationOnNextLine: false
|
||||
@ -37,24 +37,24 @@ BraceWrapping:
|
||||
AfterObjCDeclaration: false
|
||||
AfterStruct: false
|
||||
AfterUnion: false
|
||||
#AfterExternBlock: false # Unknown to clang-format-5.0
|
||||
AfterExternBlock: false
|
||||
BeforeCatch: false
|
||||
BeforeElse: false
|
||||
IndentBraces: false
|
||||
#SplitEmptyFunction: true # Unknown to clang-format-4.0
|
||||
#SplitEmptyRecord: true # Unknown to clang-format-4.0
|
||||
#SplitEmptyNamespace: true # Unknown to clang-format-4.0
|
||||
SplitEmptyFunction: true
|
||||
SplitEmptyRecord: true
|
||||
SplitEmptyNamespace: true
|
||||
BreakBeforeBinaryOperators: None
|
||||
BreakBeforeBraces: Custom
|
||||
#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0
|
||||
BreakBeforeInheritanceComma: false
|
||||
BreakBeforeTernaryOperators: false
|
||||
BreakConstructorInitializersBeforeComma: false
|
||||
#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0
|
||||
BreakConstructorInitializers: BeforeComma
|
||||
BreakAfterJavaFieldAnnotations: false
|
||||
BreakStringLiterals: false
|
||||
ColumnLimit: 80
|
||||
CommentPragmas: '^ IWYU pragma:'
|
||||
#CompactNamespaces: false # Unknown to clang-format-4.0
|
||||
CompactNamespaces: false
|
||||
ConstructorInitializerAllOnOneLineOrOnePerLine: false
|
||||
ConstructorInitializerIndentWidth: 8
|
||||
ContinuationIndentWidth: 8
|
||||
@ -62,39 +62,56 @@ Cpp11BracedListStyle: false
|
||||
DerivePointerAlignment: false
|
||||
DisableFormat: false
|
||||
ExperimentalAutoDetectBinPacking: false
|
||||
#FixNamespaceComments: false # Unknown to clang-format-4.0
|
||||
FixNamespaceComments: false
|
||||
|
||||
# Taken from:
|
||||
# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \
|
||||
# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ tools/ \
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||||
# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
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||||
# | sort | uniq
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||||
# | LC_ALL=C sort -u
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ForEachMacros:
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||||
- '__ata_qc_for_each'
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||||
- '__bio_for_each_bvec'
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||||
- '__bio_for_each_segment'
|
||||
- '__evlist__for_each_entry'
|
||||
- '__evlist__for_each_entry_continue'
|
||||
- '__evlist__for_each_entry_from'
|
||||
- '__evlist__for_each_entry_reverse'
|
||||
- '__evlist__for_each_entry_safe'
|
||||
- '__for_each_mem_range'
|
||||
- '__for_each_mem_range_rev'
|
||||
- '__for_each_thread'
|
||||
- '__hlist_for_each_rcu'
|
||||
- '__map__for_each_symbol_by_name'
|
||||
- '__perf_evlist__for_each_entry'
|
||||
- '__perf_evlist__for_each_entry_reverse'
|
||||
- '__perf_evlist__for_each_entry_safe'
|
||||
- '__rq_for_each_bio'
|
||||
- '__shost_for_each_device'
|
||||
- 'apei_estatus_for_each_section'
|
||||
- 'ata_for_each_dev'
|
||||
- 'ata_for_each_link'
|
||||
- '__ata_qc_for_each'
|
||||
- 'ata_qc_for_each'
|
||||
- 'ata_qc_for_each_raw'
|
||||
- 'ata_qc_for_each_with_internal'
|
||||
- 'ax25_for_each'
|
||||
- 'ax25_uid_for_each'
|
||||
- '__bio_for_each_bvec'
|
||||
- 'bio_for_each_bvec'
|
||||
- 'bio_for_each_bvec_all'
|
||||
- 'bio_for_each_folio_all'
|
||||
- 'bio_for_each_integrity_vec'
|
||||
- '__bio_for_each_segment'
|
||||
- 'bio_for_each_segment'
|
||||
- 'bio_for_each_segment_all'
|
||||
- 'bio_list_for_each'
|
||||
- 'bip_for_each_vec'
|
||||
- 'bitmap_for_each_clear_region'
|
||||
- 'bitmap_for_each_set_region'
|
||||
- 'blkg_for_each_descendant_post'
|
||||
- 'blkg_for_each_descendant_pre'
|
||||
- 'blk_queue_for_each_rl'
|
||||
- 'bond_for_each_slave'
|
||||
- 'bond_for_each_slave_rcu'
|
||||
- 'bpf__perf_for_each_map'
|
||||
- 'bpf__perf_for_each_map_named'
|
||||
- 'bpf_for_each_spilled_reg'
|
||||
- 'bpf_object__for_each_map'
|
||||
- 'bpf_object__for_each_program'
|
||||
- 'bpf_object__for_each_safe'
|
||||
- 'bpf_perf_object__for_each'
|
||||
- 'btree_for_each_safe128'
|
||||
- 'btree_for_each_safe32'
|
||||
- 'btree_for_each_safe64'
|
||||
@ -102,6 +119,7 @@ ForEachMacros:
|
||||
- 'card_for_each_dev'
|
||||
- 'cgroup_taskset_for_each'
|
||||
- 'cgroup_taskset_for_each_leader'
|
||||
- 'cpufreq_for_each_efficient_entry_idx'
|
||||
- 'cpufreq_for_each_entry'
|
||||
- 'cpufreq_for_each_entry_idx'
|
||||
- 'cpufreq_for_each_valid_entry'
|
||||
@ -109,9 +127,22 @@ ForEachMacros:
|
||||
- 'css_for_each_child'
|
||||
- 'css_for_each_descendant_post'
|
||||
- 'css_for_each_descendant_pre'
|
||||
- 'damon_for_each_region'
|
||||
- 'damon_for_each_region_safe'
|
||||
- 'damon_for_each_scheme'
|
||||
- 'damon_for_each_scheme_safe'
|
||||
- 'damon_for_each_target'
|
||||
- 'damon_for_each_target_safe'
|
||||
- 'data__for_each_file'
|
||||
- 'data__for_each_file_new'
|
||||
- 'data__for_each_file_start'
|
||||
- 'device_for_each_child_node'
|
||||
- 'displayid_iter_for_each'
|
||||
- 'dma_fence_array_for_each'
|
||||
- 'dma_fence_chain_for_each'
|
||||
- 'dma_fence_unwrap_for_each'
|
||||
- 'dma_resv_for_each_fence'
|
||||
- 'dma_resv_for_each_fence_unlocked'
|
||||
- 'do_for_each_ftrace_op'
|
||||
- 'drm_atomic_crtc_for_each_plane'
|
||||
- 'drm_atomic_crtc_state_for_each_plane'
|
||||
@ -135,6 +166,25 @@ ForEachMacros:
|
||||
- 'drm_mm_for_each_node'
|
||||
- 'drm_mm_for_each_node_in_range'
|
||||
- 'drm_mm_for_each_node_safe'
|
||||
- 'dsa_switch_for_each_available_port'
|
||||
- 'dsa_switch_for_each_cpu_port'
|
||||
- 'dsa_switch_for_each_port'
|
||||
- 'dsa_switch_for_each_port_continue_reverse'
|
||||
- 'dsa_switch_for_each_port_safe'
|
||||
- 'dsa_switch_for_each_user_port'
|
||||
- 'dsa_tree_for_each_user_port'
|
||||
- 'dso__for_each_symbol'
|
||||
- 'dsos__for_each_with_build_id'
|
||||
- 'elf_hash_for_each_possible'
|
||||
- 'elf_section__for_each_rel'
|
||||
- 'elf_section__for_each_rela'
|
||||
- 'elf_symtab__for_each_symbol'
|
||||
- 'evlist__for_each_cpu'
|
||||
- 'evlist__for_each_entry'
|
||||
- 'evlist__for_each_entry_continue'
|
||||
- 'evlist__for_each_entry_from'
|
||||
- 'evlist__for_each_entry_reverse'
|
||||
- 'evlist__for_each_entry_safe'
|
||||
- 'flow_action_for_each'
|
||||
- 'for_each_acpi_dev_match'
|
||||
- 'for_each_active_dev_scope'
|
||||
@ -142,8 +192,11 @@ ForEachMacros:
|
||||
- 'for_each_active_iommu'
|
||||
- 'for_each_aggr_pgid'
|
||||
- 'for_each_available_child_of_node'
|
||||
- 'for_each_bench'
|
||||
- 'for_each_bio'
|
||||
- 'for_each_board_func_rsrc'
|
||||
- 'for_each_btf_ext_rec'
|
||||
- 'for_each_btf_ext_sec'
|
||||
- 'for_each_bvec'
|
||||
- 'for_each_card_auxs'
|
||||
- 'for_each_card_auxs_safe'
|
||||
@ -159,17 +212,22 @@ ForEachMacros:
|
||||
- 'for_each_child_of_node'
|
||||
- 'for_each_clear_bit'
|
||||
- 'for_each_clear_bit_from'
|
||||
- 'for_each_clear_bitrange'
|
||||
- 'for_each_clear_bitrange_from'
|
||||
- 'for_each_cmd'
|
||||
- 'for_each_cmsghdr'
|
||||
- 'for_each_collection'
|
||||
- 'for_each_comp_order'
|
||||
- 'for_each_compatible_node'
|
||||
- 'for_each_component_dais'
|
||||
- 'for_each_component_dais_safe'
|
||||
- 'for_each_comp_order'
|
||||
- 'for_each_console'
|
||||
- 'for_each_cpu'
|
||||
- 'for_each_cpu_and'
|
||||
- 'for_each_cpu_not'
|
||||
- 'for_each_cpu_wrap'
|
||||
- 'for_each_dapm_widgets'
|
||||
- 'for_each_dedup_cand'
|
||||
- 'for_each_dev_addr'
|
||||
- 'for_each_dev_scope'
|
||||
- 'for_each_dma_cap_mask'
|
||||
@ -179,13 +237,14 @@ ForEachMacros:
|
||||
- 'for_each_dpcm_fe'
|
||||
- 'for_each_drhd_unit'
|
||||
- 'for_each_dss_dev'
|
||||
- 'for_each_dtpm_table'
|
||||
- 'for_each_efi_memory_desc'
|
||||
- 'for_each_efi_memory_desc_in_map'
|
||||
- 'for_each_element'
|
||||
- 'for_each_element_extid'
|
||||
- 'for_each_element_id'
|
||||
- 'for_each_endpoint_of_node'
|
||||
- 'for_each_event'
|
||||
- 'for_each_event_tps'
|
||||
- 'for_each_evictable_lru'
|
||||
- 'for_each_fib6_node_rt_rcu'
|
||||
- 'for_each_fib6_walker_rt'
|
||||
@ -194,30 +253,35 @@ ForEachMacros:
|
||||
- 'for_each_free_mem_range'
|
||||
- 'for_each_free_mem_range_reverse'
|
||||
- 'for_each_func_rsrc'
|
||||
- 'for_each_group_evsel'
|
||||
- 'for_each_group_member'
|
||||
- 'for_each_hstate'
|
||||
- 'for_each_if'
|
||||
- 'for_each_inject_fn'
|
||||
- 'for_each_insn'
|
||||
- 'for_each_insn_prefix'
|
||||
- 'for_each_intid'
|
||||
- 'for_each_iommu'
|
||||
- 'for_each_ip_tunnel_rcu'
|
||||
- 'for_each_irq_nr'
|
||||
- 'for_each_lang'
|
||||
- 'for_each_link_codecs'
|
||||
- 'for_each_link_cpus'
|
||||
- 'for_each_link_platforms'
|
||||
- 'for_each_lru'
|
||||
- 'for_each_matching_node'
|
||||
- 'for_each_matching_node_and_match'
|
||||
- 'for_each_member'
|
||||
- 'for_each_memcg_cache_index'
|
||||
- 'for_each_mem_pfn_range'
|
||||
- '__for_each_mem_range'
|
||||
- 'for_each_mem_range'
|
||||
- '__for_each_mem_range_rev'
|
||||
- 'for_each_mem_range_rev'
|
||||
- 'for_each_mem_region'
|
||||
- 'for_each_member'
|
||||
- 'for_each_memory'
|
||||
- 'for_each_migratetype_order'
|
||||
- 'for_each_msi_entry'
|
||||
- 'for_each_msi_entry_safe'
|
||||
- 'for_each_missing_reg'
|
||||
- 'for_each_net'
|
||||
- 'for_each_net_continue_reverse'
|
||||
- 'for_each_net_rcu'
|
||||
- 'for_each_netdev'
|
||||
- 'for_each_netdev_continue'
|
||||
- 'for_each_netdev_continue_rcu'
|
||||
@ -227,12 +291,13 @@ ForEachMacros:
|
||||
- 'for_each_netdev_rcu'
|
||||
- 'for_each_netdev_reverse'
|
||||
- 'for_each_netdev_safe'
|
||||
- 'for_each_net_rcu'
|
||||
- 'for_each_new_connector_in_state'
|
||||
- 'for_each_new_crtc_in_state'
|
||||
- 'for_each_new_mst_mgr_in_state'
|
||||
- 'for_each_new_plane_in_state'
|
||||
- 'for_each_new_plane_in_state_reverse'
|
||||
- 'for_each_new_private_obj_in_state'
|
||||
- 'for_each_new_reg'
|
||||
- 'for_each_node'
|
||||
- 'for_each_node_by_name'
|
||||
- 'for_each_node_by_type'
|
||||
@ -248,20 +313,20 @@ ForEachMacros:
|
||||
- 'for_each_old_connector_in_state'
|
||||
- 'for_each_old_crtc_in_state'
|
||||
- 'for_each_old_mst_mgr_in_state'
|
||||
- 'for_each_old_plane_in_state'
|
||||
- 'for_each_old_private_obj_in_state'
|
||||
- 'for_each_oldnew_connector_in_state'
|
||||
- 'for_each_oldnew_crtc_in_state'
|
||||
- 'for_each_oldnew_mst_mgr_in_state'
|
||||
- 'for_each_oldnew_plane_in_state'
|
||||
- 'for_each_oldnew_plane_in_state_reverse'
|
||||
- 'for_each_oldnew_private_obj_in_state'
|
||||
- 'for_each_old_plane_in_state'
|
||||
- 'for_each_old_private_obj_in_state'
|
||||
- 'for_each_online_cpu'
|
||||
- 'for_each_online_node'
|
||||
- 'for_each_online_pgdat'
|
||||
- 'for_each_path'
|
||||
- 'for_each_pci_bridge'
|
||||
- 'for_each_pci_dev'
|
||||
- 'for_each_pci_msi_entry'
|
||||
- 'for_each_pcm_streams'
|
||||
- 'for_each_physmem_range'
|
||||
- 'for_each_populated_zone'
|
||||
@ -269,6 +334,7 @@ ForEachMacros:
|
||||
- 'for_each_present_cpu'
|
||||
- 'for_each_prime_number'
|
||||
- 'for_each_prime_number_from'
|
||||
- 'for_each_probe_cache_entry'
|
||||
- 'for_each_process'
|
||||
- 'for_each_process_thread'
|
||||
- 'for_each_prop_codec_conf'
|
||||
@ -278,6 +344,8 @@ ForEachMacros:
|
||||
- 'for_each_prop_dlc_cpus'
|
||||
- 'for_each_prop_dlc_platforms'
|
||||
- 'for_each_property_of_node'
|
||||
- 'for_each_reg'
|
||||
- 'for_each_reg_filtered'
|
||||
- 'for_each_registered_fb'
|
||||
- 'for_each_requested_gpio'
|
||||
- 'for_each_requested_gpio_in_range'
|
||||
@ -287,8 +355,12 @@ ForEachMacros:
|
||||
- 'for_each_rtd_components'
|
||||
- 'for_each_rtd_cpu_dais'
|
||||
- 'for_each_rtd_dais'
|
||||
- 'for_each_script'
|
||||
- 'for_each_sec'
|
||||
- 'for_each_set_bit'
|
||||
- 'for_each_set_bit_from'
|
||||
- 'for_each_set_bitrange'
|
||||
- 'for_each_set_bitrange_from'
|
||||
- 'for_each_set_clump8'
|
||||
- 'for_each_sg'
|
||||
- 'for_each_sg_dma_page'
|
||||
@ -297,18 +369,25 @@ ForEachMacros:
|
||||
- 'for_each_sgtable_dma_sg'
|
||||
- 'for_each_sgtable_page'
|
||||
- 'for_each_sgtable_sg'
|
||||
- 'for_each_shell_test'
|
||||
- 'for_each_sibling_event'
|
||||
- 'for_each_subelement'
|
||||
- 'for_each_subelement_extid'
|
||||
- 'for_each_subelement_id'
|
||||
- '__for_each_thread'
|
||||
- 'for_each_sublist'
|
||||
- 'for_each_subsystem'
|
||||
- 'for_each_supported_activate_fn'
|
||||
- 'for_each_supported_inject_fn'
|
||||
- 'for_each_test'
|
||||
- 'for_each_thread'
|
||||
- 'for_each_token'
|
||||
- 'for_each_unicast_dest_pgid'
|
||||
- 'for_each_vsi'
|
||||
- 'for_each_wakeup_source'
|
||||
- 'for_each_zone'
|
||||
- 'for_each_zone_zonelist'
|
||||
- 'for_each_zone_zonelist_nodemask'
|
||||
- 'func_for_each_insn'
|
||||
- 'fwnode_for_each_available_child_node'
|
||||
- 'fwnode_for_each_child_node'
|
||||
- 'fwnode_graph_for_each_endpoint'
|
||||
@ -322,7 +401,13 @@ ForEachMacros:
|
||||
- 'hash_for_each_possible_safe'
|
||||
- 'hash_for_each_rcu'
|
||||
- 'hash_for_each_safe'
|
||||
- 'hashmap__for_each_entry'
|
||||
- 'hashmap__for_each_entry_safe'
|
||||
- 'hashmap__for_each_key_entry'
|
||||
- 'hashmap__for_each_key_entry_safe'
|
||||
- 'hctx_for_each_ctx'
|
||||
- 'hists__for_each_format'
|
||||
- 'hists__for_each_sort_list'
|
||||
- 'hlist_bl_for_each_entry'
|
||||
- 'hlist_bl_for_each_entry_rcu'
|
||||
- 'hlist_bl_for_each_entry_safe'
|
||||
@ -338,7 +423,6 @@ ForEachMacros:
|
||||
- 'hlist_for_each_entry_rcu_notrace'
|
||||
- 'hlist_for_each_entry_safe'
|
||||
- 'hlist_for_each_entry_srcu'
|
||||
- '__hlist_for_each_rcu'
|
||||
- 'hlist_for_each_safe'
|
||||
- 'hlist_nulls_for_each_entry'
|
||||
- 'hlist_nulls_for_each_entry_from'
|
||||
@ -346,9 +430,6 @@ ForEachMacros:
|
||||
- 'hlist_nulls_for_each_entry_safe'
|
||||
- 'i3c_bus_for_each_i2cdev'
|
||||
- 'i3c_bus_for_each_i3cdev'
|
||||
- 'ide_host_for_each_port'
|
||||
- 'ide_port_for_each_dev'
|
||||
- 'ide_port_for_each_present_dev'
|
||||
- 'idr_for_each_entry'
|
||||
- 'idr_for_each_entry_continue'
|
||||
- 'idr_for_each_entry_continue_ul'
|
||||
@ -356,7 +437,12 @@ ForEachMacros:
|
||||
- 'in_dev_for_each_ifa_rcu'
|
||||
- 'in_dev_for_each_ifa_rtnl'
|
||||
- 'inet_bind_bucket_for_each'
|
||||
- 'inet_lhash2_for_each_icsk'
|
||||
- 'inet_lhash2_for_each_icsk_continue'
|
||||
- 'inet_lhash2_for_each_icsk_rcu'
|
||||
- 'intlist__for_each_entry'
|
||||
- 'intlist__for_each_entry_safe'
|
||||
- 'kcore_copy__for_each_phdr'
|
||||
- 'key_for_each'
|
||||
- 'key_for_each_safe'
|
||||
- 'klp_for_each_func'
|
||||
@ -367,7 +453,9 @@ ForEachMacros:
|
||||
- 'klp_for_each_object_static'
|
||||
- 'kunit_suite_for_each_test_case'
|
||||
- 'kvm_for_each_memslot'
|
||||
- 'kvm_for_each_memslot_in_gfn_range'
|
||||
- 'kvm_for_each_vcpu'
|
||||
- 'libbpf_nla_for_each_attr'
|
||||
- 'list_for_each'
|
||||
- 'list_for_each_codec'
|
||||
- 'list_for_each_codec_safe'
|
||||
@ -387,6 +475,7 @@ ForEachMacros:
|
||||
- 'list_for_each_entry_safe_from'
|
||||
- 'list_for_each_entry_safe_reverse'
|
||||
- 'list_for_each_entry_srcu'
|
||||
- 'list_for_each_from'
|
||||
- 'list_for_each_prev'
|
||||
- 'list_for_each_prev_safe'
|
||||
- 'list_for_each_safe'
|
||||
@ -394,11 +483,18 @@ ForEachMacros:
|
||||
- 'llist_for_each_entry'
|
||||
- 'llist_for_each_entry_safe'
|
||||
- 'llist_for_each_safe'
|
||||
- 'map__for_each_symbol'
|
||||
- 'map__for_each_symbol_by_name'
|
||||
- 'map_for_each_event'
|
||||
- 'map_for_each_metric'
|
||||
- 'maps__for_each_entry'
|
||||
- 'maps__for_each_entry_safe'
|
||||
- 'mci_for_each_dimm'
|
||||
- 'media_device_for_each_entity'
|
||||
- 'media_device_for_each_intf'
|
||||
- 'media_device_for_each_link'
|
||||
- 'media_device_for_each_pad'
|
||||
- 'msi_for_each_desc'
|
||||
- 'nanddev_io_for_each_page'
|
||||
- 'netdev_for_each_lower_dev'
|
||||
- 'netdev_for_each_lower_private'
|
||||
@ -423,6 +519,20 @@ ForEachMacros:
|
||||
- 'pcl_for_each_chunk'
|
||||
- 'pcl_for_each_segment'
|
||||
- 'pcm_for_each_format'
|
||||
- 'perf_config_items__for_each_entry'
|
||||
- 'perf_config_sections__for_each_entry'
|
||||
- 'perf_config_set__for_each_entry'
|
||||
- 'perf_cpu_map__for_each_cpu'
|
||||
- 'perf_evlist__for_each_entry'
|
||||
- 'perf_evlist__for_each_entry_reverse'
|
||||
- 'perf_evlist__for_each_entry_safe'
|
||||
- 'perf_evlist__for_each_evsel'
|
||||
- 'perf_evlist__for_each_mmap'
|
||||
- 'perf_hpp_list__for_each_format'
|
||||
- 'perf_hpp_list__for_each_format_safe'
|
||||
- 'perf_hpp_list__for_each_sort_list'
|
||||
- 'perf_hpp_list__for_each_sort_list_safe'
|
||||
- 'perf_pmu__for_each_hybrid_pmu'
|
||||
- 'ping_portaddr_for_each_entry'
|
||||
- 'plist_for_each'
|
||||
- 'plist_for_each_continue'
|
||||
@ -442,6 +552,7 @@ ForEachMacros:
|
||||
- 'rdma_for_each_block'
|
||||
- 'rdma_for_each_port'
|
||||
- 'rdma_umem_for_each_dma_block'
|
||||
- 'resort_rb__for_each_entry'
|
||||
- 'resource_list_for_each_entry'
|
||||
- 'resource_list_for_each_entry_safe'
|
||||
- 'rhl_for_each_entry_rcu'
|
||||
@ -455,15 +566,18 @@ ForEachMacros:
|
||||
- 'rht_for_each_from'
|
||||
- 'rht_for_each_rcu'
|
||||
- 'rht_for_each_rcu_from'
|
||||
- '__rq_for_each_bio'
|
||||
- 'rq_for_each_bvec'
|
||||
- 'rq_for_each_segment'
|
||||
- 'rq_list_for_each'
|
||||
- 'rq_list_for_each_safe'
|
||||
- 'scsi_for_each_prot_sg'
|
||||
- 'scsi_for_each_sg'
|
||||
- 'sctp_for_each_hentry'
|
||||
- 'sctp_skb_for_each'
|
||||
- 'sec_for_each_insn'
|
||||
- 'sec_for_each_insn_continue'
|
||||
- 'sec_for_each_insn_from'
|
||||
- 'shdma_for_each_chan'
|
||||
- '__shost_for_each_device'
|
||||
- 'shost_for_each_device'
|
||||
- 'sk_for_each'
|
||||
- 'sk_for_each_bound'
|
||||
@ -480,7 +594,13 @@ ForEachMacros:
|
||||
- 'snd_soc_dapm_widget_for_each_path_safe'
|
||||
- 'snd_soc_dapm_widget_for_each_sink_path'
|
||||
- 'snd_soc_dapm_widget_for_each_source_path'
|
||||
- 'strlist__for_each_entry'
|
||||
- 'strlist__for_each_entry_safe'
|
||||
- 'sym_for_each_insn'
|
||||
- 'sym_for_each_insn_continue_reverse'
|
||||
- 'symbols__for_each_entry'
|
||||
- 'tb_property_for_each'
|
||||
- 'tcf_act_for_each_action'
|
||||
- 'tcf_exts_for_each_action'
|
||||
- 'udp_portaddr_for_each_entry'
|
||||
- 'udp_portaddr_for_each_entry_rcu'
|
||||
@ -504,15 +624,17 @@ ForEachMacros:
|
||||
- 'xbc_node_for_each_array_value'
|
||||
- 'xbc_node_for_each_child'
|
||||
- 'xbc_node_for_each_key_value'
|
||||
- 'xbc_node_for_each_subkey'
|
||||
- 'zorro_for_each_dev'
|
||||
|
||||
#IncludeBlocks: Preserve # Unknown to clang-format-5.0
|
||||
IncludeBlocks: Preserve
|
||||
IncludeCategories:
|
||||
- Regex: '.*'
|
||||
Priority: 1
|
||||
IncludeIsMainRegex: '(Test)?$'
|
||||
IndentCaseLabels: false
|
||||
#IndentPPDirectives: None # Unknown to clang-format-5.0
|
||||
IndentGotoLabels: false
|
||||
IndentPPDirectives: None
|
||||
IndentWidth: 8
|
||||
IndentWrappedFunctionNames: false
|
||||
JavaScriptQuotes: Leave
|
||||
@ -522,13 +644,13 @@ MacroBlockBegin: ''
|
||||
MacroBlockEnd: ''
|
||||
MaxEmptyLinesToKeep: 1
|
||||
NamespaceIndentation: None
|
||||
#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0
|
||||
ObjCBinPackProtocolList: Auto
|
||||
ObjCBlockIndentWidth: 8
|
||||
ObjCSpaceAfterProperty: true
|
||||
ObjCSpaceBeforeProtocolList: true
|
||||
|
||||
# Taken from git's rules
|
||||
#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0
|
||||
PenaltyBreakAssignment: 10
|
||||
PenaltyBreakBeforeFirstCallParameter: 30
|
||||
PenaltyBreakComment: 10
|
||||
PenaltyBreakFirstLessLess: 0
|
||||
@ -539,14 +661,14 @@ PenaltyReturnTypeOnItsOwnLine: 60
|
||||
PointerAlignment: Right
|
||||
ReflowComments: false
|
||||
SortIncludes: false
|
||||
#SortUsingDeclarations: false # Unknown to clang-format-4.0
|
||||
SortUsingDeclarations: false
|
||||
SpaceAfterCStyleCast: false
|
||||
SpaceAfterTemplateKeyword: true
|
||||
SpaceBeforeAssignmentOperators: true
|
||||
#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0
|
||||
#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0
|
||||
SpaceBeforeParens: ControlStatements
|
||||
#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0
|
||||
SpaceBeforeCtorInitializerColon: true
|
||||
SpaceBeforeInheritanceColon: true
|
||||
SpaceBeforeParens: ControlStatementsExceptForEachMacros
|
||||
SpaceBeforeRangeBasedForLoopColon: true
|
||||
SpaceInEmptyParentheses: false
|
||||
SpacesBeforeTrailingComments: 1
|
||||
SpacesInAngles: false
|
||||
|
||||
@ -104,6 +104,20 @@ Description: Dump the status of the QM.
|
||||
Four states: initiated, started, stopped and closed.
|
||||
Available for both PF and VF, and take no other effect on HPRE.
|
||||
|
||||
What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/diff_regs
|
||||
Date: Mar 2022
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
Description: QM debug registers(regs) read hardware register value. This
|
||||
node is used to show the change of the qm register values. This
|
||||
node can be help users to check the change of register values.
|
||||
|
||||
What: /sys/kernel/debug/hisi_hpre/<bdf>/hpre_dfx/diff_regs
|
||||
Date: Mar 2022
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
Description: HPRE debug registers(regs) read hardware register value. This
|
||||
node is used to show the change of the register values. This
|
||||
node can be help users to check the change of register values.
|
||||
|
||||
What: /sys/kernel/debug/hisi_hpre/<bdf>/hpre_dfx/send_cnt
|
||||
Date: Apr 2020
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
|
||||
@ -84,6 +84,20 @@ Description: Dump the status of the QM.
|
||||
Four states: initiated, started, stopped and closed.
|
||||
Available for both PF and VF, and take no other effect on SEC.
|
||||
|
||||
What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/diff_regs
|
||||
Date: Mar 2022
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
Description: QM debug registers(regs) read hardware register value. This
|
||||
node is used to show the change of the qm register values. This
|
||||
node can be help users to check the change of register values.
|
||||
|
||||
What: /sys/kernel/debug/hisi_sec2/<bdf>/sec_dfx/diff_regs
|
||||
Date: Mar 2022
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
Description: SEC debug registers(regs) read hardware register value. This
|
||||
node is used to show the change of the register values. This
|
||||
node can be help users to check the change of register values.
|
||||
|
||||
What: /sys/kernel/debug/hisi_sec2/<bdf>/sec_dfx/send_cnt
|
||||
Date: Apr 2020
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
|
||||
@ -97,6 +97,20 @@ Description: Dump the status of the QM.
|
||||
Four states: initiated, started, stopped and closed.
|
||||
Available for both PF and VF, and take no other effect on ZIP.
|
||||
|
||||
What: /sys/kernel/debug/hisi_zip/<bdf>/qm/diff_regs
|
||||
Date: Mar 2022
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
Description: QM debug registers(regs) read hardware register value. This
|
||||
node is used to show the change of the qm registers value. This
|
||||
node can be help users to check the change of register values.
|
||||
|
||||
What: /sys/kernel/debug/hisi_zip/<bdf>/zip_dfx/diff_regs
|
||||
Date: Mar 2022
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
Description: ZIP debug registers(regs) read hardware register value. This
|
||||
node is used to show the change of the registers value. this
|
||||
node can be help users to check the change of register values.
|
||||
|
||||
What: /sys/kernel/debug/hisi_zip/<bdf>/zip_dfx/send_cnt
|
||||
Date: Apr 2020
|
||||
Contact: linux-crypto@vger.kernel.org
|
||||
|
||||
@ -103,8 +103,8 @@ What: /sys/class/cxl/<afu>/api_version_compatible
|
||||
Date: September 2014
|
||||
Contact: linuxppc-dev@lists.ozlabs.org
|
||||
Description: read only
|
||||
Decimal value of the the lowest version of the userspace API
|
||||
this this kernel supports.
|
||||
Decimal value of the lowest version of the userspace API
|
||||
this kernel supports.
|
||||
Users: https://github.com/ibm-capi/libcxl
|
||||
|
||||
|
||||
|
||||
87
Documentation/ABI/testing/sysfs-driver-ccp
Normal file
87
Documentation/ABI/testing/sysfs-driver-ccp
Normal file
@ -0,0 +1,87 @@
|
||||
What: /sys/bus/pci/devices/<BDF>/fused_part
|
||||
Date: June 2022
|
||||
KernelVersion: 5.19
|
||||
Contact: mario.limonciello@amd.com
|
||||
Description:
|
||||
The /sys/bus/pci/devices/<BDF>/fused_part file reports
|
||||
whether the CPU or APU has been fused to prevent tampering.
|
||||
0: Not fused
|
||||
1: Fused
|
||||
|
||||
What: /sys/bus/pci/devices/<BDF>/debug_lock_on
|
||||
Date: June 2022
|
||||
KernelVersion: 5.19
|
||||
Contact: mario.limonciello@amd.com
|
||||
Description:
|
||||
The /sys/bus/pci/devices/<BDF>/debug_lock_on reports
|
||||
whether the AMD CPU or APU has been unlocked for debugging.
|
||||
Possible values:
|
||||
0: Not locked
|
||||
1: Locked
|
||||
|
||||
What: /sys/bus/pci/devices/<BDF>/tsme_status
|
||||
Date: June 2022
|
||||
KernelVersion: 5.19
|
||||
Contact: mario.limonciello@amd.com
|
||||
Description:
|
||||
The /sys/bus/pci/devices/<BDF>/tsme_status file reports
|
||||
the status of transparent secure memory encryption on AMD systems.
|
||||
Possible values:
|
||||
0: Not active
|
||||
1: Active
|
||||
|
||||
What: /sys/bus/pci/devices/<BDF>/anti_rollback_status
|
||||
Date: June 2022
|
||||
KernelVersion: 5.19
|
||||
Contact: mario.limonciello@amd.com
|
||||
Description:
|
||||
The /sys/bus/pci/devices/<BDF>/anti_rollback_status file reports
|
||||
whether the PSP is enforcing rollback protection.
|
||||
Possible values:
|
||||
0: Not enforcing
|
||||
1: Enforcing
|
||||
|
||||
What: /sys/bus/pci/devices/<BDF>/rpmc_production_enabled
|
||||
Date: June 2022
|
||||
KernelVersion: 5.19
|
||||
Contact: mario.limonciello@amd.com
|
||||
Description:
|
||||
The /sys/bus/pci/devices/<BDF>/rpmc_production_enabled file reports
|
||||
whether Replay Protected Monotonic Counter support has been enabled.
|
||||
Possible values:
|
||||
0: Not enabled
|
||||
1: Enabled
|
||||
|
||||
What: /sys/bus/pci/devices/<BDF>/rpmc_spirom_available
|
||||
Date: June 2022
|
||||
KernelVersion: 5.19
|
||||
Contact: mario.limonciello@amd.com
|
||||
Description:
|
||||
The /sys/bus/pci/devices/<BDF>/rpmc_spirom_available file reports
|
||||
whether an Replay Protected Monotonic Counter supported SPI is installed
|
||||
on the system.
|
||||
Possible values:
|
||||
0: Not present
|
||||
1: Present
|
||||
|
||||
What: /sys/bus/pci/devices/<BDF>/hsp_tpm_available
|
||||
Date: June 2022
|
||||
KernelVersion: 5.19
|
||||
Contact: mario.limonciello@amd.com
|
||||
Description:
|
||||
The /sys/bus/pci/devices/<BDF>/hsp_tpm_available file reports
|
||||
whether the HSP TPM has been activated.
|
||||
Possible values:
|
||||
0: Not activated or present
|
||||
1: Activated
|
||||
|
||||
What: /sys/bus/pci/devices/<BDF>/rom_armor_enforced
|
||||
Date: June 2022
|
||||
KernelVersion: 5.19
|
||||
Contact: mario.limonciello@amd.com
|
||||
Description:
|
||||
The /sys/bus/pci/devices/<BDF>/rom_armor_enforced file reports
|
||||
whether RomArmor SPI protection is enforced.
|
||||
Possible values:
|
||||
0: Not enforced
|
||||
1: Enforced
|
||||
@ -158,9 +158,15 @@ Each key-value pair is shown in each line with following style::
|
||||
Boot Kernel With a Boot Config
|
||||
==============================
|
||||
|
||||
Since the boot configuration file is loaded with initrd, it will be added
|
||||
to the end of the initrd (initramfs) image file with padding, size,
|
||||
checksum and 12-byte magic word as below.
|
||||
There are two options to boot the kernel with bootconfig: attaching the
|
||||
bootconfig to the initrd image or embedding it in the kernel itself.
|
||||
|
||||
Attaching a Boot Config to Initrd
|
||||
---------------------------------
|
||||
|
||||
Since the boot configuration file is loaded with initrd by default,
|
||||
it will be added to the end of the initrd (initramfs) image file with
|
||||
padding, size, checksum and 12-byte magic word as below.
|
||||
|
||||
[initrd][bootconfig][padding][size(le32)][checksum(le32)][#BOOTCONFIG\n]
|
||||
|
||||
@ -196,6 +202,25 @@ To remove the config from the image, you can use -d option as below::
|
||||
Then add "bootconfig" on the normal kernel command line to tell the
|
||||
kernel to look for the bootconfig at the end of the initrd file.
|
||||
|
||||
Embedding a Boot Config into Kernel
|
||||
-----------------------------------
|
||||
|
||||
If you can not use initrd, you can also embed the bootconfig file in the
|
||||
kernel by Kconfig options. In this case, you need to recompile the kernel
|
||||
with the following configs::
|
||||
|
||||
CONFIG_BOOT_CONFIG_EMBED=y
|
||||
CONFIG_BOOT_CONFIG_EMBED_FILE="/PATH/TO/BOOTCONFIG/FILE"
|
||||
|
||||
``CONFIG_BOOT_CONFIG_EMBED_FILE`` requires an absolute path or a relative
|
||||
path to the bootconfig file from source tree or object tree.
|
||||
The kernel will embed it as the default bootconfig.
|
||||
|
||||
Just as when attaching the bootconfig to the initrd, you need ``bootconfig``
|
||||
option on the kernel command line to enable the embedded bootconfig.
|
||||
|
||||
Note that even if you set this option, you can override the embedded
|
||||
bootconfig by another bootconfig which attached to the initrd.
|
||||
|
||||
Kernel parameters via Boot Config
|
||||
=================================
|
||||
|
||||
@ -262,6 +262,28 @@ Which shows that the base frequency now increased from 2600 MHz at performance
|
||||
level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
|
||||
use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
|
||||
|
||||
Changing performance level via BMC Interface
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
It is possible to change SST-PP level using out of band (OOB) agent (Via some
|
||||
remote management console, through BMC "Baseboard Management Controller"
|
||||
interface). This mode is supported from the Sapphire Rapids processor
|
||||
generation. The kernel and tool change to support this mode is added to Linux
|
||||
kernel version 5.18. To enable this feature, kernel config
|
||||
"CONFIG_INTEL_HFI_THERMAL" is required. The minimum version of the tool
|
||||
is "v1.12" to support this feature, which is part of Linux kernel version 5.18.
|
||||
|
||||
To support such configuration, this tool can be used as a daemon. Add
|
||||
a command line option --oob::
|
||||
|
||||
# intel-speed-select --oob
|
||||
Intel(R) Speed Select Technology
|
||||
Executing on CPU model:143[0x8f]
|
||||
OOB mode is enabled and will run as daemon
|
||||
|
||||
In this mode the tool will online/offline CPUs based on the new performance
|
||||
level.
|
||||
|
||||
Check presence of other Intel(R) SST features
|
||||
---------------------------------------------
|
||||
|
||||
|
||||
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8186
|
||||
|
||||
maintainers:
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The devices provide clock gate control in different IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8186-imp_iic_wrap
|
||||
- mediatek,mt8186-mfgsys
|
||||
- mediatek,mt8186-wpesys
|
||||
- mediatek,mt8186-imgsys1
|
||||
- mediatek,mt8186-imgsys2
|
||||
- mediatek,mt8186-vdecsys
|
||||
- mediatek,mt8186-vencsys
|
||||
- mediatek,mt8186-camsys
|
||||
- mediatek,mt8186-camsys_rawa
|
||||
- mediatek,mt8186-camsys_rawb
|
||||
- mediatek,mt8186-mdpsys
|
||||
- mediatek,mt8186-ipesys
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
imp_iic_wrap: clock-controller@11017000 {
|
||||
compatible = "mediatek,mt8186-imp_iic_wrap";
|
||||
reg = <0x11017000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek System Clock Controller for MT8186
|
||||
|
||||
maintainers:
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The apmixedsys provides most of PLLs which generated from SoC 26m.
|
||||
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
|
||||
The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
|
||||
The mcusys provides mux control to select the clock source in AP MCU.
|
||||
The device nodes also provide the system control capacity for configuration.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8186-mcusys
|
||||
- mediatek,mt8186-topckgen
|
||||
- mediatek,mt8186-infracfg_ao
|
||||
- mediatek,mt8186-apmixedsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8186-topckgen", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Sumit Gupta <sumitg@nvidia.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
description: |+
|
||||
The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
|
||||
registers that initiate CPU frequency/voltage transitions.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "ccplex@([0-9a-f]+)$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra186-ccplex-cluster
|
||||
- nvidia,tegra234-ccplex-cluster
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the BPMP node that needs to be queried to get
|
||||
operating point data for all CPUs.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- nvidia,bpmp
|
||||
- status
|
||||
|
||||
examples:
|
||||
- |
|
||||
ccplex@e000000 {
|
||||
compatible = "nvidia,tegra234-ccplex-cluster";
|
||||
reg = <0x0e000000 0x5ffff>;
|
||||
nvidia,bpmp = <&bpmp>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: EN7523 Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Felix Fietkau <nbd@nbd.name>
|
||||
- John Crispin <nbd@nbd.name>
|
||||
|
||||
description: |
|
||||
This node defines the System Control Unit of the EN7523 SoC,
|
||||
a collection of registers configuring many different aspects of the SoC.
|
||||
|
||||
The clock driver uses it to read and configure settings of the
|
||||
PLL controller, which provides clocks for the CPU, the bus and
|
||||
other SoC internal peripherals.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify which clock they consume.
|
||||
|
||||
All these identifiers can be found in:
|
||||
[1]: <include/dt-bindings/clock/en7523-clk.h>.
|
||||
|
||||
The clocks are provided inside a system controller node.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: airoha,en7523-scu
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
"#clock-cells":
|
||||
description:
|
||||
The first cell indicates the clock number, see [1] for available
|
||||
clocks.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/en7523-clk.h>
|
||||
scu: system-controller@1fa20000 {
|
||||
compatible = "airoha,en7523-scu";
|
||||
reg = <0x1fa20000 0x400>,
|
||||
<0x1fb00000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -1,186 +1,2 @@
|
||||
This binding is a work-in-progress, and are based on some experimental
|
||||
work by benh[1].
|
||||
|
||||
Sources of clock signal can be represented by any node in the device
|
||||
tree. Those nodes are designated as clock providers. Clock consumer
|
||||
nodes use a phandle and clock specifier pair to connect clock provider
|
||||
outputs to clock inputs. Similar to the gpio specifiers, a clock
|
||||
specifier is an array of zero, one or more cells identifying the clock
|
||||
output on a device. The length of a clock specifier is defined by the
|
||||
value of a #clock-cells property in the clock provider node.
|
||||
|
||||
[1] https://patchwork.ozlabs.org/patch/31551/
|
||||
|
||||
==Clock providers==
|
||||
|
||||
Required properties:
|
||||
#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
|
||||
with a single clock output and 1 for nodes with multiple
|
||||
clock outputs.
|
||||
|
||||
Optional properties:
|
||||
clock-output-names: Recommended to be a list of strings of clock output signal
|
||||
names indexed by the first cell in the clock specifier.
|
||||
However, the meaning of clock-output-names is domain
|
||||
specific to the clock provider, and is only provided to
|
||||
encourage using the same meaning for the majority of clock
|
||||
providers. This format may not work for clock providers
|
||||
using a complex clock specifier format. In those cases it
|
||||
is recommended to omit this property and create a binding
|
||||
specific names property.
|
||||
|
||||
Clock consumer nodes must never directly reference
|
||||
the provider's clock-output-names property.
|
||||
|
||||
For example:
|
||||
|
||||
oscillator {
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "ckil", "ckih";
|
||||
};
|
||||
|
||||
- this node defines a device with two clock outputs, the first named
|
||||
"ckil" and the second named "ckih". Consumer nodes always reference
|
||||
clocks by index. The names should reflect the clock output signal
|
||||
names for the device.
|
||||
|
||||
clock-indices: If the identifying number for the clocks in the node
|
||||
is not linear from zero, then this allows the mapping of
|
||||
identifiers into the clock-output-names array.
|
||||
|
||||
For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
|
||||
|
||||
oscillator {
|
||||
compatible = "myclocktype";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <1>, <3>;
|
||||
clock-output-names = "clka", "clkb";
|
||||
}
|
||||
|
||||
This ensures we do not have any empty strings in clock-output-names
|
||||
|
||||
|
||||
==Clock consumers==
|
||||
|
||||
Required properties:
|
||||
clocks: List of phandle and clock specifier pairs, one pair
|
||||
for each clock input to the device. Note: if the
|
||||
clock provider specifies '0' for #clock-cells, then
|
||||
only the phandle portion of the pair will appear.
|
||||
|
||||
Optional properties:
|
||||
clock-names: List of clock input name strings sorted in the same
|
||||
order as the clocks property. Consumers drivers
|
||||
will use clock-names to match clock input names
|
||||
with clocks specifiers.
|
||||
clock-ranges: Empty property indicating that child nodes can inherit named
|
||||
clocks from this node. Useful for bus nodes to provide a
|
||||
clock to their children.
|
||||
|
||||
For example:
|
||||
|
||||
device {
|
||||
clocks = <&osc 1>, <&ref 0>;
|
||||
clock-names = "baud", "register";
|
||||
};
|
||||
|
||||
|
||||
This represents a device with two clock inputs, named "baud" and "register".
|
||||
The baud clock is connected to output 1 of the &osc device, and the register
|
||||
clock is connected to output 0 of the &ref.
|
||||
|
||||
==Example==
|
||||
|
||||
/* external oscillator */
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32678>;
|
||||
clock-output-names = "osc";
|
||||
};
|
||||
|
||||
/* phase-locked-loop device, generates a higher frequency clock
|
||||
* from the external oscillator reference */
|
||||
pll: pll@4c000 {
|
||||
compatible = "vendor,some-pll-interface"
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc 0>;
|
||||
clock-names = "ref";
|
||||
reg = <0x4c000 0x1000>;
|
||||
clock-output-names = "pll", "pll-switched";
|
||||
};
|
||||
|
||||
/* UART, using the low frequency oscillator for the baud clock,
|
||||
* and the high frequency switched PLL output for register
|
||||
* clocking */
|
||||
uart@a000 {
|
||||
compatible = "fsl,imx-uart";
|
||||
reg = <0xa000 0x1000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&osc 0>, <&pll 1>;
|
||||
clock-names = "baud", "register";
|
||||
};
|
||||
|
||||
This DT fragment defines three devices: an external oscillator to provide a
|
||||
low-frequency reference clock, a PLL device to generate a higher frequency
|
||||
clock signal, and a UART.
|
||||
|
||||
* The oscillator is fixed-frequency, and provides one clock output, named "osc".
|
||||
* The PLL is both a clock provider and a clock consumer. It uses the clock
|
||||
signal generated by the external oscillator, and provides two output signals
|
||||
("pll" and "pll-switched").
|
||||
* The UART has its baud clock connected the external oscillator and its
|
||||
register clock connected to the PLL clock (the "pll-switched" signal)
|
||||
|
||||
==Assigned clock parents and rates==
|
||||
|
||||
Some platforms may require initial configuration of default parent clocks
|
||||
and clock frequencies. Such a configuration can be specified in a device tree
|
||||
node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
|
||||
properties. The assigned-clock-parents property should contain a list of parent
|
||||
clocks in the form of a phandle and clock specifier pair and the
|
||||
assigned-clock-rates property should contain a list of frequencies in Hz. Both
|
||||
these properties should correspond to the clocks listed in the assigned-clocks
|
||||
property.
|
||||
|
||||
To skip setting parent or rate of a clock its corresponding entry should be
|
||||
set to 0, or can be omitted if it is not followed by any non-zero entry.
|
||||
|
||||
uart@a000 {
|
||||
compatible = "fsl,imx-uart";
|
||||
reg = <0xa000 0x1000>;
|
||||
...
|
||||
clocks = <&osc 0>, <&pll 1>;
|
||||
clock-names = "baud", "register";
|
||||
|
||||
assigned-clocks = <&clkcon 0>, <&pll 2>;
|
||||
assigned-clock-parents = <&pll 2>;
|
||||
assigned-clock-rates = <0>, <460800>;
|
||||
};
|
||||
|
||||
In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
|
||||
the <&pll 2> clock is assigned a frequency value of 460800 Hz.
|
||||
|
||||
Configuring a clock's parent and rate through the device node that consumes
|
||||
the clock can be done only for clocks that have a single user. Specifying
|
||||
conflicting parent or rate configuration in multiple consumer nodes for
|
||||
a shared clock is forbidden.
|
||||
|
||||
Configuration of common clocks, which affect multiple consumer devices can
|
||||
be similarly specified in the clock provider node.
|
||||
|
||||
==Protected clocks==
|
||||
|
||||
Some platforms or firmwares may not fully expose all the clocks to the OS, such
|
||||
as in situations where those clks are used by drivers running in ARM secure
|
||||
execution levels. Such a configuration can be specified in device tree with the
|
||||
protected-clocks property in the form of a clock specifier list. This property should
|
||||
only be specified in the node that is providing the clocks being protected:
|
||||
|
||||
clock-controller@a000f000 {
|
||||
compatible = "vendor,clk95;
|
||||
reg = <0xa000f000 0x1000>
|
||||
#clocks-cells = <1>;
|
||||
...
|
||||
protected-clocks = <UART3_CLK>, <SPI5_CLK>;
|
||||
};
|
||||
This file has moved to the clock binding schema:
|
||||
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
|
||||
|
||||
@ -20,12 +20,10 @@ description: |
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8960.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8960.h
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8084
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
|
||||
@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on APQ8084.
|
||||
|
||||
See also::
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8084
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@fc400000 {
|
||||
compatible = "qcom,gcc-apq8084";
|
||||
reg = <0xfc400000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
128
Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
Normal file
128
Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
Normal file
@ -0,0 +1,128 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC8280xp.
|
||||
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,gcc-sc8280xp.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc8280xp
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO reference clock
|
||||
- description: Sleep clock
|
||||
- description: UFS memory first RX symbol clock
|
||||
- description: UFS memory second RX symbol clock
|
||||
- description: UFS memory first TX symbol clock
|
||||
- description: UFS card first RX symbol clock
|
||||
- description: UFS card second RX symbol clock
|
||||
- description: UFS card first TX symbol clock
|
||||
- description: Primary USB SuperSpeed pipe clock
|
||||
- description: USB4 PHY pipegmux clock source
|
||||
- description: USB4 PHY DP gmux clock source
|
||||
- description: USB4 PHY sys piegmux clock source
|
||||
- description: USB4 PHY PCIe pipe clock
|
||||
- description: USB4 PHY router max pipe clock
|
||||
- description: Primary USB4 RX0 clock
|
||||
- description: Primary USB4 RX1 clock
|
||||
- description: Secondary USB SuperSpeed pipe clock
|
||||
- description: Second USB4 PHY pipegmux clock source
|
||||
- description: Second USB4 PHY DP gmux clock source
|
||||
- description: Second USB4 PHY sys pipegmux clock source
|
||||
- description: Second USB4 PHY PCIe pipe clock
|
||||
- description: Second USB4 PHY router max pipe clock
|
||||
- description: Secondary USB4 RX0 clock
|
||||
- description: Secondary USB4 RX1 clock
|
||||
- description: Multiport USB first SupserSpeed pipe clock
|
||||
- description: Multiport USB second SuperSpeed pipe clock
|
||||
- description: PCIe 2a pipe clock
|
||||
- description: PCIe 2b pipe clock
|
||||
- description: PCIe 3a pipe clock
|
||||
- description: PCIe 3b pipe clock
|
||||
- description: PCIe 4 pipe clock
|
||||
- description: First EMAC controller reference clock
|
||||
- description: Second EMAC controller reference clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
maxItems: 389
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc8280xp";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&ufs_phy_rx_symbol_0_clk>,
|
||||
<&ufs_phy_rx_symbol_1_clk>,
|
||||
<&ufs_phy_tx_symbol_0_clk>,
|
||||
<&ufs_card_rx_symbol_0_clk>,
|
||||
<&ufs_card_rx_symbol_1_clk>,
|
||||
<&ufs_card_tx_symbol_0_clk>,
|
||||
<&usb_0_ssphy>,
|
||||
<&gcc_usb4_phy_pipegmux_clk_src>,
|
||||
<&gcc_usb4_phy_dp_gmux_clk_src>,
|
||||
<&gcc_usb4_phy_sys_pipegmux_clk_src>,
|
||||
<&usb4_phy_gcc_usb4_pcie_pipe_clk>,
|
||||
<&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
|
||||
<&qusb4phy_gcc_usb4_rx0_clk>,
|
||||
<&qusb4phy_gcc_usb4_rx1_clk>,
|
||||
<&usb_1_ssphy>,
|
||||
<&gcc_usb4_1_phy_pipegmux_clk_src>,
|
||||
<&gcc_usb4_1_phy_dp_gmux_clk_src>,
|
||||
<&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
|
||||
<&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
|
||||
<&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
|
||||
<&qusb4phy_1_gcc_usb4_rx0_clk>,
|
||||
<&qusb4phy_1_gcc_usb4_rx1_clk>,
|
||||
<&usb_2_ssphy>,
|
||||
<&usb_3_ssphy>,
|
||||
<&pcie2a_lane>,
|
||||
<&pcie2b_lane>,
|
||||
<&pcie3a_lane>,
|
||||
<&pcie3b_lane>,
|
||||
<&pcie4_lane>,
|
||||
<&rxc0_ref_clk>,
|
||||
<&rxc1_ref_clk>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -1,63 +0,0 @@
|
||||
Qualcomm RPM Clock Controller Binding
|
||||
------------------------------------------------
|
||||
The RPM is a dedicated hardware engine for managing the shared
|
||||
SoC resources in order to keep the lowest power profile. It
|
||||
communicates with other hardware subsystems via shared memory
|
||||
and accepts clock requests, aggregates the requests and turns
|
||||
the clocks on/off or scales them on demand.
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following. The generic
|
||||
compatible "qcom,rpmcc" should be also included.
|
||||
|
||||
"qcom,rpmcc-mdm9607", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8660", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8060", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8226", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8936", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8953", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8976", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
"qcom,rpmcc-ipq806x", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8992",·"qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8994",·"qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8998", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcm2290", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcs404", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sdm660", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sm6115", "qcom,rpmcc"
|
||||
"qcom,rpmcc-sm6125", "qcom,rpmcc"
|
||||
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h>
|
||||
and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock
|
||||
is an "active" clock, which means that the consumer only care that the
|
||||
clock is available when the apps CPU subsystem is active, i.e. not
|
||||
suspended or in deep idle. If it is important that the clock keeps running
|
||||
during system suspend, you need to specify the non-active clock, the one
|
||||
not containing *_A_* in the enumerator name.
|
||||
|
||||
Example:
|
||||
smd {
|
||||
compatible = "qcom,smd";
|
||||
|
||||
rpm {
|
||||
interrupts = <0 168 1>;
|
||||
qcom,ipc = <&apcs 8 0>;
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests {
|
||||
compatible = "qcom,rpm-msm8916";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
rpmcc: clock-controller {
|
||||
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
75
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
Normal file
75
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
Normal file
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,rpmcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm RPM Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description: |
|
||||
The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and
|
||||
come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is
|
||||
an "active" clock, which means that the consumer only care that the clock is
|
||||
available when the apps CPU subsystem is active, i.e. not suspended or in
|
||||
deep idle. If it is important that the clock keeps running during system
|
||||
suspend, you need to specify the non-active clock, the one not containing
|
||||
*_A_* in the enumerator name.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,rpmcc-apq8060
|
||||
- qcom,rpmcc-apq8064
|
||||
- qcom,rpmcc-ipq806x
|
||||
- qcom,rpmcc-mdm9607
|
||||
- qcom,rpmcc-msm8226
|
||||
- qcom,rpmcc-msm8660
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
- qcom,rpmcc-msm8974
|
||||
- qcom,rpmcc-msm8976
|
||||
- qcom,rpmcc-msm8992
|
||||
- qcom,rpmcc-msm8994
|
||||
- qcom,rpmcc-msm8996
|
||||
- qcom,rpmcc-msm8998
|
||||
- qcom,rpmcc-qcm2290
|
||||
- qcom,rpmcc-qcs404
|
||||
- qcom,rpmcc-sdm660
|
||||
- qcom,rpmcc-sm6115
|
||||
- qcom,rpmcc-sm6125
|
||||
- const: qcom,rpmcc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xo
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
rpm {
|
||||
rpm-requests {
|
||||
compatible = "qcom,rpm-msm8916";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
clock-controller {
|
||||
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -49,6 +49,7 @@ properties:
|
||||
- renesas,r8a77995-cpg-mssr # R-Car D3
|
||||
- renesas,r8a779a0-cpg-mssr # R-Car V3U
|
||||
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
|
||||
- renesas,r8a779g0-cpg-mssr # R-Car V4H
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -39,6 +39,17 @@ properties:
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^dma-router@[a-f0-9]+$":
|
||||
type: object
|
||||
$ref: "../dma/renesas,rzn1-dmamux.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -4,14 +4,15 @@
|
||||
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
|
||||
title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
|
||||
Standby Mode share the same register block.
|
||||
On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
|
||||
Standby Mode share the same register block. On RZ/V2M, the functionality is
|
||||
similar, but does not have Clock Monitor Registers.
|
||||
|
||||
They provide the following functionalities:
|
||||
- The CPG block generates various core clocks,
|
||||
@ -23,8 +24,10 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-cpg # RZ/V2L
|
||||
- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
|
||||
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-cpg # RZ/V2L
|
||||
- renesas,r9a09g011-cpg # RZ/V2M
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -42,9 +45,10 @@ properties:
|
||||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/r9a07g*-cpg.h>
|
||||
<dt-bindings/clock/r9a0*-cpg.h>
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
|
||||
<dt-bindings/clock/r9a09g011-cpg.h>.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
@ -58,7 +62,7 @@ properties:
|
||||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the module number, as defined in
|
||||
the <dt-bindings/clock/r9a07g0*-cpg.h>.
|
||||
the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
|
||||
@ -1,70 +0,0 @@
|
||||
* Rockchip PX30 Clock and Reset Unit
|
||||
|
||||
The PX30 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
|
||||
- compatible: CRU should be "rockchip,px30-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- clocks: A list of phandle + clock-specifier pairs for the clocks listed
|
||||
in clock-names
|
||||
- clock-names: Should contain the following:
|
||||
- "xin24m" for both PMUCRU and CRU
|
||||
- "gpll" for CRU (sourced from PMUCRU)
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "i2sx_clkin" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
pmucru: clock-controller@ff2bc000 {
|
||||
compatible = "rockchip,px30-pmucru";
|
||||
reg = <0x0 0xff2bc000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@ff2b0000 {
|
||||
compatible = "rockchip,px30-cru";
|
||||
reg = <0x0 0xff2b0000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff030000 {
|
||||
compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xff030000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
119
Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml
Normal file
119
Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml
Normal file
@ -0,0 +1,119 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip PX30 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The PX30 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "i2sx_clkin" - external I2S clock - optional
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,px30-cru
|
||||
- rockchip,px30-pmucru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Clock for both PMUCRU and CRU
|
||||
- description: Clock for CRU (sourced from PMUCRU)
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: xin24m
|
||||
- const: gpll
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: rockchip,px30-cru
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/px30-cru.h>
|
||||
|
||||
pmucru: clock-controller@ff2bc000 {
|
||||
compatible = "rockchip,px30-pmucru";
|
||||
reg = <0xff2bc000 0x1000>;
|
||||
clocks = <&xin24m>;
|
||||
clock-names = "xin24m";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@ff2b0000 {
|
||||
compatible = "rockchip,px30-cru";
|
||||
reg = <0xff2b0000 0x1000>;
|
||||
clocks = <&xin24m>, <&pmucru PLL_GPLL>;
|
||||
clock-names = "xin24m", "gpll";
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,56 +0,0 @@
|
||||
* Rockchip RK3036 Clock and Reset Unit
|
||||
|
||||
The RK3036 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3036-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "rmii_clkin" - external EMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@20060000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20060000 0x100>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3036 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3036 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "rmii_clkin" - external EMAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3036-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3036-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,61 +0,0 @@
|
||||
* Rockchip RK3188/RK3066 Clock and Reset Unit
|
||||
|
||||
The RK3188/RK3066 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
|
||||
"rockchip,rk3066a-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
|
||||
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
|
||||
Similar macros exist for the reset sources in these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "xin27m" - 27mhz crystal input on rk3066 - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_cif0" - external camera clock - optional,
|
||||
- "ext_rmii" - external RMII clock - optional,
|
||||
- "ext_jtag" - externalJTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3188/RK3066 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
|
||||
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
|
||||
Similar macros exist for the reset sources in these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - RTC clock - optional
|
||||
- "xin27m" - 27mhz crystal input on RK3066 - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "ext_cif0" - external camera clock - optional
|
||||
- "ext_rmii" - external RMII clock - optional
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3066a-cru
|
||||
- rockchip,rk3188-cru
|
||||
- rockchip,rk3188a-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,58 +0,0 @@
|
||||
* Rockchip RK3228 Clock and Reset Unit
|
||||
|
||||
The RK3228 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3228-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10110000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10110000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3228 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3228 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3228-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,67 +0,0 @@
|
||||
* Rockchip RK3288 Clock and Reset Unit
|
||||
|
||||
The RK3288 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
A revision of this SoC is available: rk3288w. The clock tree is a bit
|
||||
different so another dt-compatible is available. Noticed that it is only
|
||||
setting the difference but there is no automatic revision detection. This
|
||||
should be performed by bootloaders.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
|
||||
case of this revision of Rockchip rk3288.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_edp_24m" - external display port clock - optional,
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3188-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@ -0,0 +1,85 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3288 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3288 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
A revision of this SoC is available: rk3288w. The clock tree is a bit
|
||||
different so another dt-compatible is available. Noticed that it is only
|
||||
setting the difference but there is no automatic revision detection. This
|
||||
should be performed by boot loaders.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_edp_24m" - external display port clock - optional,
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3288-cru
|
||||
- rockchip,rk3288w-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3288-cru";
|
||||
reg = <0xff760000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,60 +0,0 @@
|
||||
* Rockchip RK3308 Clock and Reset Unit
|
||||
|
||||
The RK3308 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: CRU should be "rockchip,rk3308-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
|
||||
"mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
|
||||
"mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
|
||||
- "mac_clkin" - external MAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: clock-controller@ff500000 {
|
||||
compatible = "rockchip,rk3308-cru";
|
||||
reg = <0x0 0xff500000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff0a0000 {
|
||||
compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xff0a0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3308 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3308 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in",
|
||||
"mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in",
|
||||
"mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or
|
||||
SPDIF clock - optional
|
||||
- "mac_clkin" - external MAC clock - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3308-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff500000 {
|
||||
compatible = "rockchip,rk3308-cru";
|
||||
reg = <0xff500000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,61 +0,0 @@
|
||||
* Rockchip RK3368 Clock and Reset Unit
|
||||
|
||||
The RK3368 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3368-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional,
|
||||
- "ext_isp" - external ISP clock - optional,
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
- "ext_vip" - external VIP clock - optional,
|
||||
- "usbotg_out" - output clock of the pll in the otg phy
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3368-cru";
|
||||
reg = <0x0 0xff760000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3368 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3368 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "xin32k" - rtc clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "ext_hsadc" - external HSADC clock - optional
|
||||
- "ext_isp" - external ISP clock - optional
|
||||
- "ext_jtag" - external JTAG clock - optional
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "usbotg_out" - output clock of the pll in the otg phy
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3368-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3368-cru";
|
||||
reg = <0xff760000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Rockchip RK3399 Clock and Reset Unit
|
||||
|
||||
maintainers:
|
||||
- Xing Zheng <zhengxing@rock-chips.com>
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
@ -22,11 +22,11 @@ description: |
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
|
||||
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
|
||||
|
||||
@ -46,24 +46,15 @@ properties:
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
|
||||
assigned-clocks:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
assigned-clock-parents:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
assigned-clock-rates:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
phandle to the syscon managing the "general register files". It is used
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files". It is used
|
||||
for GRF muxes, if missing any muxes present in the GRF will not be
|
||||
available.
|
||||
|
||||
@ -77,7 +68,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pmucru: pmu-clock-controller@ff750000 {
|
||||
pmucru: clock-controller@ff750000 {
|
||||
compatible = "rockchip,rk3399-pmucru";
|
||||
reg = <0xff750000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
@ -34,6 +34,19 @@ properties:
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -1,59 +0,0 @@
|
||||
* Rockchip RV1108 Clock and Reset Unit
|
||||
|
||||
The RV1108 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rv1108-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "hdmiphy" - external clock input derived from HDMI PHY - optional
|
||||
- "usbphy" - external clock input derived from USB PHY - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20200000 {
|
||||
compatible = "rockchip,rv1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@10230000 {
|
||||
compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
|
||||
reg = <0x10230000 0x100>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RV1108 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RV1108 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required
|
||||
- "ext_vip" - external VIP clock - optional
|
||||
- "ext_i2s" - external I2S clock - optional
|
||||
- "ext_gmac" - external GMAC clock - optional
|
||||
- "hdmiphy" - external clock input derived from HDMI PHY - optional
|
||||
- "usbphy" - external clock input derived from USB PHY - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rv1108-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20200000 {
|
||||
compatible = "rockchip,rv1108-cru";
|
||||
reg = <0x20200000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -41,6 +41,7 @@ description: |
|
||||
|
||||
The list of valid indices for STM32MP1 is available in:
|
||||
include/dt-bindings/reset-controller/stm32mp1-resets.h
|
||||
include/dt-bindings/reset-controller/stm32mp13-resets.h
|
||||
|
||||
This file implements defines like:
|
||||
#define LTDC_R 3072
|
||||
@ -57,6 +58,7 @@ properties:
|
||||
- enum:
|
||||
- st,stm32mp1-rcc-secure
|
||||
- st,stm32mp1-rcc
|
||||
- st,stm32mp13-rcc
|
||||
- const: syscon
|
||||
clocks: true
|
||||
clock-names: true
|
||||
|
||||
@ -109,6 +109,25 @@ properties:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
clkout-clock:
|
||||
description: A subnode with three clock cells for externally routed clocks,
|
||||
output clocks. These are two PRCMU-internal clocks that can be divided and
|
||||
muxed out on the pads of the DB8500 SoC.
|
||||
type: object
|
||||
|
||||
properties:
|
||||
'#clock-cells':
|
||||
description:
|
||||
The first cell indicates which output clock we are using,
|
||||
possible values are 0 (CLKOUT1) and 1 (CLKOUT2).
|
||||
The second cell indicates which clock we want to use as source,
|
||||
possible values are 0 thru 7, see the defines for the different
|
||||
source clocks.
|
||||
The third cell is a divider, legal values are 1 thru 63.
|
||||
const: 3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -119,3 +138,41 @@ required:
|
||||
- smp-twd-clock
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/ste-db8500-clkout.h>
|
||||
clocks@8012 {
|
||||
compatible = "stericsson,u8500-clks";
|
||||
reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
|
||||
<0x8000f000 0x1000>, <0xa03ff000 0x1000>,
|
||||
<0xa03cf000 0x1000>;
|
||||
|
||||
prcmu_clk: prcmu-clock {
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
prcc_pclk: prcc-periph-clock {
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
prcc_kclk: prcc-kernel-clock {
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
prcc_reset: prcc-reset-controller {
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
|
||||
rtc_clk: rtc32k-clock {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
smp_twd_clk: smp-twd-clock {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
clkout_clk: clkout-clock {
|
||||
#clock-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -15,6 +15,7 @@ properties:
|
||||
- enum:
|
||||
- ti,am654-ehrpwm-tbclk
|
||||
- ti,am64-epwm-tbclk
|
||||
- ti,am62-epwm-tbclk
|
||||
- const: syscon
|
||||
|
||||
"#clock-cells":
|
||||
|
||||
@ -20,6 +20,13 @@ Optional properties:
|
||||
Vsram to fit SoC specific needs. When absent, the voltage scaling
|
||||
flow is handled by hardware, hence no software "voltage tracking" is
|
||||
needed.
|
||||
- mediatek,cci:
|
||||
Used to confirm the link status between cpufreq and mediatek cci. Because
|
||||
cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
|
||||
To prevent the issue of high frequency and low voltage, we need to use this
|
||||
property to make sure mediatek cci is ready.
|
||||
For details of mediatek cci, please refer to
|
||||
Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
|
||||
- #cooling-cells:
|
||||
For details, please refer to
|
||||
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
|
||||
|
||||
@ -15,6 +15,7 @@ properties:
|
||||
- ti,j721e-sa2ul
|
||||
- ti,am654-sa2ul
|
||||
- ti,am64-sa2ul
|
||||
- ti,am62-sa3ul
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -20,9 +20,11 @@ properties:
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: allwinner,sun50i-a64-dma
|
||||
- const: allwinner,sun50i-a100-dma
|
||||
- const: allwinner,sun50i-h6-dma
|
||||
- enum:
|
||||
- allwinner,sun20i-d1-dma
|
||||
- allwinner,sun50i-a64-dma
|
||||
- allwinner,sun50i-a100-dma
|
||||
- allwinner,sun50i-h6-dma
|
||||
- items:
|
||||
- const: allwinner,sun8i-r40-dma
|
||||
- const: allwinner,sun50i-a64-dma
|
||||
@ -58,6 +60,7 @@ if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun20i-d1-dma
|
||||
- allwinner,sun50i-a100-dma
|
||||
- allwinner,sun50i-h6-dma
|
||||
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Altera mSGDMA IP core
|
||||
|
||||
maintainers:
|
||||
- Olivier Dautricourt <olivier.dautricourt@orolia.com>
|
||||
- Olivier Dautricourt <olivierdautricourt@gmail.com>
|
||||
|
||||
description: |
|
||||
Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
|
||||
|
||||
@ -55,6 +55,9 @@ properties:
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
@ -10,10 +10,12 @@ Required properties:
|
||||
or one irq for pdma device
|
||||
|
||||
Optional properties:
|
||||
- #dma-channels: Number of DMA channels supported by the controller (defaults
|
||||
- dma-channels: Number of DMA channels supported by the controller (defaults
|
||||
to 32 when not specified)
|
||||
- #dma-requests: Number of DMA requestor lines supported by the controller
|
||||
- #dma-channels: deprecated
|
||||
- dma-requests: Number of DMA requestor lines supported by the controller
|
||||
(defaults to 32 when not specified)
|
||||
- #dma-requests: deprecated
|
||||
|
||||
"marvell,pdma-1.0"
|
||||
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
|
||||
@ -33,7 +35,7 @@ pdma: dma-controller@d4000000 {
|
||||
reg = <0xd4000000 0x10000>;
|
||||
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
interrupt-parent = <&intcmux32>;
|
||||
#dma-channels = <16>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -45,7 +47,7 @@ pdma: dma-controller@d4000000 {
|
||||
compatible = "marvell,pdma-1.0";
|
||||
reg = <0xd4000000 0x10000>;
|
||||
interrupts = <47>;
|
||||
#dma-channels = <16>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,110 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
|
||||
|
||||
description: |
|
||||
The Tegra General Purpose Central (GPC) DMA controller is used for faster
|
||||
data transfers between memory to memory, memory to device and device to
|
||||
memory.
|
||||
|
||||
maintainers:
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Rajesh Gumasta <rgumasta@nvidia.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "dma-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra186-gpcdma
|
||||
- items:
|
||||
- const: nvidia,tegra194-gpcdma
|
||||
- const: nvidia,tegra186-gpcdma
|
||||
|
||||
"#dma-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Should contain all of the per-channel DMA interrupts in
|
||||
ascending order with respect to the DMA channel index.
|
||||
minItems: 1
|
||||
maxItems: 31
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: gpcdma
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
- "#dma-cells"
|
||||
- iommus
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
dma-controller@2600000 {
|
||||
compatible = "nvidia,tegra186-gpcdma";
|
||||
reg = <0x2600000 0x210000>;
|
||||
resets = <&bpmp TEGRA186_RESET_GPCDMA>;
|
||||
reset-names = "gpcdma";
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
|
||||
dma-coherent;
|
||||
};
|
||||
...
|
||||
@ -19,9 +19,12 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7280-gpi-dma
|
||||
- qcom,sdm845-gpi-dma
|
||||
- qcom,sm8150-gpi-dma
|
||||
- qcom,sm8250-gpi-dma
|
||||
- qcom,sm8350-gpi-dma
|
||||
- qcom,sm8450-gpi-dma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -42,11 +42,10 @@ properties:
|
||||
- const: renesas,rcar-dmac
|
||||
|
||||
- items:
|
||||
- const: renesas,dmac-r8a779a0 # R-Car V3U
|
||||
|
||||
- items:
|
||||
- const: renesas,dmac-r8a779f0 # R-Car S4-8
|
||||
- const: renesas,rcar-gen4-dmac
|
||||
- enum:
|
||||
- renesas,dmac-r8a779a0 # R-Car V3U
|
||||
- renesas,dmac-r8a779f0 # R-Car S4-8
|
||||
- const: renesas,rcar-gen4-dmac # R-Car Gen4
|
||||
|
||||
reg: true
|
||||
|
||||
@ -121,7 +120,6 @@ if:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,dmac-r8a779a0
|
||||
- renesas,rcar-gen4-dmac
|
||||
then:
|
||||
properties:
|
||||
|
||||
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/N1 DMA mux
|
||||
|
||||
maintainers:
|
||||
- Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "dma-router.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,rzn1-dmamux
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: DMA mux first register offset within the system control parent.
|
||||
|
||||
'#dma-cells':
|
||||
const: 6
|
||||
description:
|
||||
The first four cells are dedicated to the master DMA controller. The fifth
|
||||
cell gives the DMA mux bit index that must be set starting from 0. The
|
||||
sixth cell gives the binary value that must be written there, ie. 0 or 1.
|
||||
|
||||
dma-masters:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
dma-requests:
|
||||
const: 32
|
||||
|
||||
required:
|
||||
- reg
|
||||
- dma-requests
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
dma-router@a0 {
|
||||
compatible = "renesas,rzn1-dmamux";
|
||||
reg = <0xa0 4>;
|
||||
#dma-cells = <6>;
|
||||
dma-masters = <&dma0 &dma1>;
|
||||
dma-requests = <32>;
|
||||
};
|
||||
@ -28,7 +28,15 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: sifive,fu540-c000-pdma
|
||||
- enum:
|
||||
- sifive,fu540-c000-pdma
|
||||
- const: sifive,pdma0
|
||||
description:
|
||||
Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
|
||||
Supported compatible strings are -
|
||||
"sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
|
||||
SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
|
||||
with no chip integration tweaks.
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -37,6 +45,12 @@ properties:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
dma-channels:
|
||||
description: For backwards-compatibility, the default value is 4
|
||||
minimum: 1
|
||||
maximum: 4
|
||||
default: 4
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
|
||||
@ -50,8 +64,9 @@ unevaluatedProperties: false
|
||||
examples:
|
||||
- |
|
||||
dma-controller@3000000 {
|
||||
compatible = "sifive,fu540-c000-pdma";
|
||||
compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
|
||||
reg = <0x3000000 0x8000>;
|
||||
dma-channels = <4>;
|
||||
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
@ -15,7 +15,13 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: snps,dma-spear1340
|
||||
oneOf:
|
||||
- const: snps,dma-spear1340
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a06g032-dma
|
||||
- const: renesas,rzn1-dma
|
||||
|
||||
|
||||
"#dma-cells":
|
||||
minimum: 3
|
||||
|
||||
@ -8,10 +8,13 @@ Required properties:
|
||||
- interrupts: Should contain one interrupt shared by all channel.
|
||||
- #dma-cells: must be <1>. Used to represent the number of integer
|
||||
cells in the dmas property of client device.
|
||||
- #dma-channels : Number of DMA channels supported. Should be 32.
|
||||
- dma-channels : Number of DMA channels supported. Should be 32.
|
||||
- clock-names: Should contain the clock of the DMA controller.
|
||||
- clocks: Should contain a clock specifier for each entry in clock-names.
|
||||
|
||||
Deprecated properties:
|
||||
- #dma-channels : Number of DMA channels supported. Should be 32.
|
||||
|
||||
Example:
|
||||
|
||||
Controller:
|
||||
@ -20,7 +23,7 @@ apdma: dma-controller@20100000 {
|
||||
reg = <0x20100000 0x4000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <32>;
|
||||
dma-channels = <32>;
|
||||
clock-names = "enable";
|
||||
clocks = <&clk_ap_ahb_gates 5>;
|
||||
};
|
||||
|
||||
@ -110,7 +110,11 @@ axi_vdma_0: axivdma@40030000 {
|
||||
Required properties:
|
||||
- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
|
||||
where Channel ID is '0' for write/tx and '1' for read/rx
|
||||
channel.
|
||||
channel. For MCMDA, MM2S channel(write/tx) ID start from
|
||||
'0' and is in [0-15] range. S2MM channel(read/rx) ID start
|
||||
from '16' and is in [16-31] range. These channels ID are
|
||||
fixed irrespective of IP configuration.
|
||||
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
|
||||
@ -46,11 +46,11 @@ properties:
|
||||
- renesas,i2c-r8a77980 # R-Car V3H
|
||||
- renesas,i2c-r8a77990 # R-Car E3
|
||||
- renesas,i2c-r8a77995 # R-Car D3
|
||||
- renesas,i2c-r8a779a0 # R-Car V3U
|
||||
- const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,i2c-r8a779a0 # R-Car V3U
|
||||
- renesas,i2c-r8a779f0 # R-Car S4-8
|
||||
- const: renesas,rcar-gen4-i2c # R-Car Gen4
|
||||
|
||||
|
||||
@ -18,10 +18,20 @@ properties:
|
||||
- items:
|
||||
- const: allwinner,sun50i-a64-lradc
|
||||
- const: allwinner,sun8i-a83t-r-lradc
|
||||
- const: allwinner,sun50i-r329-lradc
|
||||
- items:
|
||||
- const: allwinner,sun20i-d1-lradc
|
||||
- const: allwinner,sun50i-r329-lradc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
@ -68,6 +78,18 @@ required:
|
||||
- interrupts
|
||||
- vref-supply
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- allwinner,sun50i-r329-lradc
|
||||
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
960
Documentation/devicetree/bindings/input/azoteq,iqs7222.yaml
Normal file
960
Documentation/devicetree/bindings/input/azoteq,iqs7222.yaml
Normal file
@ -0,0 +1,960 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/azoteq,iqs7222.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Azoteq IQS7222A/B/C Capacitive Touch Controller
|
||||
|
||||
maintainers:
|
||||
- Jeff LaBundy <jeff@labundy.com>
|
||||
|
||||
description: |
|
||||
The Azoteq IQS7222A, IQS7222B and IQS7222C are multichannel capacitive touch
|
||||
controllers that feature additional sensing capabilities.
|
||||
|
||||
Link to datasheets: https://www.azoteq.com/
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- azoteq,iqs7222a
|
||||
- azoteq,iqs7222b
|
||||
- azoteq,iqs7222c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
irq-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
Specifies the GPIO connected to the device's active-low RDY output.
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
Specifies the GPIO connected to the device's active-low MCLR input. The
|
||||
device is temporarily held in hardware reset prior to initialization if
|
||||
this property is present.
|
||||
|
||||
azoteq,rf-filt-enable:
|
||||
type: boolean
|
||||
description: Enables the device's internal RF filter.
|
||||
|
||||
azoteq,max-counts:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
description: |
|
||||
Specifies the maximum number of conversion periods (counts) that can be
|
||||
reported as follows:
|
||||
0: 1023
|
||||
1: 2047
|
||||
2: 4095
|
||||
3: 16384
|
||||
|
||||
azoteq,auto-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
description: |
|
||||
Specifies the number of conversions to occur before an interrupt is
|
||||
generated as follows:
|
||||
0: 4
|
||||
1: 8
|
||||
2: 16
|
||||
3: 32
|
||||
|
||||
azoteq,ati-frac-div-fine:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the preloaded ATI fine fractional divider.
|
||||
|
||||
azoteq,ati-frac-div-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the preloaded ATI coarse fractional divider.
|
||||
|
||||
azoteq,ati-comp-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 1023
|
||||
description: Specifies the preloaded ATI compensation selection.
|
||||
|
||||
azoteq,lta-beta-lp:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Specifies the long-term average filter damping factor to be applied during
|
||||
low-power mode.
|
||||
|
||||
azoteq,lta-beta-np:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Specifies the long-term average filter damping factor to be applied during
|
||||
normal-power mode.
|
||||
|
||||
azoteq,counts-beta-lp:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Specifies the counts filter damping factor to be applied during low-power
|
||||
mode.
|
||||
|
||||
azoteq,counts-beta-np:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Specifies the counts filter damping factor to be applied during normal-
|
||||
power mode.
|
||||
|
||||
azoteq,lta-fast-beta-lp:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Specifies the long-term average filter fast damping factor to be applied
|
||||
during low-power mode.
|
||||
|
||||
azoteq,lta-fast-beta-np:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description:
|
||||
Specifies the long-term average filter fast damping factor to be applied
|
||||
during normal-power mode.
|
||||
|
||||
azoteq,timeout-ati-ms:
|
||||
multipleOf: 500
|
||||
minimum: 0
|
||||
maximum: 32767500
|
||||
description:
|
||||
Specifies the delay (in ms) before ATI is retried following an ATI error.
|
||||
|
||||
azoteq,rate-ati-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the rate (in ms) at which ATI status is evaluated.
|
||||
|
||||
azoteq,timeout-np-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait for an event before moving
|
||||
from normal-power mode to low-power mode.
|
||||
|
||||
azoteq,rate-np-ms:
|
||||
minimum: 0
|
||||
maximum: 3000
|
||||
description: Specifies the report rate (in ms) during normal-power mode.
|
||||
|
||||
azoteq,timeout-lp-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait for an event before moving
|
||||
from low-power mode to ultra-low-power mode.
|
||||
|
||||
azoteq,rate-lp-ms:
|
||||
minimum: 0
|
||||
maximum: 3000
|
||||
description: Specifies the report rate (in ms) during low-power mode.
|
||||
|
||||
azoteq,timeout-ulp-ms:
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the rate (in ms) at which channels not regularly sampled during
|
||||
ultra-low-power mode are updated.
|
||||
|
||||
azoteq,rate-ulp-ms:
|
||||
minimum: 0
|
||||
maximum: 3000
|
||||
description: Specifies the report rate (in ms) during ultra-low-power mode.
|
||||
|
||||
patternProperties:
|
||||
"^cycle-[0-9]$":
|
||||
type: object
|
||||
description: Represents a conversion cycle serving two sensing channels.
|
||||
|
||||
properties:
|
||||
azoteq,conv-period:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the cycle's conversion period.
|
||||
|
||||
azoteq,conv-frac:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the cycle's conversion frequency fraction.
|
||||
|
||||
azoteq,tx-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
description: Specifies the CTx pin(s) associated with the cycle.
|
||||
|
||||
azoteq,rx-float-inactive:
|
||||
type: boolean
|
||||
description: Floats any inactive CRx pins instead of grounding them.
|
||||
|
||||
azoteq,dead-time-enable:
|
||||
type: boolean
|
||||
description:
|
||||
Increases the denominator of the conversion frequency formula by one.
|
||||
|
||||
azoteq,tx-freq-fosc:
|
||||
type: boolean
|
||||
description:
|
||||
Fixes the conversion frequency to that of the device's core clock.
|
||||
|
||||
azoteq,vbias-enable:
|
||||
type: boolean
|
||||
description: Enables the bias voltage for use during inductive sensing.
|
||||
|
||||
azoteq,sense-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
description: |
|
||||
Specifies the cycle's sensing mode as follows:
|
||||
0: None
|
||||
1: Self capacitive
|
||||
2: Mutual capacitive
|
||||
3: Inductive
|
||||
|
||||
Note that in the case of IQS7222A, cycles 5 and 6 are restricted to
|
||||
Hall-effect sensing.
|
||||
|
||||
azoteq,iref-enable:
|
||||
type: boolean
|
||||
description:
|
||||
Enables the current reference for use during various sensing modes.
|
||||
|
||||
azoteq,iref-level:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the cycle's current reference level.
|
||||
|
||||
azoteq,iref-trim:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the cycle's current reference trim.
|
||||
|
||||
dependencies:
|
||||
azoteq,iref-level: ["azoteq,iref-enable"]
|
||||
azoteq,iref-trim: ["azoteq,iref-enable"]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
"^channel-([0-9]|1[0-9])$":
|
||||
type: object
|
||||
description:
|
||||
Represents a single sensing channel. A channel is active if defined and
|
||||
inactive otherwise.
|
||||
|
||||
Note that in the case of IQS7222A, channels 10 and 11 are restricted to
|
||||
Hall-effect sensing with events reported on channel 10 only.
|
||||
|
||||
properties:
|
||||
azoteq,ulp-allow:
|
||||
type: boolean
|
||||
description:
|
||||
Permits the device to enter ultra-low-power mode while the channel
|
||||
lies in a state of touch or proximity.
|
||||
|
||||
azoteq,ref-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 9
|
||||
description: Specifies a separate reference channel to be followed.
|
||||
|
||||
azoteq,ref-weight:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description: Specifies the relative weight of the reference channel.
|
||||
|
||||
azoteq,use-prox:
|
||||
type: boolean
|
||||
description:
|
||||
Activates the reference channel in response to proximity events
|
||||
instead of touch events.
|
||||
|
||||
azoteq,ati-band:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
description: |
|
||||
Specifies the channel's ATI band as a fraction of its ATI target as
|
||||
follows:
|
||||
0: 1/16
|
||||
1: 1/8
|
||||
2: 1/4
|
||||
3: 1/2
|
||||
|
||||
azoteq,global-halt:
|
||||
type: boolean
|
||||
description:
|
||||
Specifies that the channel's long-term average is to freeze if any
|
||||
other participating channel lies in a proximity or touch state.
|
||||
|
||||
azoteq,invert-enable:
|
||||
type: boolean
|
||||
description:
|
||||
Inverts the polarity of the states reported for proximity and touch
|
||||
events relative to their respective thresholds.
|
||||
|
||||
azoteq,dual-direction:
|
||||
type: boolean
|
||||
description:
|
||||
Specifies that the channel's long-term average is to freeze in the
|
||||
presence of either increasing or decreasing counts, thereby permit-
|
||||
ting events to be reported in either direction.
|
||||
|
||||
azoteq,rx-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description: Specifies the CRx pin(s) associated with the channel.
|
||||
|
||||
azoteq,samp-cap-double:
|
||||
type: boolean
|
||||
description: Doubles the sampling capacitance from 40 pF to 80 pF.
|
||||
|
||||
azoteq,vref-half:
|
||||
type: boolean
|
||||
description: Halves the discharge threshold from 1.0 V to 0.5 V.
|
||||
|
||||
azoteq,proj-bias:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
description: |
|
||||
Specifies the bias current applied during mutual (projected)
|
||||
capacitive sensing as follows:
|
||||
0: 2 uA
|
||||
1: 5 uA
|
||||
2: 7 uA
|
||||
3: 10 uA
|
||||
|
||||
azoteq,ati-target:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
multipleOf: 8
|
||||
minimum: 0
|
||||
maximum: 2040
|
||||
description: Specifies the channel's ATI target.
|
||||
|
||||
azoteq,ati-base:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
multipleOf: 16
|
||||
minimum: 0
|
||||
maximum: 496
|
||||
description: Specifies the channel's ATI base.
|
||||
|
||||
azoteq,ati-mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5]
|
||||
description: |
|
||||
Specifies the channel's ATI mode as follows:
|
||||
0: Disabled
|
||||
1: Compensation
|
||||
2: Compensation divider
|
||||
3: Fine fractional divider
|
||||
4: Coarse fractional divider
|
||||
5: Full
|
||||
|
||||
azoteq,ati-frac-div-fine:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the channel's ATI fine fractional divider.
|
||||
|
||||
azoteq,ati-frac-mult-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the channel's ATI coarse fractional multiplier.
|
||||
|
||||
azoteq,ati-frac-div-coarse:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the channel's ATI coarse fractional divider.
|
||||
|
||||
azoteq,ati-comp-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
description: Specifies the channel's ATI compensation divider.
|
||||
|
||||
azoteq,ati-comp-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 1023
|
||||
description: Specifies the channel's ATI compensation selection.
|
||||
|
||||
azoteq,debounce-enter:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the channel's debounce entrance factor.
|
||||
|
||||
azoteq,debounce-exit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
description: Specifies the channel's debounce exit factor.
|
||||
|
||||
patternProperties:
|
||||
"^event-(prox|touch)$":
|
||||
type: object
|
||||
description:
|
||||
Represents a proximity or touch event reported by the channel.
|
||||
|
||||
properties:
|
||||
azoteq,gpio-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 2
|
||||
description: |
|
||||
Specifies one or more GPIO mapped to the event as follows:
|
||||
0: GPIO0
|
||||
1: GPIO3 (IQS7222C only)
|
||||
2: GPIO4 (IQS7222C only)
|
||||
|
||||
Note that although multiple events can be mapped to a single
|
||||
GPIO, they must all be of the same type (proximity, touch or
|
||||
slider gesture).
|
||||
|
||||
azoteq,thresh:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Specifies the threshold for the event. Valid entries range from
|
||||
0-127 and 0-255 for proximity and touch events, respectively.
|
||||
|
||||
azoteq,hyst:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description:
|
||||
Specifies the hysteresis for the event (touch events only).
|
||||
|
||||
azoteq,timeout-press-ms:
|
||||
multipleOf: 500
|
||||
minimum: 0
|
||||
maximum: 127500
|
||||
description:
|
||||
Specifies the length of time (in ms) to wait before automatically
|
||||
releasing a press event. Specify zero to allow the press state to
|
||||
persist indefinitely.
|
||||
|
||||
The IQS7222B does not feature channel-specific timeouts; the time-
|
||||
out specified for any one channel applies to all channels.
|
||||
|
||||
linux,code:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Numeric key or switch code associated with the event. Specify
|
||||
KEY_RESERVED (0) to opt out of event reporting.
|
||||
|
||||
linux,input-type:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 5]
|
||||
default: 1
|
||||
description:
|
||||
Specifies whether the event is to be interpreted as a key (1)
|
||||
or a switch (5).
|
||||
|
||||
required:
|
||||
- linux,code
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
dependencies:
|
||||
azoteq,ref-weight: ["azoteq,ref-select"]
|
||||
azoteq,use-prox: ["azoteq,ref-select"]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
"^slider-[0-1]$":
|
||||
type: object
|
||||
description: Represents a slider comprising three or four channels.
|
||||
|
||||
properties:
|
||||
azoteq,channel-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 9
|
||||
description:
|
||||
Specifies the order of the channels that participate in the slider.
|
||||
|
||||
azoteq,slider-size:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the slider's one-dimensional resolution, equal to the
|
||||
maximum coordinate plus one.
|
||||
|
||||
azoteq,lower-cal:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the slider's lower starting point.
|
||||
|
||||
azoteq,upper-cal:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
description: Specifies the slider's upper starting point.
|
||||
|
||||
azoteq,top-speed:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 65535
|
||||
description:
|
||||
Specifies the speed of movement after which coordinate filtering is
|
||||
no longer applied.
|
||||
|
||||
azoteq,bottom-speed:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
multipleOf: 4
|
||||
minimum: 0
|
||||
maximum: 1020
|
||||
description:
|
||||
Specifies the speed of movement after which coordinate filtering is
|
||||
linearly reduced.
|
||||
|
||||
azoteq,bottom-beta:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
Specifies the coordinate filter damping factor to be applied
|
||||
while the speed of movement is below that which is specified
|
||||
by azoteq,bottom-speed.
|
||||
|
||||
azoteq,static-beta:
|
||||
type: boolean
|
||||
description:
|
||||
Applies the coordinate filter damping factor specified by
|
||||
azoteq,bottom-beta regardless of the speed of movement.
|
||||
|
||||
azoteq,use-prox:
|
||||
type: boolean
|
||||
description:
|
||||
Directs the slider to respond to the proximity states of the selected
|
||||
channels instead of their corresponding touch states. Note the slider
|
||||
cannot report granular coordinates during a state of proximity.
|
||||
|
||||
linux,axis:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Specifies the absolute axis to which coordinates are mapped. Specify
|
||||
ABS_WHEEL to operate the slider as a wheel (IQS7222C only).
|
||||
|
||||
patternProperties:
|
||||
"^event-(press|tap|(swipe|flick)-(pos|neg))$":
|
||||
type: object
|
||||
description:
|
||||
Represents a press or gesture (IQS7222A only) event reported by
|
||||
the slider.
|
||||
|
||||
properties:
|
||||
linux,code:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Numeric key code associated with the event.
|
||||
|
||||
azoteq,gesture-max-ms:
|
||||
multipleOf: 4
|
||||
minimum: 0
|
||||
maximum: 1020
|
||||
description:
|
||||
Specifies the length of time (in ms) within which a tap, swipe
|
||||
or flick gesture must be completed in order to be acknowledged
|
||||
by the device. The number specified for any one swipe or flick
|
||||
gesture applies to all remaining swipe or flick gestures.
|
||||
|
||||
azoteq,gesture-min-ms:
|
||||
multipleOf: 4
|
||||
minimum: 0
|
||||
maximum: 124
|
||||
description:
|
||||
Specifies the length of time (in ms) for which a tap gesture must
|
||||
be held in order to be acknowledged by the device.
|
||||
|
||||
azoteq,gesture-dist:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
multipleOf: 16
|
||||
minimum: 0
|
||||
maximum: 4080
|
||||
description:
|
||||
Specifies the distance across which a swipe or flick gesture must
|
||||
travel in order to be acknowledged by the device. The number spec-
|
||||
ified for any one swipe or flick gesture applies to all remaining
|
||||
swipe or flick gestures.
|
||||
|
||||
azoteq,gpio-select:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 0
|
||||
description: |
|
||||
Specifies an individual GPIO mapped to a tap, swipe or flick
|
||||
gesture as follows:
|
||||
0: GPIO0
|
||||
1: GPIO3 (reserved)
|
||||
2: GPIO4 (reserved)
|
||||
|
||||
Note that although multiple events can be mapped to a single
|
||||
GPIO, they must all be of the same type (proximity, touch or
|
||||
slider gesture).
|
||||
|
||||
required:
|
||||
- linux,code
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- azoteq,channel-select
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
"^gpio-[0-2]$":
|
||||
type: object
|
||||
description: |
|
||||
Represents a GPIO mapped to one or more events as follows:
|
||||
gpio-0: GPIO0
|
||||
gpio-1: GPIO3 (IQS7222C only)
|
||||
gpio-2: GPIO4 (IQS7222C only)
|
||||
|
||||
allOf:
|
||||
- $ref: ../pinctrl/pincfg-node.yaml#
|
||||
|
||||
properties:
|
||||
drive-open-drain: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: azoteq,iqs7222b
|
||||
|
||||
then:
|
||||
patternProperties:
|
||||
"^cycle-[0-9]$":
|
||||
properties:
|
||||
azoteq,iref-enable: false
|
||||
|
||||
"^channel-([0-9]|1[0-9])$":
|
||||
properties:
|
||||
azoteq,ref-select: false
|
||||
|
||||
patternProperties:
|
||||
"^event-(prox|touch)$":
|
||||
properties:
|
||||
azoteq,gpio-select: false
|
||||
|
||||
"^slider-[0-1]$": false
|
||||
|
||||
"^gpio-[0-2]$": false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: azoteq,iqs7222a
|
||||
|
||||
then:
|
||||
patternProperties:
|
||||
"^channel-([0-9]|1[0-9])$":
|
||||
patternProperties:
|
||||
"^event-(prox|touch)$":
|
||||
properties:
|
||||
azoteq,gpio-select:
|
||||
maxItems: 1
|
||||
items:
|
||||
maximum: 0
|
||||
|
||||
"^slider-[0-1]$":
|
||||
properties:
|
||||
azoteq,slider-size:
|
||||
multipleOf: 16
|
||||
maximum: 4080
|
||||
|
||||
azoteq,top-speed:
|
||||
multipleOf: 4
|
||||
maximum: 1020
|
||||
|
||||
else:
|
||||
patternProperties:
|
||||
"^channel-([0-9]|1[0-9])$":
|
||||
properties:
|
||||
azoteq,ulp-allow: false
|
||||
|
||||
"^slider-[0-1]$":
|
||||
patternProperties:
|
||||
"^event-(press|tap|(swipe|flick)-(pos|neg))$":
|
||||
properties:
|
||||
azoteq,gesture-max-ms: false
|
||||
|
||||
azoteq,gesture-min-ms: false
|
||||
|
||||
azoteq,gesture-dist: false
|
||||
|
||||
azoteq,gpio-select: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- irq-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
iqs7222a@44 {
|
||||
compatible = "azoteq,iqs7222a";
|
||||
reg = <0x44>;
|
||||
irq-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
|
||||
azoteq,lta-beta-lp = <7>;
|
||||
azoteq,lta-beta-np = <8>;
|
||||
azoteq,counts-beta-lp = <2>;
|
||||
azoteq,counts-beta-np = <3>;
|
||||
azoteq,lta-fast-beta-lp = <3>;
|
||||
azoteq,lta-fast-beta-np = <4>;
|
||||
|
||||
cycle-0 {
|
||||
azoteq,conv-period = <5>;
|
||||
azoteq,conv-frac = <127>;
|
||||
azoteq,tx-enable = <1>, <2>, <4>, <5>;
|
||||
azoteq,dead-time-enable;
|
||||
azoteq,sense-mode = <2>;
|
||||
};
|
||||
|
||||
cycle-1 {
|
||||
azoteq,conv-period = <5>;
|
||||
azoteq,conv-frac = <127>;
|
||||
azoteq,tx-enable = <5>;
|
||||
azoteq,dead-time-enable;
|
||||
azoteq,sense-mode = <2>;
|
||||
};
|
||||
|
||||
cycle-2 {
|
||||
azoteq,conv-period = <5>;
|
||||
azoteq,conv-frac = <127>;
|
||||
azoteq,tx-enable = <4>;
|
||||
azoteq,dead-time-enable;
|
||||
azoteq,sense-mode = <2>;
|
||||
};
|
||||
|
||||
cycle-3 {
|
||||
azoteq,conv-period = <5>;
|
||||
azoteq,conv-frac = <127>;
|
||||
azoteq,tx-enable = <2>;
|
||||
azoteq,dead-time-enable;
|
||||
azoteq,sense-mode = <2>;
|
||||
};
|
||||
|
||||
cycle-4 {
|
||||
azoteq,conv-period = <5>;
|
||||
azoteq,conv-frac = <127>;
|
||||
azoteq,tx-enable = <1>;
|
||||
azoteq,dead-time-enable;
|
||||
azoteq,sense-mode = <2>;
|
||||
};
|
||||
|
||||
cycle-5 {
|
||||
azoteq,conv-period = <2>;
|
||||
azoteq,conv-frac = <0>;
|
||||
};
|
||||
|
||||
cycle-6 {
|
||||
azoteq,conv-period = <2>;
|
||||
azoteq,conv-frac = <0>;
|
||||
};
|
||||
|
||||
channel-0 {
|
||||
azoteq,ulp-allow;
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <3>;
|
||||
azoteq,ati-target = <800>;
|
||||
azoteq,ati-base = <208>;
|
||||
azoteq,ati-mode = <5>;
|
||||
};
|
||||
|
||||
channel-1 {
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <3>;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <208>;
|
||||
azoteq,ati-mode = <5>;
|
||||
};
|
||||
|
||||
channel-2 {
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <3>;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <208>;
|
||||
azoteq,ati-mode = <5>;
|
||||
};
|
||||
|
||||
channel-3 {
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <3>;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <208>;
|
||||
azoteq,ati-mode = <5>;
|
||||
};
|
||||
|
||||
channel-4 {
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <3>;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <208>;
|
||||
azoteq,ati-mode = <5>;
|
||||
};
|
||||
|
||||
channel-5 {
|
||||
azoteq,ulp-allow;
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <6>;
|
||||
azoteq,ati-target = <800>;
|
||||
azoteq,ati-base = <144>;
|
||||
azoteq,ati-mode = <5>;
|
||||
};
|
||||
|
||||
channel-6 {
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <6>;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <160>;
|
||||
azoteq,ati-mode = <5>;
|
||||
|
||||
event-touch {
|
||||
linux,code = <KEY_MUTE>;
|
||||
};
|
||||
};
|
||||
|
||||
channel-7 {
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <6>;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <160>;
|
||||
azoteq,ati-mode = <5>;
|
||||
|
||||
event-touch {
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
channel-8 {
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <6>;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <160>;
|
||||
azoteq,ati-mode = <5>;
|
||||
|
||||
event-touch {
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
};
|
||||
|
||||
channel-9 {
|
||||
azoteq,global-halt;
|
||||
azoteq,invert-enable;
|
||||
azoteq,rx-enable = <6>;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <160>;
|
||||
azoteq,ati-mode = <5>;
|
||||
|
||||
event-touch {
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
};
|
||||
|
||||
channel-10 {
|
||||
azoteq,ulp-allow;
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <112>;
|
||||
|
||||
event-touch {
|
||||
linux,code = <SW_LID>;
|
||||
linux,input-type = <EV_SW>;
|
||||
};
|
||||
};
|
||||
|
||||
channel-11 {
|
||||
azoteq,ati-target = <496>;
|
||||
azoteq,ati-base = <112>;
|
||||
};
|
||||
|
||||
slider-0 {
|
||||
azoteq,channel-select = <1>, <2>, <3>, <4>;
|
||||
azoteq,slider-size = <4080>;
|
||||
azoteq,upper-cal = <50>;
|
||||
azoteq,lower-cal = <30>;
|
||||
azoteq,top-speed = <200>;
|
||||
azoteq,bottom-speed = <1>;
|
||||
azoteq,bottom-beta = <3>;
|
||||
|
||||
event-tap {
|
||||
linux,code = <KEY_PLAYPAUSE>;
|
||||
azoteq,gesture-max-ms = <600>;
|
||||
azoteq,gesture-min-ms = <24>;
|
||||
};
|
||||
|
||||
event-flick-pos {
|
||||
linux,code = <KEY_NEXTSONG>;
|
||||
azoteq,gesture-max-ms = <600>;
|
||||
azoteq,gesture-dist = <816>;
|
||||
};
|
||||
|
||||
event-flick-neg {
|
||||
linux,code = <KEY_PREVIOUSSONG>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -15,14 +15,16 @@ description: |
|
||||
Google's ChromeOS EC Keyboard is a simple matrix keyboard
|
||||
implemented on a separate EC (Embedded Controller) device. It provides
|
||||
a message for reading key scans from the EC. These are then converted
|
||||
into keycodes for processing by the kernel.
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/input/matrix-keymap.yaml#"
|
||||
into keycodes for processing by the kernel. This device also supports
|
||||
switches/buttons like power and volume buttons.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: google,cros-ec-keyb
|
||||
oneOf:
|
||||
- description: ChromeOS EC with only buttons/switches
|
||||
const: google,cros-ec-keyb-switches
|
||||
- description: ChromeOS EC with keyboard and possibly buttons/switches
|
||||
const: google,cros-ec-keyb
|
||||
|
||||
google,needs-ghost-filter:
|
||||
description:
|
||||
@ -42,15 +44,31 @@ properties:
|
||||
where the lower 16 bits are reserved. This property is specified only
|
||||
when the keyboard has a custom design for the top row keys.
|
||||
|
||||
dependencies:
|
||||
function-row-phsymap: [ 'linux,keymap' ]
|
||||
google,needs-ghost-filter: [ 'linux,keymap' ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: google,cros-ec-keyb
|
||||
then:
|
||||
$ref: "/schemas/input/matrix-keymap.yaml#"
|
||||
required:
|
||||
- keypad,num-rows
|
||||
- keypad,num-columns
|
||||
- linux,keymap
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/input/input.h>
|
||||
cros-ec-keyb {
|
||||
keyboard-controller {
|
||||
compatible = "google,cros-ec-keyb";
|
||||
keypad,num-rows = <8>;
|
||||
keypad,num-columns = <13>;
|
||||
@ -114,3 +132,9 @@ examples:
|
||||
/* UP LEFT */
|
||||
0x070b0067 0x070c0069>;
|
||||
};
|
||||
- |
|
||||
/* No matrix keyboard, just buttons/switches */
|
||||
keyboard-controller {
|
||||
compatible = "google,cros-ec-keyb-switches";
|
||||
};
|
||||
...
|
||||
|
||||
@ -22,6 +22,7 @@ Properties:
|
||||
- "qcom,sc7280-pdc": For SC7280
|
||||
- "qcom,sdm845-pdc": For SDM845
|
||||
- "qcom,sm6350-pdc": For SM6350
|
||||
- "qcom,sm8150-pdc": For SM8150
|
||||
- "qcom,sm8250-pdc": For SM8250
|
||||
- "qcom,sm8350-pdc": For SM8350
|
||||
|
||||
|
||||
@ -37,8 +37,10 @@ properties:
|
||||
- qcom,sc7180-smmu-500
|
||||
- qcom,sc7280-smmu-500
|
||||
- qcom,sc8180x-smmu-500
|
||||
- qcom,sc8280xp-smmu-500
|
||||
- qcom,sdm845-smmu-500
|
||||
- qcom,sdx55-smmu-500
|
||||
- qcom,sdx65-smmu-500
|
||||
- qcom,sm6350-smmu-500
|
||||
- qcom,sm8150-smmu-500
|
||||
- qcom,sm8250-smmu-500
|
||||
@ -62,8 +64,9 @@ properties:
|
||||
for improved performance.
|
||||
items:
|
||||
- enum:
|
||||
- nvidia,tegra194-smmu
|
||||
- nvidia,tegra186-smmu
|
||||
- nvidia,tegra194-smmu
|
||||
- nvidia,tegra234-smmu
|
||||
- const: nvidia,smmu-500
|
||||
- items:
|
||||
- const: arm,mmu-500
|
||||
@ -157,6 +160,17 @@ properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
nvidia,memory-controller:
|
||||
description: |
|
||||
A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
|
||||
The memory controller needs to be programmed with a mapping of memory
|
||||
client IDs to ARM SMMU stream IDs.
|
||||
|
||||
If this property is absent, the mapping programmed by early firmware
|
||||
will be used and it is not guaranteed that IOMMU translations will be
|
||||
enabled for any given device.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -172,13 +186,20 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra194-smmu
|
||||
- nvidia,tegra186-smmu
|
||||
- nvidia,tegra194-smmu
|
||||
- nvidia,tegra234-smmu
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
# The reference to the memory controller is required to ensure that the
|
||||
# memory client to stream ID mapping can be done synchronously with the
|
||||
# IOMMU attachment.
|
||||
required:
|
||||
- nvidia,memory-controller
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
|
||||
@ -76,7 +76,11 @@ properties:
|
||||
- mediatek,mt8167-m4u # generation two
|
||||
- mediatek,mt8173-m4u # generation two
|
||||
- mediatek,mt8183-m4u # generation two
|
||||
- mediatek,mt8186-iommu-mm # generation two
|
||||
- mediatek,mt8192-m4u # generation two
|
||||
- mediatek,mt8195-iommu-vdo # generation two
|
||||
- mediatek,mt8195-iommu-vpp # generation two
|
||||
- mediatek,mt8195-iommu-infra # generation two
|
||||
|
||||
- description: mt7623 generation one
|
||||
items:
|
||||
@ -119,7 +123,9 @@ properties:
|
||||
dt-binding/memory/mt8167-larb-port.h for mt8167,
|
||||
dt-binding/memory/mt8173-larb-port.h for mt8173,
|
||||
dt-binding/memory/mt8183-larb-port.h for mt8183,
|
||||
dt-binding/memory/mt8186-memory-port.h for mt8186,
|
||||
dt-binding/memory/mt8192-larb-port.h for mt8192.
|
||||
dt-binding/memory/mt8195-memory-port.h for mt8195.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
@ -128,7 +134,6 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- mediatek,larbs
|
||||
- '#iommu-cells'
|
||||
|
||||
allOf:
|
||||
@ -140,7 +145,10 @@ allOf:
|
||||
- mediatek,mt2701-m4u
|
||||
- mediatek,mt2712-m4u
|
||||
- mediatek,mt8173-m4u
|
||||
- mediatek,mt8186-iommu-mm
|
||||
- mediatek,mt8192-m4u
|
||||
- mediatek,mt8195-iommu-vdo
|
||||
- mediatek,mt8195-iommu-vpp
|
||||
|
||||
then:
|
||||
required:
|
||||
@ -150,12 +158,26 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8186-iommu-mm
|
||||
- mediatek,mt8192-m4u
|
||||
- mediatek,mt8195-iommu-vdo
|
||||
- mediatek,mt8195-iommu-vpp
|
||||
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
|
||||
- if: # The IOMMUs don't have larbs.
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8195-iommu-infra
|
||||
|
||||
then:
|
||||
required:
|
||||
- mediatek,larbs
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
@ -173,13 +195,3 @@ examples:
|
||||
<&larb3>, <&larb4>, <&larb5>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/memory/mt8173-larb-port.h>
|
||||
|
||||
/* Example for a client device */
|
||||
display {
|
||||
compatible = "mediatek,mt8173-disp";
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>,
|
||||
<&iommu M4U_PORT_DISP_RDMA0>;
|
||||
};
|
||||
|
||||
@ -86,16 +86,6 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
|
||||
gsc_0: scaler@13e00000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
power-domains = <&pd_gsc>;
|
||||
clocks = <&clock CLK_GSCL0>;
|
||||
clock-names = "gscl";
|
||||
iommus = <&sysmmu_gsc0>;
|
||||
};
|
||||
|
||||
sysmmu_gsc0: iommu@13e80000 {
|
||||
compatible = "samsung,exynos-sysmmu";
|
||||
reg = <0x13E80000 0x1000>;
|
||||
|
||||
@ -57,7 +57,7 @@ properties:
|
||||
mediatek,rpmsg-name:
|
||||
description:
|
||||
Must be defined if the cros-ec is a rpmsg device for a Mediatek
|
||||
ARM Cortex M4 Co-processor. Contains the name pf the rpmsg
|
||||
ARM Cortex M4 Co-processor. Contains the name of the rpmsg
|
||||
device. Used to match the subnode to the rpmsg device announced by
|
||||
the SCP.
|
||||
$ref: "/schemas/types.yaml#/definitions/string"
|
||||
|
||||
@ -1,465 +0,0 @@
|
||||
RK8XX Power Management Integrated Circuit
|
||||
|
||||
The rk8xx family current members:
|
||||
rk805
|
||||
rk808
|
||||
rk809
|
||||
rk817
|
||||
rk818
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk805"
|
||||
- compatible: "rockchip,rk808"
|
||||
- compatible: "rockchip,rk809"
|
||||
- compatible: "rockchip,rk817"
|
||||
- compatible: "rockchip,rk818"
|
||||
- reg: I2C slave address
|
||||
- interrupts: the interrupt outputs of the controller.
|
||||
- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
|
||||
outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock binding to override the
|
||||
default output clock name
|
||||
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
|
||||
the system power.
|
||||
- wakeup-source: Device can be used as a wakeup source.
|
||||
|
||||
Optional RK805 properties:
|
||||
- vcc1-supply: The input supply for DCDC_REG1
|
||||
- vcc2-supply: The input supply for DCDC_REG2
|
||||
- vcc3-supply: The input supply for DCDC_REG3
|
||||
- vcc4-supply: The input supply for DCDC_REG4
|
||||
- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2
|
||||
- vcc6-supply: The input supply for LDO_REG3
|
||||
|
||||
Optional RK808 properties:
|
||||
- vcc1-supply: The input supply for DCDC_REG1
|
||||
- vcc2-supply: The input supply for DCDC_REG2
|
||||
- vcc3-supply: The input supply for DCDC_REG3
|
||||
- vcc4-supply: The input supply for DCDC_REG4
|
||||
- vcc6-supply: The input supply for LDO_REG1 and LDO_REG2
|
||||
- vcc7-supply: The input supply for LDO_REG3 and LDO_REG7
|
||||
- vcc8-supply: The input supply for SWITCH_REG1
|
||||
- vcc9-supply: The input supply for LDO_REG4 and LDO_REG5
|
||||
- vcc10-supply: The input supply for LDO_REG6
|
||||
- vcc11-supply: The input supply for LDO_REG8
|
||||
- vcc12-supply: The input supply for SWITCH_REG2
|
||||
- dvs-gpios: buck1/2 can be controlled by gpio dvs, this is GPIO specifiers
|
||||
for 2 host gpio's used for dvs. The format of the gpio specifier depends in
|
||||
the gpio controller. If DVS GPIOs aren't present, voltage changes will happen
|
||||
very quickly with no slow ramp time.
|
||||
|
||||
Optional shared RK809 and RK817 properties:
|
||||
- vcc1-supply: The input supply for DCDC_REG1
|
||||
- vcc2-supply: The input supply for DCDC_REG2
|
||||
- vcc3-supply: The input supply for DCDC_REG3
|
||||
- vcc4-supply: The input supply for DCDC_REG4
|
||||
- vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3
|
||||
- vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6
|
||||
- vcc7-supply: The input supply for LDO_REG7, LDO_REG8, LDO_REG9
|
||||
|
||||
Optional RK809 properties:
|
||||
- vcc8-supply: The input supply for SWITCH_REG1
|
||||
- vcc9-supply: The input supply for DCDC_REG5, SWITCH_REG2
|
||||
|
||||
Optional RK817 properties:
|
||||
- clocks: The input clock for the audio codec
|
||||
- clock-names: The clock name for the codec clock. Should be "mclk".
|
||||
- #sound-dai-cells: Needed for the interpretation of sound dais. Should be 0.
|
||||
|
||||
- vcc8-supply: The input supply for BOOST
|
||||
- vcc9-supply: The input supply for OTG_SWITCH
|
||||
- codec: The child node for the codec to hold additional properties.
|
||||
If no additional properties are required for the codec, this
|
||||
node can be omitted.
|
||||
|
||||
- rockchip,mic-in-differential: Telling if the microphone uses differential
|
||||
mode. Should be under the codec child node.
|
||||
|
||||
Optional RK818 properties:
|
||||
- vcc1-supply: The input supply for DCDC_REG1
|
||||
- vcc2-supply: The input supply for DCDC_REG2
|
||||
- vcc3-supply: The input supply for DCDC_REG3
|
||||
- vcc4-supply: The input supply for DCDC_REG4
|
||||
- boost-supply: The input supply for DCDC_BOOST
|
||||
- vcc6-supply: The input supply for LDO_REG1 and LDO_REG2
|
||||
- vcc7-supply: The input supply for LDO_REG3, LDO_REG5 and LDO_REG7
|
||||
- vcc8-supply: The input supply for LDO_REG4, LDO_REG6 and LDO_REG8
|
||||
- vcc9-supply: The input supply for LDO_REG9 and SWITCH_REG
|
||||
- h_5v-supply: The input supply for HDMI_SWITCH
|
||||
- usb-supply: The input supply for OTG_SWITCH
|
||||
|
||||
Regulators: All the regulators of RK8XX to be instantiated shall be
|
||||
listed in a child node named 'regulators'. Each regulator is represented
|
||||
by a child node of the 'regulators' node.
|
||||
|
||||
regulator-name {
|
||||
/* standard regulator bindings here */
|
||||
};
|
||||
|
||||
Following regulators of the RK805 PMIC regulators are supported. Note that
|
||||
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||
number as described in RK805 datasheet.
|
||||
|
||||
- DCDC_REGn
|
||||
- valid values for n are 1 to 4.
|
||||
- LDO_REGn
|
||||
- valid values for n are 1 to 3
|
||||
|
||||
Following regulators of the RK808 PMIC block are supported. Note that
|
||||
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||
number as described in RK808 datasheet.
|
||||
|
||||
- DCDC_REGn
|
||||
- valid values for n are 1 to 4.
|
||||
- LDO_REGn
|
||||
- valid values for n are 1 to 8.
|
||||
- SWITCH_REGn
|
||||
- valid values for n are 1 to 2
|
||||
|
||||
Following regulators of the RK809 and RK817 PMIC blocks are supported. Note that
|
||||
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||
number as described in RK809 and RK817 datasheets.
|
||||
|
||||
- DCDC_REGn
|
||||
- valid values for n are 1 to 5 for RK809.
|
||||
- valid values for n are 1 to 4 for RK817.
|
||||
- LDO_REGn
|
||||
- valid values for n are 1 to 9 for RK809.
|
||||
- valid values for n are 1 to 9 for RK817.
|
||||
- SWITCH_REGn
|
||||
- valid values for n are 1 to 2 for RK809.
|
||||
- BOOST for RK817
|
||||
- OTG_SWITCH for RK817
|
||||
|
||||
Following regulators of the RK818 PMIC block are supported. Note that
|
||||
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||
number as described in RK818 datasheet.
|
||||
|
||||
- DCDC_REGn
|
||||
- valid values for n are 1 to 4.
|
||||
- LDO_REGn
|
||||
- valid values for n are 1 to 9.
|
||||
- SWITCH_REG
|
||||
- HDMI_SWITCH
|
||||
- OTG_SWITCH
|
||||
|
||||
It is necessary to configure three pins for both the RK809 and RK817, the three
|
||||
pins are "gpio_ts" "gpio_gt" "gpio_slp".
|
||||
The gpio_gt and gpio_ts pins support the gpio function.
|
||||
The gpio_slp pin is for controlling the pmic states, as below:
|
||||
- reset
|
||||
- power down
|
||||
- sleep
|
||||
|
||||
Standard regulator bindings are used inside regulator subnodes. Check
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
for more details
|
||||
|
||||
Example:
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int &dvs_1 &dvs_2>;
|
||||
dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio7 15 GPIO_ACTIVE_HIGH>;
|
||||
reg = <0x1b>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
|
||||
vcc8-supply = <&vcc_18>;
|
||||
vcc9-supply = <&vcc_io>;
|
||||
vcc10-supply = <&vcc_io>;
|
||||
vcc12-supply = <&vcc_io>;
|
||||
vddio-supply = <&vccio_pmu>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-name = "vdd_arm";
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
};
|
||||
|
||||
vcc_io: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_io";
|
||||
};
|
||||
|
||||
vccio_pmu: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_pmu";
|
||||
};
|
||||
|
||||
vcc_tp: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_tp";
|
||||
};
|
||||
|
||||
vdd_10: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd_10";
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
};
|
||||
|
||||
vdd10_lcd: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd10_lcd";
|
||||
};
|
||||
|
||||
vcc_18: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_18";
|
||||
};
|
||||
|
||||
vcca_codec: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcca_codec";
|
||||
};
|
||||
|
||||
vcc_wl: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_wl";
|
||||
};
|
||||
|
||||
vcc_lcd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_lcd";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rk817: pmic@20 {
|
||||
compatible = "rockchip,rk817";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-output-names = "rk808-clkout1", "xin32k";
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru SCLK_I2S1_OUT>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
vcc1-supply = <&vccsys>;
|
||||
vcc2-supply = <&vccsys>;
|
||||
vcc3-supply = <&vccsys>;
|
||||
vcc4-supply = <&vccsys>;
|
||||
vcc5-supply = <&vccsys>;
|
||||
vcc6-supply = <&vccsys>;
|
||||
vcc7-supply = <&vccsys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_arm: DCDC_REG2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: DCDC_REG4 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: LDO_REG2 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v0: LDO_REG3 {
|
||||
regulator-name = "vdd_1v0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG4 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd: LDO_REG6 {
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_bl: LDO_REG7 {
|
||||
regulator-name = "vcc_bl";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_lcd: LDO_REG8 {
|
||||
regulator-name = "vcc_lcd";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <2800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_cam: LDO_REG9 {
|
||||
regulator-name = "vcc_cam";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rk817_codec: codec {
|
||||
rockchip,mic-in-differential;
|
||||
};
|
||||
};
|
||||
219
Documentation/devicetree/bindings/mfd/rockchip,rk805.yaml
Normal file
219
Documentation/devicetree/bindings/mfd/rockchip,rk805.yaml
Normal file
@ -0,0 +1,219 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/rockchip,rk805.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RK805 Power Management Integrated Circuit
|
||||
|
||||
maintainers:
|
||||
- Chris Zhong <zyw@rock-chips.com>
|
||||
- Zhang Qing <zhangqing@rock-chips.com>
|
||||
|
||||
description: |
|
||||
Rockchip RK805 series PMIC. This device consists of an i2c controlled MFD
|
||||
that includes multiple switchable regulators.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk805
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
description:
|
||||
See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
|
||||
minimum: 0
|
||||
maximum: 1
|
||||
|
||||
clock-output-names:
|
||||
description:
|
||||
From common clock binding to override the default output clock name.
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
rockchip,system-power-controller:
|
||||
type: boolean
|
||||
description:
|
||||
Telling whether or not this PMIC is controlling the system power.
|
||||
|
||||
wakeup-source:
|
||||
type: boolean
|
||||
description:
|
||||
Device can be used as a wakeup source.
|
||||
|
||||
vcc1-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG1.
|
||||
|
||||
vcc2-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG2.
|
||||
|
||||
vcc3-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG3.
|
||||
|
||||
vcc4-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG4.
|
||||
|
||||
vcc5-supply:
|
||||
description:
|
||||
The input supply for LDO_REG1 and LDO_REG2.
|
||||
|
||||
vcc6-supply:
|
||||
description:
|
||||
The input supply for LDO_REG3.
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
patternProperties:
|
||||
"^(DCDC_REG[1-4]|LDO_REG[1-3])$":
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
else:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmic@18 {
|
||||
compatible = "rockchip,rk805";
|
||||
reg = <0x18>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <0>;
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc5-supply = <&vcc_io>;
|
||||
vcc6-supply = <&vcc_io>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_arm: DCDC_REG2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_io: DCDC_REG4 {
|
||||
regulator-name = "vcc_io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_18: LDO_REG1 {
|
||||
regulator-name = "vdd_18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc18_emmc: LDO_REG2 {
|
||||
regulator-name = "vcc_18emmc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_11: LDO_REG3 {
|
||||
regulator-name = "vdd_11";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
257
Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml
Normal file
257
Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml
Normal file
@ -0,0 +1,257 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/rockchip,rk808.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RK808 Power Management Integrated Circuit
|
||||
|
||||
maintainers:
|
||||
- Chris Zhong <zyw@rock-chips.com>
|
||||
- Zhang Qing <zhangqing@rock-chips.com>
|
||||
|
||||
description: |
|
||||
Rockchip RK808 series PMIC. This device consists of an i2c controlled MFD
|
||||
that includes regulators, an RTC, and a power button.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk808
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
description:
|
||||
See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
|
||||
const: 1
|
||||
|
||||
clock-output-names:
|
||||
description:
|
||||
From common clock binding to override the default output clock name.
|
||||
maxItems: 2
|
||||
|
||||
rockchip,system-power-controller:
|
||||
type: boolean
|
||||
description:
|
||||
Telling whether or not this PMIC is controlling the system power.
|
||||
|
||||
wakeup-source:
|
||||
type: boolean
|
||||
description:
|
||||
Device can be used as a wakeup source.
|
||||
|
||||
vcc1-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG1.
|
||||
|
||||
vcc2-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG2.
|
||||
|
||||
vcc3-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG3.
|
||||
|
||||
vcc4-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG4.
|
||||
|
||||
vcc6-supply:
|
||||
description:
|
||||
The input supply for LDO_REG1 and LDO_REG2.
|
||||
|
||||
vcc7-supply:
|
||||
description:
|
||||
The input supply for LDO_REG3 and LDO_REG7.
|
||||
|
||||
vcc8-supply:
|
||||
description:
|
||||
The input supply for SWITCH_REG1.
|
||||
|
||||
vcc9-supply:
|
||||
description:
|
||||
The input supply for LDO_REG4 and LDO_REG5.
|
||||
|
||||
vcc10-supply:
|
||||
description:
|
||||
The input supply for LDO_REG6.
|
||||
|
||||
vcc11-supply:
|
||||
description:
|
||||
The input supply for LDO_REG8.
|
||||
|
||||
vcc12-supply:
|
||||
description:
|
||||
The input supply for SWITCH_REG2.
|
||||
|
||||
vddio-supply:
|
||||
description:
|
||||
The input supply for digital IO.
|
||||
|
||||
dvs-gpios:
|
||||
description: |
|
||||
buck1/2 can be controlled by gpio dvs, this is GPIO specifiers for
|
||||
2 host gpio's used for dvs. The format of the gpio specifier
|
||||
depends in the gpio controller. If DVS GPIOs aren't present,
|
||||
voltage changes will happen very quickly with no slow ramp time.
|
||||
maxItems: 2
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
patternProperties:
|
||||
"^(DCDC_REG[1-4]|LDO_REG[1-8]|SWITCH_REG[1-2])$":
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int &dvs_1 &dvs_2>;
|
||||
dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio7 15 GPIO_ACTIVE_HIGH>;
|
||||
reg = <0x1b>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
|
||||
vcc8-supply = <&vcc_18>;
|
||||
vcc9-supply = <&vcc_io>;
|
||||
vcc10-supply = <&vcc_io>;
|
||||
vcc12-supply = <&vcc_io>;
|
||||
vddio-supply = <&vccio_pmu>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-name = "vdd_arm";
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
};
|
||||
|
||||
vcc_io: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_io";
|
||||
};
|
||||
|
||||
vccio_pmu: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_pmu";
|
||||
};
|
||||
|
||||
vcc_tp: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_tp";
|
||||
};
|
||||
|
||||
vdd_10: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd_10";
|
||||
};
|
||||
|
||||
vcc18_lcd: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
};
|
||||
|
||||
vdd10_lcd: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-name = "vdd10_lcd";
|
||||
};
|
||||
|
||||
vcc_18: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_18";
|
||||
};
|
||||
|
||||
vcca_codec: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcca_codec";
|
||||
};
|
||||
|
||||
vcc_wl: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_wl";
|
||||
};
|
||||
|
||||
vcc_lcd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_lcd";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
284
Documentation/devicetree/bindings/mfd/rockchip,rk809.yaml
Normal file
284
Documentation/devicetree/bindings/mfd/rockchip,rk809.yaml
Normal file
@ -0,0 +1,284 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RK809 Power Management Integrated Circuit
|
||||
|
||||
maintainers:
|
||||
- Chris Zhong <zyw@rock-chips.com>
|
||||
- Zhang Qing <zhangqing@rock-chips.com>
|
||||
|
||||
description: |
|
||||
Rockchip RK809 series PMIC. This device consists of an i2c controlled MFD
|
||||
that includes regulators, an RTC, and power button.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk809
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
description: |
|
||||
See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
|
||||
minimum: 0
|
||||
maximum: 1
|
||||
|
||||
clock-output-names:
|
||||
description:
|
||||
From common clock binding to override the default output clock name.
|
||||
|
||||
rockchip,system-power-controller:
|
||||
type: boolean
|
||||
description:
|
||||
Telling whether or not this PMIC is controlling the system power.
|
||||
|
||||
wakeup-source:
|
||||
type: boolean
|
||||
description:
|
||||
Device can be used as a wakeup source.
|
||||
|
||||
vcc1-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG1.
|
||||
|
||||
vcc2-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG2.
|
||||
|
||||
vcc3-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG3.
|
||||
|
||||
vcc4-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG4.
|
||||
|
||||
vcc5-supply:
|
||||
description:
|
||||
The input supply for LDO_REG1, LDO_REG2, and LDO_REG3.
|
||||
|
||||
vcc6-supply:
|
||||
description:
|
||||
The input supply for LDO_REG4, LDO_REG5, and LDO_REG6.
|
||||
|
||||
vcc7-supply:
|
||||
description:
|
||||
The input supply for LDO_REG7, LDO_REG8, and LDO_REG9.
|
||||
|
||||
vcc8-supply:
|
||||
description:
|
||||
The input supply for SWITCH_REG1.
|
||||
|
||||
vcc9-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG5 and SWITCH_REG2.
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
patternProperties:
|
||||
"^(LDO_REG[1-9]|DCDC_REG[1-5]|SWITCH_REG[1-2])$":
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
else:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l_pin>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc_sysin>;
|
||||
vcc2-supply = <&vcc_sysin>;
|
||||
vcc3-supply = <&vcc_sysin>;
|
||||
vcc4-supply = <&vcc_sysin>;
|
||||
vcc6-supply = <&vcc_sysin>;
|
||||
vcc7-supply = <&vcc_sysin>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc_sysin>;
|
||||
vcc10-supply = <&vcc_sysin>;
|
||||
vcc11-supply = <&vcc_sysin>;
|
||||
vcc12-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-name = "vdd_center";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: vcc_wl: DCDC_REG4 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmupll: LDO_REG3 {
|
||||
regulator-name = "vcc1v8_pmupll";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-name = "vcc_sdio";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca3v0_codec: LDO_REG5 {
|
||||
regulator-name = "vcca3v0_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-name = "vcc_1v5";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-name = "vcca1v8_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-name = "vcc3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
330
Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml
Normal file
330
Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml
Normal file
@ -0,0 +1,330 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/rockchip,rk817.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RK817 Power Management Integrated Circuit
|
||||
|
||||
maintainers:
|
||||
- Chris Zhong <zyw@rock-chips.com>
|
||||
- Zhang Qing <zhangqing@rock-chips.com>
|
||||
|
||||
description: |
|
||||
Rockchip RK817 series PMIC. This device consists of an i2c controlled MFD
|
||||
that includes regulators, an RTC, a power button, an audio codec, and a
|
||||
battery charger manager.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk817
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
description:
|
||||
See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
|
||||
minimum: 0
|
||||
maximum: 1
|
||||
|
||||
clock-output-names:
|
||||
description:
|
||||
From common clock binding to override the default output clock name.
|
||||
|
||||
rockchip,system-power-controller:
|
||||
type: boolean
|
||||
description:
|
||||
Telling whether or not this PMIC is controlling the system power.
|
||||
|
||||
wakeup-source:
|
||||
type: boolean
|
||||
description:
|
||||
Device can be used as a wakeup source.
|
||||
|
||||
vcc1-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG1.
|
||||
|
||||
vcc2-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG2.
|
||||
|
||||
vcc3-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG3.
|
||||
|
||||
vcc4-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG4.
|
||||
|
||||
vcc5-supply:
|
||||
description:
|
||||
The input supply for LDO_REG1, LDO_REG2, and LDO_REG3.
|
||||
|
||||
vcc6-supply:
|
||||
description:
|
||||
The input supply for LDO_REG4, LDO_REG5, and LDO_REG6.
|
||||
|
||||
vcc7-supply:
|
||||
description:
|
||||
The input supply for LDO_REG7, LDO_REG8, and LDO_REG9.
|
||||
|
||||
vcc8-supply:
|
||||
description:
|
||||
The input supply for BOOST.
|
||||
|
||||
vcc9-supply:
|
||||
description:
|
||||
The input supply for OTG_SWITCH.
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
patternProperties:
|
||||
"^(LDO_REG[1-9]|DCDC_REG[1-4]|BOOST|OTG_SWITCH)$":
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
clocks:
|
||||
description:
|
||||
The input clock for the audio codec.
|
||||
|
||||
clock-names:
|
||||
description:
|
||||
The clock name for the codec clock.
|
||||
items:
|
||||
- const: mclk
|
||||
|
||||
'#sound-dai-cells':
|
||||
description:
|
||||
Needed for the interpretation of sound dais.
|
||||
const: 0
|
||||
|
||||
codec:
|
||||
description: |
|
||||
The child node for the codec to hold additional properties. If no
|
||||
additional properties are required for the codec, this node can be
|
||||
omitted.
|
||||
type: object
|
||||
properties:
|
||||
rockchip,mic-in-differential:
|
||||
type: boolean
|
||||
description:
|
||||
Describes if the microphone uses differential mode.
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
else:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/px30-cru.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rk817: pmic@20 {
|
||||
compatible = "rockchip,rk817";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-output-names = "rk808-clkout1", "xin32k";
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru SCLK_I2S1_OUT>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
vcc1-supply = <&vccsys>;
|
||||
vcc2-supply = <&vccsys>;
|
||||
vcc3-supply = <&vccsys>;
|
||||
vcc4-supply = <&vccsys>;
|
||||
vcc5-supply = <&vccsys>;
|
||||
vcc6-supply = <&vccsys>;
|
||||
vcc7-supply = <&vccsys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_arm: DCDC_REG2 {
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: DCDC_REG4 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: LDO_REG2 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v0: LDO_REG3 {
|
||||
regulator-name = "vdd_1v0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG4 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd: LDO_REG6 {
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_bl: LDO_REG7 {
|
||||
regulator-name = "vcc_bl";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_lcd: LDO_REG8 {
|
||||
regulator-name = "vcc_lcd";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <2800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_cam: LDO_REG9 {
|
||||
regulator-name = "vcc_cam";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rk817_codec: codec {
|
||||
rockchip,mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
282
Documentation/devicetree/bindings/mfd/rockchip,rk818.yaml
Normal file
282
Documentation/devicetree/bindings/mfd/rockchip,rk818.yaml
Normal file
@ -0,0 +1,282 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/rockchip,rk818.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RK818 Power Management Integrated Circuit
|
||||
|
||||
maintainers:
|
||||
- Chris Zhong <zyw@rock-chips.com>
|
||||
- Zhang Qing <zhangqing@rock-chips.com>
|
||||
|
||||
description: |
|
||||
Rockchip RK818 series PMIC. This device consists of an i2c controlled MFD
|
||||
that includes regulators, an RTC, and a power button.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk818
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
description: |
|
||||
See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
|
||||
const: 1
|
||||
|
||||
clock-output-names:
|
||||
description:
|
||||
From common clock binding to override the default output clock name.
|
||||
maxItems: 2
|
||||
|
||||
rockchip,system-power-controller:
|
||||
type: boolean
|
||||
description:
|
||||
Telling whether or not this PMIC is controlling the system power.
|
||||
|
||||
wakeup-source:
|
||||
type: boolean
|
||||
description:
|
||||
Device can be used as a wakeup source.
|
||||
|
||||
vcc1-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG1.
|
||||
|
||||
vcc2-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG2.
|
||||
|
||||
vcc3-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG3.
|
||||
|
||||
vcc4-supply:
|
||||
description:
|
||||
The input supply for DCDC_REG4.
|
||||
|
||||
boost-supply:
|
||||
description:
|
||||
The input supply for DCDC_BOOST
|
||||
|
||||
vcc6-supply:
|
||||
description:
|
||||
The input supply for LDO_REG1 and LDO_REG2.
|
||||
|
||||
vcc7-supply:
|
||||
description:
|
||||
The input supply for LDO_REG3, LDO_REG5, and LDO_REG7.
|
||||
|
||||
vcc8-supply:
|
||||
description:
|
||||
The input supply for LDO_REG4, LDO_REG6, and LDO_REG8.
|
||||
|
||||
vcc9-supply:
|
||||
description:
|
||||
The input supply for LDO_REG9 and SWITCH_REG.
|
||||
|
||||
vddio-supply:
|
||||
description:
|
||||
The input supply for digital IO.
|
||||
|
||||
h_5v-supply:
|
||||
description:
|
||||
The input supply for HDMI_SWITCH.
|
||||
|
||||
usb-supply:
|
||||
description:
|
||||
The input supply for OTG_SWITCH.
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
patternProperties:
|
||||
"^(DCDC_REG[1-4]|DCDC_BOOST|LDO_REG[1-9]|SWITCH_REG|HDMI_SWITCH|OTG_SWITCH)$":
|
||||
type: object
|
||||
$ref: ../regulator/regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/px30-cru.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rk818: pmic@1c {
|
||||
compatible = "rockchip,rk818";
|
||||
reg = <0x1c>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
|
||||
vcc1-supply = <&vdd_sys>;
|
||||
vcc2-supply = <&vdd_sys>;
|
||||
vcc3-supply = <&vdd_sys>;
|
||||
vcc4-supply = <&vdd_sys>;
|
||||
boost-supply = <&vdd_in_otg_out>;
|
||||
vcc6-supply = <&vdd_sys>;
|
||||
vcc7-supply = <&vdd_misc_1v8>;
|
||||
vcc8-supply = <&vdd_misc_1v8>;
|
||||
vcc9-supply = <&vdd_3v3_io>;
|
||||
vddio-supply = <&vdd_3v3_io>;
|
||||
|
||||
regulators {
|
||||
vdd_log: DCDC_REG1 {
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_3v3_io: DCDC_REG4 {
|
||||
regulator-name = "vdd_3v3_io";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_sys: DCDC_BOOST {
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_sd: SWITCH_REG {
|
||||
regulator-name = "vdd_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_eth_2v5: LDO_REG2 {
|
||||
regulator-name = "vdd_eth_2v5";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <2500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v0: LDO_REG3 {
|
||||
regulator-name = "vdd_1v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v8_lcd_ldo: LDO_REG4 {
|
||||
regulator-name = "vdd_1v8_lcd_ldo";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v0_lcd: LDO_REG6 {
|
||||
regulator-name = "vdd_1v0_lcd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v8_ldo: LDO_REG7 {
|
||||
regulator-name = "vdd_1v8_ldo";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_io_sd: LDO_REG9 {
|
||||
regulator-name = "vdd_io_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -79,8 +79,8 @@ examples:
|
||||
clocks = <&cmu_aud CLK_ACLK_DMAC>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
dma-channels = <8>;
|
||||
dma-requests = <32>;
|
||||
power-domains = <&pd_aud>;
|
||||
};
|
||||
|
||||
|
||||
@ -100,12 +100,4 @@ examples:
|
||||
compatible = "allwinner,sun8i-h3-system-controller", "syscon";
|
||||
reg = <0x01c00000 0x1000>;
|
||||
};
|
||||
|
||||
- |
|
||||
gpr: iomuxc-gpr@20e0000 {
|
||||
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
|
||||
reg = <0x020e0000 0x38>;
|
||||
hwlocks = <&hwlock1 1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
@ -14,6 +14,7 @@ description: |
|
||||
range of analogue I/O.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml
|
||||
- $ref: /schemas/sound/wlf,arizona.yaml#
|
||||
- $ref: /schemas/regulator/wlf,arizona.yaml#
|
||||
- $ref: /schemas/extcon/wlf,arizona.yaml#
|
||||
|
||||
@ -100,7 +100,6 @@ examples:
|
||||
|
||||
#include <dt-bindings/mux/mux.h>
|
||||
syscon@1000 {
|
||||
compatible = "fsl,imx7d-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
|
||||
reg = <0x1000 0x100>;
|
||||
|
||||
mux2: mux-controller {
|
||||
|
||||
@ -17,10 +17,10 @@ description: |
|
||||
the CPU frequencies subset and voltage value of each OPP varies based on
|
||||
the silicon variant in use.
|
||||
Qualcomm Technologies, Inc. Process Voltage Scaling Tables
|
||||
defines the voltage and frequency value based on the msm-id in SMEM
|
||||
and speedbin blown in the efuse combination.
|
||||
The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
|
||||
to provide the OPP framework with required information (existing HW bitmap).
|
||||
defines the voltage and frequency value based on the speedbin blown in
|
||||
the efuse combination.
|
||||
The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
|
||||
the OPP framework with required information (existing HW bitmap).
|
||||
This is used to determine the voltage and frequency value for each OPP of
|
||||
operating-points-v2 table when it is parsed by the OPP framework.
|
||||
|
||||
@ -50,15 +50,11 @@ patternProperties:
|
||||
description: |
|
||||
A single 32 bit bitmap value, representing compatible HW.
|
||||
Bitmap:
|
||||
0: MSM8996 V3, speedbin 0
|
||||
1: MSM8996 V3, speedbin 1
|
||||
2: MSM8996 V3, speedbin 2
|
||||
3: unused
|
||||
4: MSM8996 SG, speedbin 0
|
||||
5: MSM8996 SG, speedbin 1
|
||||
6: MSM8996 SG, speedbin 2
|
||||
7-31: unused
|
||||
maximum: 0x77
|
||||
0: MSM8996, speedbin 0
|
||||
1: MSM8996, speedbin 1
|
||||
2: MSM8996, speedbin 2
|
||||
3-31: unused
|
||||
maximum: 0x7
|
||||
|
||||
clock-latency-ns: true
|
||||
|
||||
@ -184,19 +180,19 @@ examples:
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x5>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x71>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
@ -209,25 +205,25 @@ examples:
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-1804800000 {
|
||||
opp-hz = /bits/ 64 <1804800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
opp-supported-hw = <0x6>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1900800000 {
|
||||
opp-hz = /bits/ 64 <1900800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x4>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2150400000 {
|
||||
opp-hz = /bits/ 64 <2150400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x31>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2342400000 {
|
||||
opp-hz = /bits/ 64 <2342400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -76,73 +76,24 @@ additionalProperties: false
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/aspeed-clock.h>
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
scu@1e6e2000 {
|
||||
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
|
||||
reg = <0x1e6e2000 0x1a8>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
syscon: scu@1e6e2000 {
|
||||
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
|
||||
reg = <0x1e6e2000 0x1a8>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
pinctrl: pinctrl {
|
||||
compatible = "aspeed,ast2500-pinctrl";
|
||||
aspeed,external-nodes = <&gfx>, <&lhc>;
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "aspeed,ast2500-pinctrl";
|
||||
aspeed,external-nodes = <&gfx>, <&lhc>;
|
||||
|
||||
pinctrl_i2c3_default: i2c3_default {
|
||||
function = "I2C3";
|
||||
groups = "I2C3";
|
||||
};
|
||||
|
||||
pinctrl_gpioh0_unbiased_default: gpioh0 {
|
||||
pins = "A18";
|
||||
bias-disable;
|
||||
};
|
||||
pinctrl_i2c3_default: i2c3_default {
|
||||
function = "I2C3";
|
||||
groups = "I2C3";
|
||||
};
|
||||
};
|
||||
|
||||
gfx: display@1e6e6000 {
|
||||
compatible = "aspeed,ast2500-gfx", "syscon";
|
||||
reg = <0x1e6e6000 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
|
||||
resets = <&syscon ASPEED_RESET_CRT1>;
|
||||
interrupts = <0x19>;
|
||||
syscon = <&syscon>;
|
||||
memory-region = <&gfx_memory>;
|
||||
};
|
||||
};
|
||||
|
||||
lpc: lpc@1e789000 {
|
||||
compatible = "aspeed,ast2500-lpc", "simple-mfd";
|
||||
reg = <0x1e789000 0x1000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1e789000 0x1000>;
|
||||
|
||||
lpc_host: lpc-host@80 {
|
||||
compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
|
||||
reg = <0x80 0x1e0>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x80 0x1e0>;
|
||||
|
||||
lhc: lhc@20 {
|
||||
compatible = "aspeed,ast2500-lhc";
|
||||
reg = <0x20 0x24>, <0x48 0x8>;
|
||||
pinctrl_gpioh0_unbiased_default: gpioh0 {
|
||||
pins = "A18";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gfx_memory: framebuffer {
|
||||
size = <0x01000000>;
|
||||
alignment = <0x01000000>;
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
};
|
||||
|
||||
@ -1,87 +0,0 @@
|
||||
* Freescale i.MX7 Dual IOMUX Controller
|
||||
|
||||
iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
|
||||
as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
|
||||
power state retention capabilities on gpios that are part of iomuxc-lpsr
|
||||
(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
|
||||
mux and pad control settings, it shares the input select register from main
|
||||
iomuxc controller for daisy chain settings, the fsl,input-sel property extends
|
||||
fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
|
||||
|
||||
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
|
||||
compatible = "fsl,imx7d-iomuxc-lpsr";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
fsl,input-sel = <&iomuxc>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@30330000 {
|
||||
compatible = "fsl,imx7d-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
|
||||
Peripherals using pads from iomuxc-lpsr support low state retention power
|
||||
state, under LPSR mode GPIO's state of pads are retain.
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
|
||||
and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
|
||||
"fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
|
||||
- fsl,pins: each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
||||
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
|
||||
imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
|
||||
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
|
||||
Reference Manual for detailed CONFIG settings.
|
||||
- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
|
||||
a phandle for main iomuxc controller which shares the input select register for
|
||||
daisy chain settings.
|
||||
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 5)
|
||||
PAD_CTL_PUS_5K_UP (1 << 5)
|
||||
PAD_CTL_PUS_47K_UP (2 << 5)
|
||||
PAD_CTL_PUS_100K_UP (3 << 5)
|
||||
PAD_CTL_PUE (1 << 4)
|
||||
PAD_CTL_HYS (1 << 3)
|
||||
PAD_CTL_SRE_SLOW (1 << 2)
|
||||
PAD_CTL_SRE_FAST (0 << 2)
|
||||
PAD_CTL_DSE_X1 (0 << 0)
|
||||
PAD_CTL_DSE_X4 (1 << 0)
|
||||
PAD_CTL_DSE_X2 (2 << 0)
|
||||
PAD_CTL_DSE_X6 (3 << 0)
|
||||
|
||||
Examples:
|
||||
While iomuxc-lpsr is intended to be used by dedicated peripherals to take
|
||||
advantages of LPSR power mode, is also possible that an IP to use pads from
|
||||
any of the iomux controllers. For example the I2C1 IP can use SCL pad from
|
||||
iomuxc-lpsr controller and SDA pad from iomuxc controller as:
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1_1>, <&pinctrl_i2c1_2>;
|
||||
};
|
||||
|
||||
iomuxc-lpsr@302c0000 {
|
||||
compatible = "fsl,imx7d-iomuxc-lpsr";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
fsl,input-sel = <&iomuxc>;
|
||||
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
iomuxc@30330000 {
|
||||
compatible = "fsl,imx7d-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
|
||||
pinctrl_i2c1_2: i2c1grp-2 {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
};
|
||||
113
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml
Normal file
113
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml
Normal file
@ -0,0 +1,113 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMX7D IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Dong Aisheng <aisheng.dong@nxp.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx7d-iomuxc
|
||||
- fsl,imx7d-iomuxc-lpsr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
fsl,input-sel:
|
||||
description:
|
||||
phandle for main iomuxc controller which shares the input select
|
||||
register for daisy chain settings.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm/boot/dts/imx7d-pinfunc.h>. The last integer
|
||||
CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX7D Reference Manual for detailed CONFIG settings.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx7d-iomuxc-lpsr
|
||||
|
||||
then:
|
||||
required:
|
||||
- fsl,input-sel
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx7d-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins =
|
||||
<0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
|
||||
<0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
|
||||
};
|
||||
};
|
||||
- |
|
||||
iomuxc_lpsr: pinctrl@302c0000 {
|
||||
compatible = "fsl,imx7d-iomuxc-lpsr";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
fsl,input-sel = <&iomuxc>;
|
||||
|
||||
pinctrl_gpio_lpsr: gpio1-grp {
|
||||
fsl,pins =
|
||||
<0x0008 0x0038 0x0000 0x0 0x0 0x59>,
|
||||
<0x000C 0x003C 0x0000 0x0 0x0 0x59>;
|
||||
};
|
||||
};
|
||||
77
Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
Normal file
77
Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
Normal file
@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MXRT1170 IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
- Jesse Taube <Mr.Bossman075@gmail.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imxrt1170-iomuxc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MXRT1170 Reference Manual for detailed CONFIG settings.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
iomuxc: iomuxc@400e8000 {
|
||||
compatible = "fsl,imxrt1170-iomuxc";
|
||||
reg = <0x400e8000 0x4000>;
|
||||
pinctrl_lpuart1: lpuart1grp {
|
||||
fsl,pins =
|
||||
<0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
|
||||
<0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/marvell,ac5-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell AC5 pin controller
|
||||
|
||||
maintainers:
|
||||
- Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
|
||||
description:
|
||||
Bindings for Marvell's AC5 memory-mapped pin controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: marvell,ac5-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
marvell,function:
|
||||
$ref: "/schemas/types.yaml#/definitions/string"
|
||||
description:
|
||||
Indicates the function to select.
|
||||
enum: [ dev_init_done, ge, gpio, i2c0, i2c1, int_out, led, nand, pcie, ptp, sdio,
|
||||
spi0, spi1, synce, tsen_int, uart0, uart1, uart2, uart3, uartsd, wd_int, xg ]
|
||||
|
||||
marvell,pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description:
|
||||
Array of MPP pins to be used for the given function.
|
||||
minItems: 1
|
||||
items:
|
||||
enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9,
|
||||
mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19,
|
||||
mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, mpp28, mpp29,
|
||||
mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, mpp37, mpp38, mpp39,
|
||||
mpp40, mpp41, mpp42, mpp43, mpp44, mpp45 ]
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pinctrl@80020100 {
|
||||
compatible = "marvell,ac5-pinctrl";
|
||||
reg = <0x80020100 0x20>;
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
marvell,pins = "mpp26", "mpp27";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
i2c0_gpio: i2c0-gpio-pins {
|
||||
marvell,pins = "mpp26", "mpp27";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,224 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek MT6795 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
- Sean Wang <sean.wang@kernel.org>
|
||||
|
||||
description: |
|
||||
The Mediatek's Pin controller is used to control SoC pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt6795-pinctrl
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: |
|
||||
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
|
||||
the amount of cells must be specified as 2. See the below
|
||||
mentioned gpio binding representation for description of particular cells.
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
description: GPIO valid number range.
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
description:
|
||||
Physical address base for gpio base and eint registers.
|
||||
minItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: base
|
||||
- const: eint
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
description: The interrupt outputs to sysirq.
|
||||
maxItems: 1
|
||||
|
||||
# PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'^pins':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and
|
||||
input schmitt.
|
||||
An example of using macro:
|
||||
pincontroller {
|
||||
/* GPIO0 set as multifunction GPIO0 */
|
||||
gpio-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
}
|
||||
};
|
||||
/* GPIO45 set as multifunction SDA0 */
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
|
||||
}
|
||||
};
|
||||
};
|
||||
$ref: "pinmux-node.yaml"
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description: |
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are
|
||||
defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
|
||||
directly.
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
bias-pull-down:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: mt6795 pull down PUPD/R0/R1 type define value.
|
||||
description: |
|
||||
For normal pull down type, it is not necessary to specify R1R0
|
||||
values; When pull down type is PUPD/R0/R1, adding R1R0 defines
|
||||
will set different resistance values.
|
||||
|
||||
bias-pull-up:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: mt6795 pull up PUPD/R0/R1 type define value.
|
||||
description: |
|
||||
For normal pull up type, it is not necessary to specify R1R0
|
||||
values; When pull up type is PUPD/R0/R1, adding R1R0 defines
|
||||
will set different resistance values.
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
mediatek,pull-up-adv:
|
||||
description: |
|
||||
Pull up setings for 2 pull resistors, R0 and R1. User can
|
||||
configure those special pins. Valid arguments are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
mediatek,pull-down-adv:
|
||||
description: |
|
||||
Pull down settings for 2 pull resistors, R0 and R1. User can
|
||||
configure those special pins. Valid arguments are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt6795-pinctrl";
|
||||
reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
|
||||
reg-names = "base", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 196>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
i2c0-pins {
|
||||
pins-sda-scl {
|
||||
pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
|
||||
<PINMUX_GPIO46__FUNC_SCL0>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0-pins {
|
||||
pins-cmd-dat {
|
||||
pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
|
||||
<PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
|
||||
<PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
|
||||
<PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
|
||||
<PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
|
||||
<PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
|
||||
<PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
|
||||
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
|
||||
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins-clk {
|
||||
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins-rst {
|
||||
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,42 +0,0 @@
|
||||
Microsemi Ocelot pin controller Device Tree Bindings
|
||||
----------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "mscc,ocelot-pinctrl",
|
||||
"mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
|
||||
"mscc,luton-pinctrl", "mscc,serval-pinctrl",
|
||||
"microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
|
||||
- reg : Address and length of the register set for the device
|
||||
- gpio-controller : Indicates this device is a GPIO controller
|
||||
- #gpio-cells : Must be 2.
|
||||
The first cell is the pin number and the
|
||||
second cell specifies GPIO flags, as defined in
|
||||
<dt-bindings/gpio/gpio.h>.
|
||||
- gpio-ranges : Range of pins managed by the GPIO controller.
|
||||
|
||||
|
||||
The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
|
||||
configuration documented in pinctrl-bindings.txt.
|
||||
|
||||
The following generic properties are supported:
|
||||
- function
|
||||
- pins
|
||||
|
||||
Example:
|
||||
gpio: pinctrl@71070034 {
|
||||
compatible = "mscc,ocelot-pinctrl";
|
||||
reg = <0x71070034 0x28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 22>;
|
||||
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_6", "GPIO_7";
|
||||
function = "uart";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins = "GPIO_12", "GPIO_13";
|
||||
function = "uart2";
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,116 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microsemi Ocelot pin controller
|
||||
|
||||
maintainers:
|
||||
- Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
- Lars Povlsen <lars.povlsen@microchip.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- microchip,lan966x-pinctrl
|
||||
- microchip,sparx5-pinctrl
|
||||
- mscc,jaguar2-pinctrl
|
||||
- mscc,luton-pinctrl
|
||||
- mscc,ocelot-pinctrl
|
||||
- mscc,serval-pinctrl
|
||||
- mscc,servalt-pinctrl
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Base address
|
||||
- description: Extended pin configuration registers
|
||||
minItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
gpio-ranges: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
description: Optional shared switch reset.
|
||||
items:
|
||||
- const: switch
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: "pinmux-node.yaml"
|
||||
- $ref: "pincfg-node.yaml"
|
||||
|
||||
properties:
|
||||
function: true
|
||||
pins: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
drive-strength: true
|
||||
|
||||
required:
|
||||
- function
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- microchip,lan966x-pinctrl
|
||||
- microchip,sparx5-pinctrl
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
gpio: pinctrl@71070034 {
|
||||
compatible = "mscc,ocelot-pinctrl";
|
||||
reg = <0x71070034 0x28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 22>;
|
||||
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_6", "GPIO_7";
|
||||
function = "uart";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins = "GPIO_12", "GPIO_13";
|
||||
function = "uart2";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -29,6 +29,8 @@ properties:
|
||||
description: gpio valid number range.
|
||||
maxItems: 1
|
||||
|
||||
gpio-line-names: true
|
||||
|
||||
reg:
|
||||
description: |
|
||||
Physical address base for gpio base registers. There are 11 GPIO
|
||||
@ -51,62 +53,92 @@ properties:
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'^pins':
|
||||
'-pins$':
|
||||
type: object
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and
|
||||
input schmitt.
|
||||
An example of using macro:
|
||||
pincontroller {
|
||||
/* GPIO0 set as multifunction GPIO0 */
|
||||
state_0_node_a {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
};
|
||||
/* GPIO1 set as multifunction PWM */
|
||||
state_0_node_b {
|
||||
pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
|
||||
};
|
||||
};
|
||||
$ref: "pinmux-node.yaml"
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description: |
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are defined
|
||||
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
|
||||
|
||||
drive-strength:
|
||||
description: |
|
||||
It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
|
||||
dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'^pins':
|
||||
type: object
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and
|
||||
input schmitt.
|
||||
$ref: "pinmux-node.yaml"
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description: |
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are defined
|
||||
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
|
||||
|
||||
drive-strength:
|
||||
description: |
|
||||
It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
|
||||
dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
mediatek,drive-strength-adv:
|
||||
description: |
|
||||
Describe the specific driving setup property.
|
||||
For I2C pins, the existing generic driving setup can only support
|
||||
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
|
||||
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
|
||||
driving setup, the existing generic setup will be disabled.
|
||||
The specific driving setup is controlled by E1E0EN.
|
||||
When E1=0/E0=0, the strength is 0.125mA.
|
||||
When E1=0/E0=1, the strength is 0.25mA.
|
||||
When E1=1/E0=0, the strength is 0.5mA.
|
||||
When E1=1/E0=1, the strength is 1mA.
|
||||
EN is used to enable or disable the specific driving setup.
|
||||
Valid arguments are described as below:
|
||||
0: (E1, E0, EN) = (0, 0, 0)
|
||||
1: (E1, E0, EN) = (0, 0, 1)
|
||||
2: (E1, E0, EN) = (0, 1, 0)
|
||||
3: (E1, E0, EN) = (0, 1, 1)
|
||||
4: (E1, E0, EN) = (1, 0, 0)
|
||||
5: (E1, E0, EN) = (1, 0, 1)
|
||||
6: (E1, E0, EN) = (1, 1, 0)
|
||||
7: (E1, E0, EN) = (1, 1, 1)
|
||||
So the valid arguments are from 0 to 7.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5, 6, 7]
|
||||
|
||||
mediatek,pull-up-adv:
|
||||
description: |
|
||||
Pull up settings for 2 pull resistors, R0 and R1. User can
|
||||
configure those special pins. Valid arguments are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
@ -151,8 +183,17 @@ examples:
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
output-low;
|
||||
spi1-default-pins {
|
||||
pins-cs-mosi-clk {
|
||||
pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
|
||||
<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
|
||||
<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pins-miso {
|
||||
pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- qcom,pm2250-gpio
|
||||
- qcom,pm660-gpio
|
||||
- qcom,pm660l-gpio
|
||||
- qcom,pm6125-gpio
|
||||
- qcom,pm6150-gpio
|
||||
- qcom,pm6150l-gpio
|
||||
- qcom,pm6350-gpio
|
||||
@ -32,6 +33,7 @@ properties:
|
||||
- qcom,pm8058-gpio
|
||||
- qcom,pm8150-gpio
|
||||
- qcom,pm8150b-gpio
|
||||
- qcom,pm8150l-gpio
|
||||
- qcom,pm8226-gpio
|
||||
- qcom,pm8350-gpio
|
||||
- qcom,pm8350b-gpio
|
||||
@ -49,10 +51,12 @@ properties:
|
||||
- qcom,pmi8994-gpio
|
||||
- qcom,pmi8998-gpio
|
||||
- qcom,pmk8350-gpio
|
||||
- qcom,pmm8155au-gpio
|
||||
- qcom,pmr735a-gpio
|
||||
- qcom,pmr735b-gpio
|
||||
- qcom,pms405-gpio
|
||||
- qcom,pmx55-gpio
|
||||
- qcom,pmx65-gpio
|
||||
|
||||
- enum:
|
||||
- qcom,spmi-gpio
|
||||
@ -71,6 +75,16 @@ properties:
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
gpio-line-names:
|
||||
minItems: 2
|
||||
maxItems: 44
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
# maxItems as half of total number of GPIOs, as there has to be at
|
||||
# least one usable GPIO between each reserved range.
|
||||
maxItems: 22
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
description:
|
||||
@ -87,13 +101,278 @@ required:
|
||||
- gpio-ranges
|
||||
- interrupt-controller
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8008-gpio
|
||||
- qcom,pmi8950-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
gpio-reserved-ranges:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8005-gpio
|
||||
- qcom,pm8450-gpio
|
||||
- qcom,pm8916-gpio
|
||||
- qcom,pmk8350-gpio
|
||||
- qcom,pmr735a-gpio
|
||||
- qcom,pmr735b-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8018-gpio
|
||||
- qcom,pm8019-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8350b-gpio
|
||||
- qcom,pm8950-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm6350-gpio
|
||||
- qcom,pm8350c-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm2250-gpio
|
||||
- qcom,pm6150-gpio
|
||||
- qcom,pm7325-gpio
|
||||
- qcom,pm8150-gpio
|
||||
- qcom,pm8350-gpio
|
||||
- qcom,pmc8180-gpio
|
||||
- qcom,pmi8994-gpio
|
||||
- qcom,pmm8155au-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 10
|
||||
maxItems: 10
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pmx55-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 11
|
||||
maxItems: 11
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm660l-gpio
|
||||
- qcom,pm6150l-gpio
|
||||
- qcom,pm8038-gpio
|
||||
- qcom,pm8150b-gpio
|
||||
- qcom,pm8150l-gpio
|
||||
- qcom,pmc8180c-gpio
|
||||
- qcom,pms405-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 12
|
||||
maxItems: 12
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm660-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 13
|
||||
maxItems: 13
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pmi8998-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 14
|
||||
maxItems: 14
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pmx65-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 16
|
||||
maxItems: 16
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8994-gpio
|
||||
- qcom,pma8084-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 22
|
||||
maxItems: 22
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 11
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8998-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 26
|
||||
maxItems: 26
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 13
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8941-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 36
|
||||
maxItems: 36
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 18
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8917-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 38
|
||||
maxItems: 38
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 19
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pm8058-gpio
|
||||
- qcom,pm8921-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
minItems: 44
|
||||
maxItems: 44
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 22
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-pmic-gpio-state"
|
||||
- patternProperties:
|
||||
".*":
|
||||
"(pinconf|-pins)$":
|
||||
$ref: "#/$defs/qcom-pmic-gpio-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-pmic-gpio-state:
|
||||
@ -106,6 +385,7 @@ $defs:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in
|
||||
this subnode. Valid pins are
|
||||
- gpio1-gpio9 for pm6125
|
||||
- gpio1-gpio10 for pm6150
|
||||
- gpio1-gpio12 for pm6150l
|
||||
- gpio1-gpio9 for pm6350
|
||||
@ -134,12 +414,14 @@ $defs:
|
||||
- gpio1-gpio2 for pmi8950
|
||||
- gpio1-gpio10 for pmi8994
|
||||
- gpio1-gpio4 for pmk8350
|
||||
- gpio1-gpio10 for pmm8155au
|
||||
- gpio1-gpio4 for pmr735a
|
||||
- gpio1-gpio4 for pmr735b
|
||||
- gpio1-gpio12 for pms405 (holes on gpio1, gpio9
|
||||
and gpio10)
|
||||
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
|
||||
and gpio11)
|
||||
- gpio1-gpio16 for pmx65
|
||||
|
||||
items:
|
||||
pattern: "^gpio([0-9]+)$"
|
||||
@ -174,6 +456,7 @@ $defs:
|
||||
|
||||
bias-high-impedance: true
|
||||
input-enable: true
|
||||
input-disable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
output-enable: true
|
||||
@ -232,7 +515,7 @@ examples:
|
||||
#gpio-cells = <2>;
|
||||
|
||||
pm8921_gpio_keys: gpio-keys-state {
|
||||
volume-keys {
|
||||
volume-keys-pins {
|
||||
pins = "gpio20", "gpio21";
|
||||
function = "normal";
|
||||
|
||||
|
||||
@ -42,8 +42,7 @@ properties:
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
wakeup-parent:
|
||||
maxItems: 1
|
||||
wakeup-parent: true
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
|
||||
@ -0,0 +1,115 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
|
||||
Low Power Island (LPI) TLMM block
|
||||
|
||||
maintainers:
|
||||
- Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
LPASS LPI IP on most Qualcomm SoCs
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-lpass-lpi-pinctrl
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "/schemas/pinctrl/pincfg-node.yaml"
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9])$"
|
||||
minItems: 1
|
||||
maxItems: 15
|
||||
|
||||
function:
|
||||
enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
|
||||
qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
|
||||
dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
|
||||
i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
|
||||
dmic3_data, i2s2_data ]
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
slew-rate:
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description: |
|
||||
0: No adjustments
|
||||
1: Higher Slew rate (faster edges)
|
||||
2: Lower Slew rate (slower edges)
|
||||
3: Reserved (No adjustments)
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lpass_tlmm: pinctrl@33c0000 {
|
||||
compatible = "qcom,sc7280-lpass-lpi-pinctrl";
|
||||
reg = <0x33c0000 0x20000>,
|
||||
<0x3550000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpass_tlmm 0 0 15>;
|
||||
};
|
||||
@ -42,8 +42,7 @@ properties:
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
wakeup-parent:
|
||||
maxItems: 1
|
||||
wakeup-parent: true
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
|
||||
@ -49,8 +49,7 @@ properties:
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
wakeup-parent:
|
||||
maxItems: 1
|
||||
wakeup-parent: true
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
|
||||
@ -49,8 +49,7 @@ properties:
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
wakeup-parent:
|
||||
maxItems: 1
|
||||
wakeup-parent: true
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
|
||||
@ -42,7 +42,6 @@ properties:
|
||||
description:
|
||||
Specifying the interrupt-controller used to wake up the system when the
|
||||
TLMM block has been powered down.
|
||||
maxItems: 1
|
||||
|
||||
gpio-reserved-ranges:
|
||||
description:
|
||||
|
||||
@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ralink MT7620 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Arınç ÜNAL <arinc.unal@arinc9.com>
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description:
|
||||
Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs.
|
||||
The pin controller can only set the muxing of pin groups. Muxing individual
|
||||
pins is not supported. There is no pinconf support.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ralink,mt7620-pinctrl
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
patternProperties:
|
||||
'^(.*-)?pinmux$':
|
||||
type: object
|
||||
description: node for pinctrl.
|
||||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [
|
||||
# For MT7620 SoC
|
||||
ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi, spi refclk,
|
||||
uartf, uartlite, wdt, wled,
|
||||
|
||||
# For MT7628 and MT7688 SoCs
|
||||
gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an,
|
||||
p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0,
|
||||
pwm1, refclk, sdmode, spi, spi cs1, spis, uart0, uart1, uart2,
|
||||
wdt, wled_an, wled_kn,
|
||||
]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
enum: [
|
||||
# For MT7620 SoC
|
||||
ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa,
|
||||
pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk,
|
||||
rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk,
|
||||
wdt rst, wled,
|
||||
|
||||
# For MT7628 and MT7688 SoCs
|
||||
antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn,
|
||||
p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn,
|
||||
p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2,
|
||||
refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1,
|
||||
spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -,
|
||||
]
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,mt7620-pinctrl";
|
||||
|
||||
i2c_pins: i2c0-pins {
|
||||
pinmux {
|
||||
groups = "i2c";
|
||||
function = "i2c";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,21 +1,23 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml#
|
||||
$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ralink rt2880 pinmux controller
|
||||
title: Ralink MT7621 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Arınç ÜNAL <arinc.unal@arinc9.com>
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description:
|
||||
The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
|
||||
is not supported. There is no pinconf support.
|
||||
Ralink MT7621 pin controller for MT7621 SoC.
|
||||
The pin controller can only set the muxing of pin groups. Muxing individual
|
||||
pins is not supported. There is no pinconf support.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ralink,rt2880-pinmux
|
||||
const: ralink,mt7621-pinctrl
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
@ -28,14 +30,15 @@ patternProperties:
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: Name of the pin group to use for the functions.
|
||||
enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi,
|
||||
uart1, uart2, uart3, wdt]
|
||||
description: The pin group to select.
|
||||
enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, uart1,
|
||||
uart2, uart3, wdt]
|
||||
|
||||
function:
|
||||
description: The mux function to select
|
||||
description: The mux function to select.
|
||||
enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
|
||||
pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3,
|
||||
spi, uart1, uart2, uart3, wdt refclk, wdt rst]
|
||||
pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi,
|
||||
uart1, uart2, uart3, wdt refclk, wdt rst]
|
||||
|
||||
required:
|
||||
- groups
|
||||
@ -57,7 +60,7 @@ examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,rt2880-pinmux";
|
||||
compatible = "ralink,mt7621-pinctrl";
|
||||
|
||||
i2c_pins: i2c0-pins {
|
||||
pinmux {
|
||||
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ralink RT2880 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Arınç ÜNAL <arinc.unal@arinc9.com>
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description:
|
||||
Ralink RT2880 pin controller for RT2880 SoC.
|
||||
The pin controller can only set the muxing of pin groups. Muxing individual
|
||||
pins is not supported. There is no pinconf support.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ralink,rt2880-pinctrl
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
patternProperties:
|
||||
'^(.*-)?pinmux$':
|
||||
type: object
|
||||
description: node for pinctrl.
|
||||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,rt2880-pinctrl";
|
||||
|
||||
i2c_pins: i2c0-pins {
|
||||
pinmux {
|
||||
groups = "i2c";
|
||||
function = "i2c";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ralink RT305X Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Arınç ÜNAL <arinc.unal@arinc9.com>
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description:
|
||||
Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350
|
||||
SoCs.
|
||||
The pin controller can only set the muxing of pin groups. Muxing individual
|
||||
pins is not supported. There is no pinconf support.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ralink,rt305x-pinctrl
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
patternProperties:
|
||||
'^(.*-)?pinmux$':
|
||||
type: object
|
||||
description: node for pinctrl.
|
||||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [
|
||||
# For RT3050, RT3052 and RT3350 SoCs
|
||||
i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite,
|
||||
|
||||
# For RT3352 SoC
|
||||
i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, uartf,
|
||||
uartlite,
|
||||
|
||||
# For RT5350 SoC
|
||||
i2c, jtag, led, spi, spi_cs1, uartf, uartlite,
|
||||
]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
enum: [
|
||||
# For RT3050, RT3052 and RT3350 SoCs
|
||||
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, pcm gpio,
|
||||
pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, uartlite,
|
||||
|
||||
# For RT3352 SoC
|
||||
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, mdio,
|
||||
pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf,
|
||||
uartlite, wdg_cs1,
|
||||
|
||||
# For RT5350 SoC
|
||||
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, pcm gpio,
|
||||
pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, wdg_cs1,
|
||||
]
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,rt305x-pinctrl";
|
||||
|
||||
i2c_pins: i2c0-pins {
|
||||
pinmux {
|
||||
groups = "i2c";
|
||||
function = "i2c";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ralink RT3883 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Arınç ÜNAL <arinc.unal@arinc9.com>
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description:
|
||||
Ralink RT3883 pin controller for RT3883 SoC.
|
||||
The pin controller can only set the muxing of pin groups. Muxing individual
|
||||
pins is not supported. There is no pinconf support.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ralink,rt3883-pinctrl
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
patternProperties:
|
||||
'^(.*-)?pinmux$':
|
||||
type: object
|
||||
description: node for pinctrl.
|
||||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, uartf,
|
||||
uartlite]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag,
|
||||
lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2,
|
||||
pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite]
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,rt3883-pinctrl";
|
||||
|
||||
i2c_pins: i2c0-pins {
|
||||
pinmux {
|
||||
groups = "i2c";
|
||||
function = "i2c";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -11,8 +11,8 @@ maintainers:
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
|
||||
description:
|
||||
The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
|
||||
controller.
|
||||
The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
|
||||
GPIO controller.
|
||||
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
|
||||
Each port features up to 8 pins, each of them configurable for GPIO function
|
||||
(port mode) or in alternate function mode.
|
||||
@ -23,6 +23,7 @@ properties:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
|
||||
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
|
||||
|
||||
- items:
|
||||
|
||||
@ -33,6 +33,7 @@ properties:
|
||||
enum:
|
||||
- rockchip,px30-pinctrl
|
||||
- rockchip,rk2928-pinctrl
|
||||
- rockchip,rk3036-pinctrl
|
||||
- rockchip,rk3066a-pinctrl
|
||||
- rockchip,rk3066b-pinctrl
|
||||
- rockchip,rk3128-pinctrl
|
||||
@ -44,6 +45,7 @@ properties:
|
||||
- rockchip,rk3368-pinctrl
|
||||
- rockchip,rk3399-pinctrl
|
||||
- rockchip,rk3568-pinctrl
|
||||
- rockchip,rk3588-pinctrl
|
||||
- rockchip,rv1108-pinctrl
|
||||
|
||||
rockchip,grf:
|
||||
@ -129,7 +131,7 @@ additionalProperties:
|
||||
description:
|
||||
Pin bank index.
|
||||
- minimum: 0
|
||||
maximum: 6
|
||||
maximum: 10
|
||||
description:
|
||||
Mux 0 means GPIO and mux 1 to N means
|
||||
the specific device function.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user