Merge "serial: msm_geni_serial: Add error code for Rx Framing errors"
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761d3f6718
@ -106,6 +106,7 @@ static bool con_enabled = IS_ENABLED(CONFIG_SERIAL_MSM_GENI_CONSOLE_DEFAULT_ENAB
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/* UART DMA Rx GP_IRQ_BITS */
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#define UART_DMA_RX_PARITY_ERR BIT(5)
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#define UART_DMA_RX_FRAMING_ERR BIT(6)
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#define UART_DMA_RX_ERRS (GENMASK(6, 5))
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#define UART_DMA_RX_BREAK (GENMASK(8, 7))
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@ -231,6 +232,7 @@ static void __ftrace_dbg(struct device *dev, const char *fmt, ...)
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* and SOC is not ready to receive data
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* @UART_ERROR_FLOW_OFF: used to indicate when UART is not ready to
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* receive data and flow is turned off
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* @UART_ERROR_RX_FRAMING_ERR: used when Rx framing error encountered
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*/
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enum uart_error_code {
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UART_ERROR_DEFAULT = 0,
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@ -255,6 +257,7 @@ enum uart_error_code {
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UART_ERROR_RX_SBE_ERROR = 19,
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SOC_ERROR_START_TX_IOS_SOC_RFR_HIGH = 20,
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UART_ERROR_FLOW_OFF = 21,
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UART_ERROR_RX_FRAMING_ERR = 22,
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/* keep last */
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UART_ERROR_CODE_MAX,
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@ -2952,61 +2955,69 @@ static bool handle_rx_dma_xfer(u32 s_irq_status, struct uart_port *uport)
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unsigned long lock_flags;
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spin_lock_irqsave(&msm_port->rx_lock, lock_flags);
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dma_rx_status = geni_read_reg(uport->membase,
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SE_DMA_RX_IRQ_STAT);
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dma_rx_status = geni_read_reg(uport->membase, SE_DMA_RX_IRQ_STAT);
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if (dma_rx_status) {
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geni_write_reg(dma_rx_status, uport->membase,
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SE_DMA_RX_IRQ_CLR);
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geni_write_reg(dma_rx_status, uport->membase, SE_DMA_RX_IRQ_CLR);
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if (dma_rx_status & RX_RESET_DONE) {
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s.Reset done. 0x%x.\n", __func__, dma_rx_status);
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"%s Rx Reset done dma_rx_status=0x%x\n",
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__func__, dma_rx_status);
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ret = true;
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}
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if (dma_rx_status & UART_DMA_RX_ERRS) {
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if (dma_rx_status & UART_DMA_RX_PARITY_ERR) {
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uport->icount.parity++;
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msm_geni_update_uart_error_code(msm_port,
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UART_ERROR_RX_PARITY_ERROR);
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}
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s.Rx Errors. 0x%x parity:%d\n",
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__func__, dma_rx_status,
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uport->icount.parity);
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drop_rx = true;
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} else if (dma_rx_status & UART_DMA_RX_BREAK) {
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uport->icount.brk++;
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s.Rx Errors. 0x%x break:%d\n",
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__func__, dma_rx_status,
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uport->icount.brk);
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if (dma_rx_status & UART_DMA_RX_PARITY_ERR) {
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uport->icount.parity++;
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msm_geni_update_uart_error_code(msm_port,
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UART_ERROR_RX_BREAK_ERROR);
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UART_ERROR_RX_PARITY_ERROR);
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s dma_rx_status:0x%x Rx Parity error:%d\n",
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__func__, dma_rx_status,
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uport->icount.parity);
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drop_rx = true;
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}
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if (dma_rx_status & RX_EOT ||
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dma_rx_status & RX_DMA_DONE) {
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msm_geni_serial_handle_dma_rx(uport,
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drop_rx);
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if (dma_rx_status & UART_DMA_RX_FRAMING_ERR) {
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uport->icount.frame++;
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msm_geni_update_uart_error_code(msm_port,
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UART_ERROR_RX_FRAMING_ERR);
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s dma_rx_status:0x%x Rx Framing error:%d\n",
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__func__, dma_rx_status,
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uport->icount.frame);
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drop_rx = true;
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}
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if (dma_rx_status & UART_DMA_RX_BREAK) {
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uport->icount.brk++;
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s dma_rx_status:0x%x Rx Break error:%d\n",
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__func__, dma_rx_status, uport->icount.brk);
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msm_geni_update_uart_error_code(msm_port,
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UART_ERROR_RX_BREAK_ERROR);
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}
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if (dma_rx_status & RX_EOT || dma_rx_status & RX_DMA_DONE) {
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msm_geni_serial_handle_dma_rx(uport, drop_rx);
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if (!(dma_rx_status & RX_GENI_CANCEL_IRQ)) {
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s. mapping rx dma\n", __func__);
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"%s mapping rx dma\n", __func__);
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geni_se_common_rx_dma_start(uport->membase,
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DMA_RX_BUF_SIZE, &msm_port->rx_dma);
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DMA_RX_BUF_SIZE,
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&msm_port->rx_dma);
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} else {
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s. not mapping rx dma\n",
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__func__);
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"%s not mapping rx dma\n", __func__);
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}
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}
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if (dma_rx_status & RX_SBE) {
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UART_LOG_DBG(msm_port->ipc_log_misc, uport->dev,
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"%s.Rx Errors. 0x%x\n",
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__func__, dma_rx_status);
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msm_geni_update_uart_error_code(msm_port, UART_ERROR_RX_SBE_ERROR);
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"%s dma_rx_status:0x%x\n", __func__,
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dma_rx_status);
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msm_geni_update_uart_error_code(msm_port,
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UART_ERROR_RX_SBE_ERROR);
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WARN_ON(1);
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}
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