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Merge "iio: adc: qcom-spmi-adc5-gen3: Update ratios for SMB_* channels for ADC7"

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qctecmdr 2022-06-07 20:50:06 -07:00 committed by Gerrit - the friendly Code Review server
commit 6118b9bca9
8 changed files with 546 additions and 244 deletions
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505
drivers/iio/adc/qcom-spmi-adc5-gen3.c
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@ -15,6 +15,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/thermal.h>
@ -54,7 +55,7 @@ static LIST_HEAD(adc_tm_device_list);
#define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0)
#define ADC5_GEN3_SID 0x4f
#define ADC5_GEN3_SID_MASK 0xf
#define ADC5_GEN3_SID_MASK GENMASK(3, 0)
#define ADC5_GEN3_PERPH_CH 0x50
#define ADC5_GEN3_CHAN_CONV_REQ BIT(7)
@ -114,8 +115,6 @@ static LIST_HEAD(adc_tm_device_list);
#define ADC_TM5_GEN3_LOWER_MASK(n) ((n) & GENMASK(7, 0))
#define ADC_TM5_GEN3_UPPER_MASK(n) (((n) & GENMASK(15, 8)) >> 8)
#define ADC_TM5_GEN3_CHANS_MAX 7
enum adc5_cal_method {
ADC5_NO_CAL = 0,
ADC5_RATIOMETRIC_CAL,
@ -143,6 +142,12 @@ static struct adc_tm_reverse_scale_fn adc_tm_rscale_fn[] = {
[SCALE_R_ABSOLUTE] = {adc_tm_absolute_rthr_gen3},
};
struct adc5_base_data {
u16 base_addr;
const char *irq_name;
int irq;
};
/**
* struct adc5_channel_prop - ADC channel property.
* @channel: channel number, refer to the channel list.
@ -154,6 +159,7 @@ static struct adc_tm_reverse_scale_fn adc_tm_rscale_fn[] = {
* start of conversion.
* @avg_samples: ability to provide single result from the ADC
* that is an average of multiple measurements.
* @sdam_index: Index for which SDAM this channel is on.
* @scale_fn_type: Represents the scaling function to convert voltage
* physical units desired by the client for the channel.
* @datasheet_name: Channel name used in device tree.
@ -169,32 +175,33 @@ static struct adc_tm_reverse_scale_fn adc_tm_rscale_fn[] = {
* @high_thr_voltage: upper threshold voltage for TM.
* @low_thr_voltage: lower threshold voltage for TM.
* @last_temp: last temperature that caused threshold violation,
* or a thermal TM channel.
* or a thermal TM channel.
* @last_temp_set: indicates if last_temp is stored.
* @req_wq: workqueue holding queued notification tasks for a non-thermal
* TM channel.
* TM channel.
* @work: scheduled work for handling non-thermal TM client notification.
* @thr_list: list of client thresholds configured for non-thermal TM channel.
* @adc_rscale_fn: reverse scaling function to convert voltage to raw code
* for non-thermal TM channels.
* for non-thermal TM channels.
*/
struct adc5_channel_prop {
unsigned int channel;
enum adc5_cal_method cal_method;
unsigned int decimation;
unsigned int sid;
unsigned int prescale;
unsigned int hw_settle_time;
unsigned int avg_samples;
unsigned int channel;
enum adc5_cal_method cal_method;
unsigned int decimation;
unsigned int sid;
unsigned int prescale;
unsigned int hw_settle_time;
unsigned int avg_samples;
unsigned int sdam_index;
enum vadc_scale_fn_type scale_fn_type;
const char *datasheet_name;
enum vadc_scale_fn_type scale_fn_type;
const char *datasheet_name;
struct adc5_chip *chip;
/* TM properties */
int adc_tm;
unsigned int tm_chan_index;
unsigned int timer;
int adc_tm;
unsigned int tm_chan_index;
unsigned int timer;
struct thermal_zone_device *tzd;
int high_thr_en;
int low_thr_en;
@ -202,8 +209,8 @@ struct adc5_channel_prop {
bool low_thr_triggered;
int64_t high_thr_voltage;
int64_t low_thr_voltage;
int last_temp;
bool last_temp_set;
int last_temp;
bool last_temp_set;
struct workqueue_struct *req_wq;
struct work_struct work;
struct list_head thr_list;
@ -214,66 +221,56 @@ struct adc5_channel_prop {
* struct adc5_chip - ADC private structure.
* @regmap: SPMI ADC5 peripheral register map field.
* @dev: SPMI ADC5 device.
* @base: base address for the ADC peripheral.
* @base: pointer to array of ADC peripheral base and interrupt.
* @debug_base: base address for the reserved ADC peripheral,
* to dump for debug purposes alone.
* to dump for debug purposes alone.
* @num_sdams: number of SDAMs being used.
* @nchannels: number of ADC channels.
* @chan_props: array of ADC channel properties.
* @iio_chans: array of IIO channels specification.
* @complete: ADC result notification after interrupt is received.
* @lock: ADC lock for access to the peripheral.
* @data: software configuration data.
* @n_tm_channels: number of ADC channels used for TM measurements.
* @list: list item, used to add this device to gloal list of ADC_TM devices.
* @device_list: pointer to list of ADC_TM devices.
* @n_tm_channels: number of ADC channels used for TM measurements.
* @tm_handler_work: scheduled work for handling TM threshold violation.
*/
struct adc5_chip {
struct regmap *regmap;
struct device *dev;
u16 base;
u16 debug_base;
unsigned int nchannels;
struct regmap *regmap;
struct device *dev;
struct adc5_base_data *base;
u16 debug_base;
unsigned int num_sdams;
unsigned int nchannels;
struct adc5_channel_prop *chan_props;
struct iio_chan_spec *iio_chans;
struct completion complete;
struct mutex lock;
const struct adc5_data *data;
struct iio_chan_spec *iio_chans;
struct completion complete;
struct mutex lock;
const struct adc5_data *data;
/* TM properties */
unsigned int n_tm_channels;
unsigned int n_tm_channels;
struct list_head list;
struct list_head *device_list;
struct work_struct tm_handler_work;
struct work_struct tm_handler_work;
};
static const struct u32_fract adc5_prescale_ratios[] = {
{ .numerator = 1, .denominator = 1 },
{ .numerator = 1, .denominator = 3 },
{ .numerator = 1, .denominator = 6 },
{ .numerator = 1, .denominator = 16 },
/* Prescale ratios for current channels below */
{ .numerator = 32, .denominator = 100 }, /* IIN_FB */
{ .numerator = 14, .denominator = 100 }, /* ICHG_SMB */
{ .numerator = 28, .denominator = 100 }, /* IIN_SMB */
{ .numerator = 1000, .denominator = 305185 }, /* ICHG_FB */
};
static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
static int adc5_read(struct adc5_chip *adc, unsigned int sdam_index, u16 offset, u8 *data, int len)
{
int ret;
ret = regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
ret = regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
if (ret < 0)
pr_err("adc read to register 0x%x of length:%d failed, ret=%d\n", offset, len, ret);
return ret;
}
static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
static int adc5_write(struct adc5_chip *adc, unsigned int sdam_index, u16 offset, u8 *data, int len)
{
int ret;
ret = regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
ret = regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
if (ret < 0)
pr_err("adc write to register 0x%x of length:%d failed, ret=%d\n", offset, len,
ret);
@ -281,22 +278,6 @@ static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
return ret;
}
static int adc5_prescaling_from_dt(u32 numerator, u32 denominator)
{
unsigned int pre;
for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++) {
if (adc5_prescale_ratios[pre].numerator == numerator &&
adc5_prescale_ratios[pre].denominator == denominator)
break;
}
if (pre == ARRAY_SIZE(adc5_prescale_ratios))
return -ENOENT;
return pre;
}
static int adc5_hw_settle_time_from_dt(u32 value,
const unsigned int *hw_settle)
{
@ -331,12 +312,13 @@ static int adc5_decimation_from_dt(u32 value,
return -ENOENT;
}
static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data)
static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data,
struct adc5_channel_prop *prop)
{
int ret;
u8 rslt[2];
ret = adc5_read(adc, ADC5_GEN3_CH0_DATA0, rslt, 2);
ret = adc5_read(adc, prop->sdam_index, ADC5_GEN3_CH0_DATA0, rslt, 2);
if (ret < 0)
return ret;
@ -370,13 +352,12 @@ static int adc5_gen3_configure(struct adc5_chip *adc,
int ret;
u8 conv_req = 0, buf[7];
ret = adc5_read(adc, ADC5_GEN3_SID, buf, sizeof(buf));
ret = adc5_read(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
if (ret < 0)
return ret;
/* Write SID */
buf[0] &= (u8) ~ADC5_GEN3_SID_MASK;
buf[0] &= prop->sid;
buf[0] = prop->sid & ADC5_GEN3_SID_MASK;
/*
* Use channel 0 by default for immediate conversion and
@ -402,27 +383,27 @@ static int adc5_gen3_configure(struct adc5_chip *adc,
reinit_completion(&adc->complete);
ret = adc5_write(adc, ADC5_GEN3_SID, buf, sizeof(buf));
ret = adc5_write(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
if (ret < 0)
return ret;
conv_req = ADC5_GEN3_CONV_REQ_REQ;
ret = adc5_write(adc, ADC5_GEN3_CONV_REQ, &conv_req, 1);
ret = adc5_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1);
return ret;
}
#define ADC5_GEN3_HS_DELAY_MIN_US 100
#define ADC5_GEN3_HS_DELAY_MAX_US 110
#define ADC5_GEN3_HS_RETRY_COUNT 20
#define ADC5_GEN3_HS_RETRY_COUNT 20
static int adc5_gen3_poll_wait_hs(struct adc5_chip *adc)
static int adc5_gen3_poll_wait_hs(struct adc5_chip *adc, struct adc5_channel_prop *prop)
{
int ret, count;
u8 status = 0;
for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) {
ret = adc5_read(adc, ADC5_GEN3_HS, &status, 1);
ret = adc5_read(adc, prop->sdam_index, ADC5_GEN3_HS, &status, 1);
if (ret < 0)
return ret;
@ -453,7 +434,7 @@ static int adc5_gen3_do_conversion(struct adc5_chip *adc,
u8 val;
mutex_lock(&adc->lock);
ret = adc5_gen3_poll_wait_hs(adc);
ret = adc5_gen3_poll_wait_hs(adc, prop);
if (ret < 0)
goto unlock;
@ -477,23 +458,23 @@ static int adc5_gen3_do_conversion(struct adc5_chip *adc,
pr_debug("ADC channel %s EOC took %u ms\n", prop->datasheet_name,
ADC5_GEN3_CONV_TIMEOUT_MS - time_pending_ms);
ret = adc5_gen3_read_voltage_data(adc, data_volt);
ret = adc5_gen3_read_voltage_data(adc, data_volt, prop);
if (ret < 0)
goto unlock;
val = BIT(0);
ret = adc5_write(adc, ADC5_GEN3_EOC_CLR, &val, 1);
ret = adc5_write(adc, prop->sdam_index, ADC5_GEN3_EOC_CLR, &val, 1);
if (ret < 0)
goto unlock;
/* To indicate conversion request is only to clear a status */
val = 0;
ret = adc5_write(adc, ADC5_GEN3_PERPH_CH, &val, 1);
ret = adc5_write(adc, prop->sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
if (ret < 0)
goto unlock;
val = ADC5_GEN3_CONV_REQ_REQ;
ret = adc5_write(adc, ADC5_GEN3_CONV_REQ, &val, 1);
ret = adc5_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
unlock:
mutex_unlock(&adc->lock);
@ -501,44 +482,62 @@ static int adc5_gen3_do_conversion(struct adc5_chip *adc,
return ret;
}
#define ADC_OFFSET_DUMP 8
#define ADC_SDAM_REG_DUMP 32
static void adc5_gen3_dump_regs_debug(struct adc5_chip *adc)
#define ADC_OFFSET_DUMP 8
#define ADC_SDAM_REG_DUMP 32
static void adc5_gen3_dump_register(struct adc5_chip *adc, unsigned int offset)
{
int rc = 0, i = 0, j = 0, offset;
int i, rc;
u8 buf[8];
for (j = 0; j < 2; j++) {
if (!j) {
offset = adc->base;
pr_debug("ADC SDAM DUMP\n");
} else {
if (adc->debug_base)
offset = adc->debug_base;
else
break;
pr_debug("SDAM 20 DUMP\n");
}
for (i = 0; i < ADC_SDAM_REG_DUMP; i++) {
rc = regmap_bulk_read(adc->regmap, offset, buf, sizeof(buf));
if (rc < 0) {
pr_err("debug register dump failed\n");
return;
}
offset += ADC_OFFSET_DUMP;
pr_debug("Buf[%d]: %*ph\n", i, sizeof(buf), buf);
for (i = 0; i < ADC_SDAM_REG_DUMP; i++) {
rc = regmap_bulk_read(adc->regmap, offset, buf, sizeof(buf));
if (rc < 0) {
pr_err("debug register dump failed with rc=%d\n", rc);
return;
}
offset += ADC_OFFSET_DUMP;
pr_debug("Buf[%d]: %*ph\n", i, sizeof(buf), buf);
}
}
static void adc5_gen3_dump_regs_debug(struct adc5_chip *adc)
{
int i = 0;
for (i = 0; i < adc->num_sdams; i++) {
pr_debug("ADC SDAM%d DUMP\n", i);
adc5_gen3_dump_register(adc, adc->base[i].base_addr);
}
if (adc->debug_base) {
pr_debug("ADC Debug base DUMP\n");
adc5_gen3_dump_register(adc, adc->debug_base);
}
}
static int get_sdam_from_irq(struct adc5_chip *adc, int irq)
{
int i;
for (i = 0; i < adc->num_sdams; i++) {
if (adc->base[i].irq == irq)
return i;
}
return -ENOENT;
}
static irqreturn_t adc5_gen3_isr(int irq, void *dev_id)
{
struct adc5_chip *adc = dev_id;
u8 status, tm_status[2], eoc_status, val;
int ret;
int ret, sdam_num;
ret = adc5_read(adc, ADC5_GEN3_EOC_STS, &eoc_status, 1);
sdam_num = get_sdam_from_irq(adc, irq);
if (sdam_num < 0) {
pr_err("adc irq %d not associated with an sdam\n", irq);
goto handler_end;
}
ret = adc5_read(adc, sdam_num, ADC5_GEN3_EOC_STS, &eoc_status, 1);
if (ret < 0) {
pr_err("adc read eoc status failed with %d\n", ret);
goto handler_end;
@ -548,7 +547,7 @@ static irqreturn_t adc5_gen3_isr(int irq, void *dev_id)
if (eoc_status & ADC5_GEN3_EOC_CHAN_0)
complete(&adc->complete);
ret = adc5_read(adc, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
ret = adc5_read(adc, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
if (ret < 0) {
pr_err("adc read TM status failed with %d\n", ret);
goto handler_end;
@ -557,7 +556,7 @@ static irqreturn_t adc5_gen3_isr(int irq, void *dev_id)
if (tm_status[0] || tm_status[1])
schedule_work(&adc->tm_handler_work);
ret = adc5_read(adc, ADC5_GEN3_STATUS1, &status, 1);
ret = adc5_read(adc, sdam_num, ADC5_GEN3_STATUS1, &status, 1);
if (ret < 0) {
pr_err("adc read status1 failed with %d\n", ret);
goto handler_end;
@ -571,70 +570,35 @@ static irqreturn_t adc5_gen3_isr(int irq, void *dev_id)
adc5_gen3_dump_regs_debug(adc);
val = ADC5_GEN3_CONV_ERR_CLR_REQ;
ret = adc5_write(adc, ADC5_GEN3_CONV_ERR_CLR, &val, 1);
ret = adc5_write(adc, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val, 1);
if (ret < 0)
goto handler_end;
/* To indicate conversion request is only to clear a status */
val = 0;
ret = adc5_write(adc, ADC5_GEN3_PERPH_CH, &val, 1);
ret = adc5_write(adc, sdam_num, ADC5_GEN3_PERPH_CH, &val, 1);
if (ret < 0)
goto handler_end;
val = ADC5_GEN3_CONV_REQ_REQ;
ret = adc5_write(adc, ADC5_GEN3_CONV_REQ, &val, 1);
ret = adc5_write(adc, sdam_num, ADC5_GEN3_CONV_REQ, &val, 1);
if (ret < 0)
goto handler_end;
}
handler_end:
return IRQ_HANDLED;
handler_end:
return IRQ_NONE;
}
static void tm_handler_work(struct work_struct *work)
{
struct adc5_chip *adc = container_of(work, struct adc5_chip,
tm_handler_work);
struct adc5_channel_prop *chan_prop;
u8 tm_status[2], buf[16], val;
int ret, i;
mutex_lock(&adc->lock);
ret = adc5_read(adc, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
if (ret < 0) {
pr_err("adc read TM status failed with %d\n", ret);
goto work_unlock;
}
ret = adc5_write(adc, ADC5_GEN3_TM_HIGH_STS_CLR, tm_status, 2);
if (ret < 0) {
pr_err("adc write TM status failed with %d\n", ret);
goto work_unlock;
}
/* To indicate conversion request is only to clear a status */
val = 0;
ret = adc5_write(adc, ADC5_GEN3_PERPH_CH, &val, 1);
if (ret < 0) {
pr_err("adc write status clear conv_req failed with %d\n", ret);
goto work_unlock;
}
val = ADC5_GEN3_CONV_REQ_REQ;
ret = adc5_write(adc, ADC5_GEN3_CONV_REQ, &val, 1);
if (ret < 0) {
pr_err("adc write conv_req failed with %d\n", ret);
goto work_unlock;
}
ret = adc5_read(adc, ADC5_GEN3_CH0_DATA0, buf, sizeof(buf));
if (ret < 0) {
pr_err("adc read data failed with %d\n", ret);
goto work_unlock;
}
mutex_unlock(&adc->lock);
int ret, i, sdam_index = -1;
struct adc5_chip *adc = container_of(work, struct adc5_chip,
tm_handler_work);
for (i = 0; i < adc->nchannels; i++) {
bool upper_set = false, lower_set = false;
@ -644,10 +608,47 @@ static void tm_handler_work(struct work_struct *work)
chan_prop = &adc->chan_props[i];
offset = chan_prop->tm_chan_index;
if (!chan_prop->adc_tm)
if (chan_prop->adc_tm != ADC_TM && chan_prop->adc_tm != ADC_TM_NON_THERMAL)
continue;
mutex_lock(&adc->lock);
if (chan_prop->sdam_index != sdam_index) {
sdam_index = chan_prop->sdam_index;
ret = adc5_read(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
if (ret < 0) {
pr_err("adc read TM status failed with %d\n", ret);
goto work_unlock;
}
ret = adc5_write(adc, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR, tm_status, 2);
if (ret < 0) {
pr_err("adc write TM status failed with %d\n", ret);
goto work_unlock;
}
/* To indicate conversion request is only to clear a status */
val = 0;
ret = adc5_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
if (ret < 0) {
pr_err("adc write status clear conv_req failed with %d\n", ret);
goto work_unlock;
}
val = ADC5_GEN3_CONV_REQ_REQ;
ret = adc5_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
if (ret < 0) {
pr_err("adc write conv_req failed with %d\n", ret);
goto work_unlock;
}
ret = adc5_read(adc, sdam_index, ADC5_GEN3_CH0_DATA0, buf, sizeof(buf));
if (ret < 0) {
pr_err("adc read data failed with %d\n", ret);
goto work_unlock;
}
}
if ((tm_status[0] & BIT(offset)) && (chan_prop->high_thr_en))
upper_set = true;
@ -802,17 +803,16 @@ static int adc_tm5_gen3_configure(struct adc5_channel_prop *prop)
u32 mask = 0;
struct adc5_chip *adc = prop->chip;
ret = adc5_gen3_poll_wait_hs(adc);
ret = adc5_gen3_poll_wait_hs(adc, prop);
if (ret < 0)
return ret;
ret = adc5_read(adc, ADC5_GEN3_SID, buf, sizeof(buf));
ret = adc5_read(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
if (ret < 0)
return ret;
/* Write SID */
buf[0] &= (u8) ~ADC5_GEN3_SID_MASK;
buf[0] &= prop->sid;
buf[0] = prop->sid & ADC5_GEN3_SID_MASK;
/*
* Select TM channel and indicate there is an actual
@ -846,12 +846,12 @@ static int adc_tm5_gen3_configure(struct adc5_channel_prop *prop)
buf[10] = ADC_TM5_GEN3_LOWER_MASK(mask);
buf[11] = ADC_TM5_GEN3_UPPER_MASK(mask);
ret = adc5_write(adc, ADC5_GEN3_SID, buf, sizeof(buf));
ret = adc5_write(adc, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
if (ret < 0)
return ret;
conv_req = ADC5_GEN3_CONV_REQ_REQ;
return adc5_write(adc, ADC5_GEN3_CONV_REQ, &conv_req, 1);
return adc5_write(adc, prop->sdam_index, ADC5_GEN3_CONV_REQ, &conv_req, 1);
}
static int adc_tm5_gen3_set_trip_temp(void *data,
@ -1292,13 +1292,13 @@ static int adc_tm_register_tzd(struct adc5_chip *adc)
default:
pr_err("Invalid ADC_TM type:%d for dt_ch:%d\n",
adc->chan_props[i].adc_tm, adc->chan_props[i].channel);
continue;
return -EINVAL;
}
if (IS_ERR(tzd)) {
pr_err("Error registering TZ zone:%ld for dt_ch:%d\n",
PTR_ERR(tzd), adc->chan_props[i].channel);
continue;
return PTR_ERR(tzd);
}
adc->chan_props[i].tzd = tzd;
}
@ -1341,51 +1341,53 @@ struct adc5_channels {
static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
[ADC5_GEN3_OFFSET_REF] = ADC5_CHAN_VOLT("ref_gnd", 0,
SCALE_HW_CALIB_DEFAULT)
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
SCALE_HW_CALIB_DEFAULT)
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT("vbat_sns", 1,
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_AMUX3_THM] = ADC5_CHAN_TEMP("smb_temp", 0,
SCALE_HW_CALIB_PM7_SMB_TEMP)
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT("vbat_sns", 1,
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_AMUX3_THM] = ADC5_CHAN_TEMP("smb_temp", 9,
SCALE_HW_CALIB_PM7_SMB_TEMP)
[ADC5_GEN3_CHG_TEMP] = ADC5_CHAN_TEMP("chg_temp", 0,
SCALE_HW_CALIB_PM7_CHG_TEMP)
[ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP("usb_sns_v_div_16", 3,
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP("vin_div_16", 3,
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_IIN_FB] = ADC5_CHAN_CUR("iin_fb", 4,
SCALE_HW_CALIB_CUR)
[ADC5_GEN3_ICHG_SMB] = ADC5_CHAN_CUR("ichg_smb", 5,
SCALE_HW_CALIB_CUR)
[ADC5_GEN3_IIN_SMB] = ADC5_CHAN_CUR("iin_smb", 6,
SCALE_HW_CALIB_CUR)
[ADC5_GEN3_ICHG_FB] = ADC5_CHAN_CUR("ichg_fb", 7,
SCALE_HW_CALIB_CUR_RAW)
SCALE_HW_CALIB_PM7_CHG_TEMP)
[ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP("usb_sns_v_div_16", 8,
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP("vin_div_16", 8,
SCALE_HW_CALIB_DEFAULT)
[ADC5_GEN3_IIN_FB] = ADC5_CHAN_CUR("iin_fb", 10,
SCALE_HW_CALIB_CUR)
[ADC5_GEN3_ICHG_SMB] = ADC5_CHAN_CUR("ichg_smb", 13,
SCALE_HW_CALIB_CUR)
[ADC5_GEN3_IIN_SMB] = ADC5_CHAN_CUR("iin_smb", 12,
SCALE_HW_CALIB_CUR)
[ADC5_GEN3_ICHG_FB] = ADC5_CHAN_CUR("ichg_fb", 16,
SCALE_HW_CALIB_CUR_RAW)
[ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
SCALE_HW_CALIB_PMIC_THERM_PM7)
SCALE_HW_CALIB_PMIC_THERM_PM7)
[ADC5_GEN3_TEMP_ALARM_LITE] = ADC5_CHAN_TEMP("die_temp_lite", 0,
SCALE_HW_CALIB_PMIC_THERM_PM7)
[ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP("amux1_gpio_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP("amux2_gpio_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP("amux3_gpio_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
[ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP("amux4_gpio_pu2", 0,
SCALE_HW_CALIB_THERM_100K_PU_PM7)
SCALE_HW_CALIB_THERM_100K_PU_PM7)
};
static int adc5_get_dt_channel_data(struct adc5_chip *adc,
@ -1396,7 +1398,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc,
const char *name = node->name, *channel_name;
u32 chan, value, varr[2];
u32 sid = 0;
int ret;
int ret, val;
struct device *dev = adc->dev;
ret = of_property_read_u32(node, "reg", &chan);
@ -1445,7 +1447,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc,
ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
if (!ret) {
ret = adc5_prescaling_from_dt(varr[0], varr[1]);
ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
if (ret < 0) {
dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
chan, varr[0], varr[1]);
@ -1510,12 +1512,16 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc,
if (prop->adc_tm && prop->adc_tm != ADC_TM_IIO) {
adc->n_tm_channels++;
if (adc->n_tm_channels > ADC_TM5_GEN3_CHANS_MAX) {
pr_err("Number of TM nodes greater than channels supported:%d\n",
adc->n_tm_channels);
if (adc->n_tm_channels > ((adc->num_sdams * 8) - 1)) {
pr_err("Number of TM nodes %u greater than channels supported:%u\n",
adc->n_tm_channels, (adc->num_sdams * 8) - 1);
return -EINVAL;
}
prop->tm_chan_index = adc->n_tm_channels;
val = adc->n_tm_channels / 8;
prop->sdam_index = val;
prop->tm_chan_index = adc->n_tm_channels - (8*val);
prop->timer = MEAS_INT_1S;
if (prop->adc_tm == ADC_TM_NON_THERMAL) {
@ -1561,7 +1567,7 @@ static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
{
const struct adc5_channels *adc_chan;
struct iio_chan_spec *iio_chan;
struct adc5_channel_prop prop, *chan_props;
struct adc5_channel_prop *chan_props;
struct device_node *child;
unsigned int index = 0;
const struct of_device_id *id;
@ -1593,22 +1599,20 @@ static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
adc->data = data;
for_each_available_child_of_node(node, child) {
ret = adc5_get_dt_channel_data(adc, &prop, child, data);
ret = adc5_get_dt_channel_data(adc, chan_props, child, data);
if (ret < 0) {
of_node_put(child);
return ret;
}
prop.chip = adc;
if (prop.scale_fn_type == -EINVAL)
prop.scale_fn_type =
data->adc_chans[prop.channel].scale_fn_type;
*chan_props = prop;
adc_chan = &data->adc_chans[prop.channel];
iio_chan->channel = prop.channel;
iio_chan->datasheet_name = prop.datasheet_name;
iio_chan->extend_name = prop.datasheet_name;
chan_props->chip = adc;
if (chan_props->scale_fn_type == -EINVAL)
chan_props->scale_fn_type =
data->adc_chans[chan_props->channel].scale_fn_type;
adc_chan = &data->adc_chans[chan_props->channel];
iio_chan->channel = chan_props->channel;
iio_chan->datasheet_name = chan_props->datasheet_name;
iio_chan->extend_name = chan_props->datasheet_name;
iio_chan->info_mask_separate = adc_chan->info_mask;
iio_chan->type = adc_chan->type;
iio_chan->address = index;
@ -1627,19 +1631,14 @@ static int adc5_gen3_probe(struct platform_device *pdev)
struct iio_dev *indio_dev;
struct adc5_chip *adc;
struct regmap *regmap;
const char *irq_name;
const __be32 *prop_addr;
int ret, irq_eoc, i;
int ret, i;
u32 reg;
char buf[20];
regmap = dev_get_regmap(dev->parent, NULL);
if (!regmap)
return -ENODEV;
ret = of_property_read_u32(node, "reg", &reg);
if (ret < 0)
return ret;
indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
if (!indio_dev)
return -ENOMEM;
@ -1648,18 +1647,38 @@ static int adc5_gen3_probe(struct platform_device *pdev)
adc->regmap = regmap;
adc->dev = dev;
prop_addr = of_get_address(dev->of_node, 0, NULL, NULL);
if (!prop_addr) {
pr_err("invalid IO resource\n");
return -EINVAL;
}
adc->base = be32_to_cpu(*prop_addr);
ret = of_property_count_u32_elems(node, "reg");
if (ret < 0)
return ret;
prop_addr = of_get_address(dev->of_node, 1, NULL, NULL);
if (!prop_addr)
pr_debug("invalid debug resource\n");
else
adc->debug_base = be32_to_cpu(*prop_addr);
adc->num_sdams = ret;
adc->base = devm_kcalloc(adc->dev, adc->num_sdams, sizeof(*adc->base), GFP_KERNEL);
if (!adc->base)
return -ENOMEM;
for (i = 0; i < adc->num_sdams; i++) {
ret = of_property_read_u32_index(node, "reg", i, &reg);
if (ret < 0)
return ret;
adc->base[i].base_addr = reg;
scnprintf(buf, sizeof(buf), "adc-sdam%d", i);
ret = of_irq_get_byname(node, buf);
if (ret < 0) {
pr_err("Failed to get irq for ADC5 GEN3 SDAM%d, ret=%d\n", i, ret);
return ret;
}
adc->base[i].irq = ret;
adc->base[i].irq_name = devm_kstrdup(adc->dev, buf, GFP_KERNEL);
if (!adc->base[i].irq_name)
return -ENOMEM;
}
if (!of_property_read_u32(node, "qcom,debug-base", &reg))
adc->debug_base = reg;
platform_set_drvdata(pdev, adc);
@ -1674,15 +1693,14 @@ static int adc5_gen3_probe(struct platform_device *pdev)
goto fail;
}
adc_tm_register_tzd(adc);
for (i = 0; i < adc->num_sdams; i++) {
ret = devm_request_irq(dev, adc->base[i].irq, adc5_gen3_isr,
0, adc->base[i].irq_name, adc);
if (ret < 0)
goto fail;
}
irq_eoc = platform_get_irq(pdev, 0);
irq_name = "pm-adc5";
if (adc->data->name)
irq_name = adc->data->name;
ret = devm_request_irq(dev, irq_eoc, adc5_gen3_isr, 0,
irq_name, adc);
ret = adc_tm_register_tzd(adc);
if (ret < 0)
goto fail;
@ -1715,7 +1733,7 @@ static int adc5_gen3_exit(struct platform_device *pdev)
{
struct adc5_chip *adc = platform_get_drvdata(pdev);
u8 data = 0;
int i;
int i, sdam_index;
mutex_lock(&adc->lock);
for (i = 0; i < adc->nchannels; i++) {
@ -1725,16 +1743,17 @@ static int adc5_gen3_exit(struct platform_device *pdev)
}
/* Disable all available channels */
for (i = 0; i < 8; i++) {
for (i = 0; i < adc->num_sdams * 8; i++) {
sdam_index = i / 8;
data = MEAS_INT_DISABLE;
adc5_write(adc, ADC5_GEN3_TIMER_SEL, &data, 1);
adc5_write(adc, sdam_index, ADC5_GEN3_TIMER_SEL, &data, 1);
/* To indicate there is an actual conversion request */
data = ADC5_GEN3_CHAN_CONV_REQ | i;
adc5_write(adc, ADC5_GEN3_PERPH_CH, &data, 1);
data = ADC5_GEN3_CHAN_CONV_REQ | (i - (sdam_index*8));
adc5_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &data, 1);
data = ADC5_GEN3_CONV_REQ_REQ;
adc5_write(adc, ADC5_GEN3_CONV_REQ, &data, 1);
adc5_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &data, 1);
}
mutex_unlock(&adc->lock);

2
drivers/iio/adc/qcom-vadc-common.c
View File

@ -614,6 +614,8 @@ static const struct u32_fract adc5_prescale_ratios[] = {
{ .numerator = 640, .denominator = 4100 }, /* ICHG_SMB_new */
{ .numerator = 1000, .denominator = 305185 }, /* ICHG_FB */
{ .numerator = 1000, .denominator = 610370 }, /* ICHG_FB_2X */
{ .numerator = 1000, .denominator = 366220 }, /* ICHG_FB ADC5_GEN3 */
{ .numerator = 1000, .denominator = 732440 }, /* ICHG_FB_2X ADC5_GEN3 */
};
static int qcom_vadc_scale_hw_calib_volt(

48
include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550.h Normal file
View File

@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
#ifndef PM8550_SID
#define PM8550_SID 1
#endif
/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
#define PM8550_ADC5_GEN3_OFFSET_REF (PM8550_SID << 8 | 0x00)
#define PM8550_ADC5_GEN3_1P25VREF (PM8550_SID << 8 | 0x01)
#define PM8550_ADC5_GEN3_VREF_VADC (PM8550_SID << 8 | 0x02)
#define PM8550_ADC5_GEN3_DIE_TEMP (PM8550_SID << 8 | 0x03)
#define PM8550_ADC5_GEN3_AMUX_THM1 (PM8550_SID << 8 | 0x04)
#define PM8550_ADC5_GEN3_AMUX_THM2 (PM8550_SID << 8 | 0x05)
#define PM8550_ADC5_GEN3_AMUX_THM3 (PM8550_SID << 8 | 0x06)
#define PM8550_ADC5_GEN3_AMUX_THM4 (PM8550_SID << 8 | 0x07)
#define PM8550_ADC5_GEN3_AMUX_THM5 (PM8550_SID << 8 | 0x08)
#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2 (PM8550_SID << 8 | 0x09)
#define PM8550_ADC5_GEN3_AMUX1_GPIO3 (PM8550_SID << 8 | 0x0a)
#define PM8550_ADC5_GEN3_AMUX2_GPIO4 (PM8550_SID << 8 | 0x0b)
#define PM8550_ADC5_GEN3_AMUX3_GPIO7 (PM8550_SID << 8 | 0x0c)
#define PM8550_ADC5_GEN3_AMUX4_GPIO12 (PM8550_SID << 8 | 0x0d)
/* 100k pull-up */
#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU (PM8550_SID << 8 | 0x44)
#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU (PM8550_SID << 8 | 0x45)
#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU (PM8550_SID << 8 | 0x46)
#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU (PM8550_SID << 8 | 0x47)
#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU (PM8550_SID << 8 | 0x48)
#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU (PM8550_SID << 8 | 0x49)
#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU (PM8550_SID << 8 | 0x4a)
#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU (PM8550_SID << 8 | 0x4b)
#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU (PM8550_SID << 8 | 0x4c)
#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550_SID << 8 | 0x4d)
/* 1/3 Divider */
#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3 (PM8550_SID << 8 | 0x8c)
#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3 (PM8550_SID << 8 | 0x8d)
#define PM8550_ADC5_GEN3_VPH_PWR (PM8550_SID << 8 | 0x8e)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */

97
include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550b.h Normal file
View File

@ -0,0 +1,97 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
#ifndef PM8550B_SID
#define PM8550B_SID 7
#endif
/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
#define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00)
#define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01)
#define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02)
#define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03)
#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04)
#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05)
#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06)
#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07)
#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08)
#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09)
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c)
#define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d)
#define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10)
#define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11)
#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12)
#define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13)
#define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15)
#define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17)
#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18)
#define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19)
#define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a)
#define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b)
#define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e)
#define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f)
#define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1)
/* 30k pull-up */
#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24)
#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25)
#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26)
#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27)
#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28)
#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29)
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c)
#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d)
#define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33)
/* 100k pull-up */
#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44)
#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45)
#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46)
#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47)
#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48)
#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49)
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c)
#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d)
#define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53)
/* 400k pull-up */
#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64)
#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65)
#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66)
#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67)
#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68)
#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69)
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c)
#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d)
#define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73)
/* 1/3 Divider */
#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a)
#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b)
#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c)
#define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e)
#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f)
#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94)
#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96)
#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pm8550vx.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
#ifndef PM8550VS_C_SID
#define PM8550VS_C_SID 2
#endif
#ifndef PM8550VS_D_SID
#define PM8550VS_D_SID 3
#endif
#ifndef PM8550VS_E_SID
#define PM8550VS_E_SID 4
#endif
#ifndef PM8550VS_G_SID
#define PM8550VS_G_SID 6
#endif
#ifndef PM8550VE_SID
#define PM8550VE_SID 5
#endif
/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
#define PM8550VS_C_ADC5_GEN3_OFFSET_REF (PM8550VS_C_SID << 8 | 0x00)
#define PM8550VS_C_ADC5_GEN3_1P25VREF (PM8550VS_C_SID << 8 | 0x01)
#define PM8550VS_C_ADC5_GEN3_VREF_VADC (PM8550VS_C_SID << 8 | 0X02)
#define PM8550VS_C_ADC5_GEN3_DIE_TEMP (PM8550VS_C_SID << 8 | 0x03)
#define PM8550VS_D_ADC5_GEN3_OFFSET_REF (PM8550VS_D_SID << 8 | 0x00)
#define PM8550VS_D_ADC5_GEN3_1P25VREF (PM8550VS_D_SID << 8 | 0x01)
#define PM8550VS_D_ADC5_GEN3_VREF_VADC (PM8550VS_D_SID << 8 | 0X02)
#define PM8550VS_D_ADC5_GEN3_DIE_TEMP (PM8550VS_D_SID << 8 | 0x03)
#define PM8550VS_E_ADC5_GEN3_OFFSET_REF (PM8550VS_E_SID << 8 | 0x00)
#define PM8550VS_E_ADC5_GEN3_1P25VREF (PM8550VS_E_SID << 8 | 0x01)
#define PM8550VS_E_ADC5_GEN3_VREF_VADC (PM8550VS_E_SID << 8 | 0X02)
#define PM8550VS_E_ADC5_GEN3_DIE_TEMP (PM8550VS_E_SID << 8 | 0x03)
#define PM8550VS_G_ADC5_GEN3_OFFSET_REF (PM8550VS_G_SID << 8 | 0x00)
#define PM8550VS_G_ADC5_GEN3_1P25VREF (PM8550VS_G_SID << 8 | 0x01)
#define PM8550VS_G_ADC5_GEN3_VREF_VADC (PM8550VS_G_SID << 8 | 0X02)
#define PM8550VS_G_ADC5_GEN3_DIE_TEMP (PM8550VS_G_SID << 8 | 0x03)
#define PM8550VE_ADC5_GEN3_OFFSET_REF (PM8550VE_SID << 8 | 0x00)
#define PM8550VE_ADC5_GEN3_1P25VREF (PM8550VE_SID << 8 | 0x01)
#define PM8550VE_ADC5_GEN3_VREF_VADC (PM8550VE_SID << 8 | 0X02)
#define PM8550VE_ADC5_GEN3_DIE_TEMP (PM8550VE_SID << 8 | 0x03)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-pmk8550.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
#ifndef PMK8550_SID
#define PMK8550_SID 0
#endif
/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
#define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00)
#define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01)
#define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02)
#define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03)
#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04)
#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05)
#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06)
#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07)
#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08)
#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09)
#define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a)
/* 30k pull-up */
#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24)
#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25)
#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26)
#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27)
#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28)
#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29)
#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a)
/* 100k pull-up */
#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44)
#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45)
#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46)
#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47)
#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48)
#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49)
#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a)
/* 400k pull-up */
#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64)
#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65)
#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66)
#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67)
#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68)
#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69)
#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a)
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */

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include/dt-bindings/iio/qcom,spmi-adc5-gen3-smb139x.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_GEN3_SMB139X_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_GEN3_SMB139X_H
#ifndef SMB1394_1_SID
#define SMB1394_1_SID 0x09
#endif
#ifndef SMB1394_2_SID
#define SMB1394_2_SID 0x0b
#endif
#define SMB1394_1_ADC5_GEN3_SMB_TEMP (SMB1394_1_SID << 8 | 0x06)
#define SMB1394_1_ADC5_GEN3_IIN_SMB (SMB1394_1_SID << 8 | 0x19)
#define SMB1394_1_ADC5_GEN3_ICHG_SMB (SMB1394_1_SID << 8 | 0x1b)
#define SMB1394_2_ADC5_GEN3_SMB_TEMP (SMB1394_2_SID << 8 | 0x06)
#define SMB1394_2_ADC5_GEN3_IIN_SMB (SMB1394_2_SID << 8 | 0x19)
#define SMB1394_2_ADC5_GEN3_ICHG_SMB (SMB1394_2_SID << 8 | 0x1b)
#endif

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include/dt-bindings/iio/qcom,spmi-vadc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2014,2018-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
@ -323,8 +324,9 @@
#define ADC5_GEN3_VIN_DIV16_MUX 0x12
#define ADC5_GEN3_VREF_BAT_THERM 0x15
#define ADC5_GEN3_IIN_FB 0x17
#define ADC5_GEN3_ICHG_SMB 0x18
#define ADC5_GEN3_TEMP_ALARM_LITE 0x18
#define ADC5_GEN3_IIN_SMB 0x19
#define ADC5_GEN3_ICHG_SMB 0x1b
#define ADC5_GEN3_ICHG_FB 0xa1
/* 30k pull-up1 */