dmaengine: msm_gpi: add GPI dmaengine driver snapshot for pineapple
This is a snapshot of gpi dmaengine driver and associated files
as of msm-5.15 'commit 8d5f6e9fa5567 ("dmaengine: msm_gpi: add
GPI dmaengine driver snapshot for kalama")'.
Change-Id: I98aed9e09d927225776d9f4533ca74a7cf7c078b
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
This commit is contained in:
Anil Veshala Veshala
Gerrit - the friendly Code Review server
parent
21315ac40e
commit
5f7523ae5f
@ -31,6 +31,27 @@ config QCOM_GPI_DMA
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can use a standardize interface that is protocol independent to
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transfer data between DDR and peripheral.
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config MSM_GPI_DMA
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tristate "Qualcomm Technologies Inc GPI DMA support"
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depends on ARCH_QCOM
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Enable support for the QCOM GPI DMA controller. This controller
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provides DMA capabilities for a variety of peripheral buses such
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as I2C, UART, and SPI. By using GPI dmaengine driver, bus drivers
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can use a standardize interface that is protocol independent to
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transfer data between DDR and peripheral.
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config MSM_GPI_DMA_DEBUG
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bool "Qualcomm Technologies Inc GPI debug support"
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depends on MSM_GPI_DMA
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help
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Enable detailed logging for QCOM GPI driver. Extra logging will be
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helpful when debugging critical issues. By using GPI dmaengine driver,
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bus drivers can use a standardize interface that is protocol independent
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to transfer data between DDR and peripheral.
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config QCOM_HIDMA_MGMT
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tristate "Qualcomm Technologies HIDMA Management support"
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depends on HAS_IOMEM
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@ -2,6 +2,7 @@
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obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
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obj-$(CONFIG_QCOM_BAM_DMA) += bam_dma.o
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obj-$(CONFIG_QCOM_GPI_DMA) += gpi.o
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obj-$(CONFIG_MSM_GPI_DMA) += msm_gpi.o
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obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o
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hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o
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obj-$(CONFIG_QCOM_HIDMA) += hdma.o
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3285
drivers/dma/qcom/msm_gpi.c
Normal file
3285
drivers/dma/qcom/msm_gpi.c
Normal file
File diff suppressed because it is too large
Load Diff
231
drivers/dma/qcom/msm_gpi_mmio.h
Normal file
231
drivers/dma/qcom/msm_gpi_mmio.h
Normal file
@ -0,0 +1,231 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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/* Register offsets from gpi-top */
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#define GPI_GPII_n_CH_k_CNTXT_0_OFFS(n, k) \
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(0x20000 + (0x4000 * (n)) + (0x80 * (k)))
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#define GPI_GPII_n_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK (0xFF000000)
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#define GPI_GPII_n_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT (24)
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#define GPI_GPII_n_CH_k_CNTXT_0_CHSTATE_BMSK (0xF00000)
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#define GPI_GPII_n_CH_k_CNTXT_0_CHSTATE_SHFT (20)
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#define GPI_GPII_n_CH_k_CNTXT_0_ERINDEX_BMSK (0x7C000)
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#define GPI_GPII_n_CH_k_CNTXT_0_ERINDEX_SHFT (14)
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#define GPI_GPII_n_CH_k_CNTXT_0_CHID_BMSK (0x1F00)
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#define GPI_GPII_n_CH_k_CNTXT_0_CHID_SHFT (8)
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#define GPI_GPII_n_CH_k_CNTXT_0_EE_BMSK (0xF0)
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#define GPI_GPII_n_CH_k_CNTXT_0_EE_SHFT (4)
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#define GPI_GPII_n_CH_k_CNTXT_0_CHTYPE_DIR_BMSK (0x8)
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#define GPI_GPII_n_CH_k_CNTXT_0_CHTYPE_DIR_SHFT (3)
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#define GPI_GPII_n_CH_k_CNTXT_0_CHTYPE_PROTO_BMSK (0x7)
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#define GPI_GPII_n_CH_k_CNTXT_0_CHTYPE_PROTO_SHFT (0)
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#define GPI_GPII_n_CH_k_CNTXT_0(el_size, erindex, chtype_dir, chtype_proto) \
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((el_size << 24) | (erindex << 14) | (chtype_dir << 3) | (chtype_proto))
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#define GPI_CHTYPE_DIR_IN (0)
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#define GPI_CHTYPE_DIR_OUT (1)
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#define GPI_CHTYPE_PROTO_GPI (0x2)
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#define GPI_GPII_n_CH_k_CNTXT_1_R_LENGTH_BMSK (0xFFFF)
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#define GPI_GPII_n_CH_k_CNTXT_1_R_LENGTH_SHFT (0)
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#define GPI_GPII_n_CH_k_DOORBELL_0_OFFS(n, k) (0x22000 + (0x4000 * (n)) \
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+ (0x8 * (k)))
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#define GPI_GPII_n_CH_CMD_OFFS(n) (0x23008 + (0x4000 * (n)))
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#define GPI_GPII_n_CH_CMD_OPCODE_BMSK (0xFF000000)
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#define GPI_GPII_n_CH_CMD_OPCODE_SHFT (24)
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#define GPI_GPII_n_CH_CMD_CHID_BMSK (0xFF)
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#define GPI_GPII_n_CH_CMD_CHID_SHFT (0)
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#define GPI_GPII_n_CH_CMD(opcode, chid) ((opcode << 24) | chid)
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#define GPI_GPII_n_CH_CMD_ALLOCATE (0)
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#define GPI_GPII_n_CH_CMD_START (1)
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#define GPI_GPII_n_CH_CMD_STOP (2)
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#define GPI_GPII_n_CH_CMD_RESET (9)
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#define GPI_GPII_n_CH_CMD_DE_ALLOC (10)
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#define GPI_GPII_n_CH_CMD_UART_SW_STALE (32)
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#define GPI_GPII_n_CH_CMD_UART_RFR_READY (33)
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#define GPI_GPII_n_CH_CMD_UART_RFR_NOT_READY (34)
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/* EV Context Array */
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_OFFS(n, k) \
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(0x21000 + (0x4000 * (n)) + (0x80 * (k)))
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK (0xFF000000)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT (24)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK (0xF00000)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT (20)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_INTYPE_BMSK (0x10000)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_INTYPE_SHFT (16)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_EVCHID_BMSK (0xFF00)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_EVCHID_SHFT (8)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_EE_BMSK (0xF0)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_EE_SHFT (4)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK (0xF)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT (0)
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#define GPI_GPII_n_EV_CH_k_CNTXT_0(el_size, intype, chtype) \
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((el_size << 24) | (intype << 16) | (chtype))
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#define GPI_INTTYPE_IRQ (1)
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#define GPI_CHTYPE_GPI_EV (0x2)
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#define GPI_GPII_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK (0xFFFF)
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#define GPI_GPII_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT (0)
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enum CNTXT_OFFS {
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CNTXT_0_CONFIG = 0x0,
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CNTXT_1_R_LENGTH = 0x4,
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CNTXT_2_RING_BASE_LSB = 0x8,
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CNTXT_3_RING_BASE_MSB = 0xC,
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CNTXT_4_RING_RP_LSB = 0x10,
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CNTXT_5_RING_RP_MSB = 0x14,
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CNTXT_6_RING_WP_LSB = 0x18,
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CNTXT_7_RING_WP_MSB = 0x1C,
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CNTXT_8_RING_INT_MOD = 0x20,
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CNTXT_9_RING_INTVEC = 0x24,
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CNTXT_10_RING_MSI_LSB = 0x28,
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CNTXT_11_RING_MSI_MSB = 0x2C,
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CNTXT_12_RING_RP_UPDATE_LSB = 0x30,
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CNTXT_13_RING_RP_UPDATE_MSB = 0x34,
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};
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#define GPI_GPII_n_EV_CH_k_DOORBELL_0_OFFS(n, k) \
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(0x22100 + (0x4000 * (n)) + (0x8 * (k)))
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#define GPI_GPII_n_EV_CH_CMD_OFFS(n) \
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(0x23010 + (0x4000 * (n)))
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#define GPI_GPII_n_EV_CH_CMD_OPCODE_BMSK (0xFF000000)
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#define GPI_GPII_n_EV_CH_CMD_OPCODE_SHFT (24)
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#define GPI_GPII_n_EV_CH_CMD_CHID_BMSK (0xFF)
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#define GPI_GPII_n_EV_CH_CMD_CHID_SHFT (0)
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#define GPI_GPII_n_EV_CH_CMD(opcode, chid) \
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((opcode << 24) | chid)
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#define GPI_GPII_n_EV_CH_CMD_ALLOCATE (0x00)
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#define GPI_GPII_n_EV_CH_CMD_RESET (0x09)
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#define GPI_GPII_n_EV_CH_CMD_DE_ALLOC (0x0A)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_OFFS(n) \
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(0x23080 + (0x4000 * (n)))
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/* mask type register */
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) \
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(0x23088 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_BMSK (0x7F)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_SHFT (0)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_GENERAL (0x40)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_INTER_GPII_EV_CTRL (0x20)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_INTER_GPII_CH_CTRL (0x10)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_IEOB (0x08)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_GLOB (0x04)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL (0x02)
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#define GPI_GPII_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL (0x01)
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#define GPI_GPII_n_CNTXT_SRC_GPII_CH_IRQ_OFFS(n) \
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(0x23090 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n) \
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(0x23094 + (0x4000 * (n)))
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/* Mask channel control interrupt register */
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#define GPI_GPII_n_CNTXT_SRC_CH_IRQ_MSK_OFFS(n) \
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(0x23098 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_SRC_CH_IRQ_MSK_BMSK (0x3)
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#define GPI_GPII_n_CNTXT_SRC_CH_IRQ_MSK_SHFT (0)
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/* Mask event control interrupt register */
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#define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n) \
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(0x2309C + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_BMSK (0x1)
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#define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_SHFT (0)
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#define GPI_GPII_n_CNTXT_SRC_CH_IRQ_CLR_OFFS(n) \
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(0x230A0 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n) \
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(0x230A4 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_OFFS(n) \
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(0x230B0 + (0x4000 * (n)))
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/* Mask event interrupt register */
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#define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n) \
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(0x230B8 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_BMSK (0x1)
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#define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_SHFT (0)
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#define GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n) \
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(0x230C0 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) \
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(0x23100 + (0x4000 * (n)))
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#define GPI_GLOB_IRQ_ERROR_INT_MSK (0x1)
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#define GPI_GLOB_IRQ_GP_INT1_MSK (0x2)
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#define GPI_GLOB_IRQ_GP_INT2_MSK (0x4)
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#define GPI_GLOB_IRQ_GP_INT3_MSK (0x8)
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/* GPII specific Global - Enable bit register */
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_OFFS(n) \
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(0x23108 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_BMSK (0xF)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_SHFT (0)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_GP_INT3 (0x8)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_GP_INT2 (0x4)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_GP_INT1 (0x2)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_ERROR_INT (0x1)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) \
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(0x23110 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_GPII_IRQ_STTS_OFFS(n) \
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(0x23118 + (0x4000 * (n)))
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/* GPII general interrupt - Enable bit register */
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#define GPI_GPII_n_CNTXT_GPII_IRQ_EN_OFFS(n) \
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(0x23120 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_GPII_IRQ_EN_BMSK (0xF)
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#define GPI_GPII_n_CNTXT_GPII_IRQ_EN_SHFT (0)
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#define GPI_GPII_n_CNTXT_GPII_IRQ_EN_STACK_OVRFLOW (0x8)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_CMD_FIFO_OVRFLOW (0x4)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_BUS_ERROR (0x2)
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#define GPI_GPII_n_CNTXT_GLOB_IRQ_EN_BREAK_POINT (0x1)
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#define GPI_GPII_n_CNTXT_GPII_IRQ_CLR_OFFS(n) \
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(0x23128 + (0x4000 * (n)))
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/* GPII Interrupt Type register */
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#define GPI_GPII_n_CNTXT_INTSET_OFFS(n) \
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(0x23180 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_INTSET_BMSK (0x1)
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#define GPI_GPII_n_CNTXT_INTSET_SHFT (0)
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#define GPI_GPII_n_CNTXT_MSI_BASE_LSB_OFFS(n) \
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(0x23188 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_MSI_BASE_MSB_OFFS(n) \
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(0x2318C + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_SCRATCH_0_OFFS(n) \
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(0x23400 + (0x4000 * (n)))
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#define GPI_GPII_n_CNTXT_SCRATCH_1_OFFS(n) \
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(0x23404 + (0x4000 * (n)))
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#define GPI_GPII_n_ERROR_LOG_OFFS(n) \
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(0x23200 + (0x4000 * (n)))
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#define GPI_GPII_n_ERROR_LOG_CLR_OFFS(n) \
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(0x23210 + (0x4000 * (n)))
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/* QOS Registers */
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#define GPI_GPII_n_CH_k_QOS_OFFS(n, k) \
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(0x2005C + (0x4000 * (n)) + (0x80 * (k)))
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/* Scratch registeres */
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#define GPI_GPII_n_CH_k_SCRATCH_0_OFFS(n, k) \
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(0x20060 + (0x4000 * (n)) + (0x80 * (k)))
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#define GPI_GPII_n_CH_K_SCRATCH_0(pair, proto, seid) \
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((pair << 16) | (proto << 4) | seid)
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#define GPI_GPII_n_CH_k_SCRATCH_1_OFFS(n, k) \
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(0x20064 + (0x4000 * (n)) + (0x80 * (k)))
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#define GPI_GPII_n_CH_k_SCRATCH_2_OFFS(n, k) \
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(0x20068 + (0x4000 * (n)) + (0x80 * (k)))
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#define GPI_GPII_n_CH_k_SCRATCH_3_OFFS(n, k) \
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(0x2006C + (0x4000 * (n)) + (0x80 * (k)))
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/* Debug registers */
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#define GPI_DEBUG_PC_FOR_DEBUG (0x5048)
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#define GPI_DEBUG_SW_RF_n_READ(n) (0x5100 + (0x4 * n))
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/* GPI_DEBUG_QSB registers */
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#define GPI_DEBUG_QSB_LOG_SEL (0x5050)
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#define GPI_DEBUG_QSB_LOG_CLR (0x5058)
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#define GPI_DEBUG_QSB_LOG_ERR_TRNS_ID (0x5060)
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#define GPI_DEBUG_QSB_LOG_0 (0x5064)
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#define GPI_DEBUG_QSB_LOG_1 (0x5068)
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#define GPI_DEBUG_QSB_LOG_2 (0x506C)
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#define GPI_DEBUG_QSB_LOG_LAST_MISC_ID(n) (0x5070 + (0x4*n))
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271
include/linux/msm_gpi.h
Normal file
271
include/linux/msm_gpi.h
Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef __MSM_GPI_H_
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#define __MSM_GPI_H_
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#include <linux/types.h>
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struct __packed msm_gpi_tre {
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u32 dword[4];
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};
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enum msm_gpi_tre_type {
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MSM_GPI_TRE_INVALID = 0x00,
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MSM_GPI_TRE_NOP = 0x01,
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MSM_GPI_TRE_DMA_W_BUF = 0x10,
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MSM_GPI_TRE_DMA_IMMEDIATE = 0x11,
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MSM_GPI_TRE_DMA_W_SG_LIST = 0x12,
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MSM_GPI_TRE_GO = 0x20,
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MSM_GPI_TRE_CONFIG0 = 0x22,
|
||||
MSM_GPI_TRE_CONFIG1 = 0x23,
|
||||
MSM_GPI_TRE_CONFIG2 = 0x24,
|
||||
MSM_GPI_TRE_CONFIG3 = 0x25,
|
||||
MSM_GPI_TRE_LOCK = 0x30,
|
||||
MSM_GPI_TRE_UNLOCK = 0x31,
|
||||
};
|
||||
|
||||
#define MSM_GPI_TRE_TYPE(tre) ((tre->dword[3] >> 16) & 0xFF)
|
||||
|
||||
/* Lock TRE */
|
||||
#define MSM_GPI_LOCK_TRE_DWORD0 (0)
|
||||
#define MSM_GPI_LOCK_TRE_DWORD1 (0)
|
||||
#define MSM_GPI_LOCK_TRE_DWORD2 (0)
|
||||
#define MSM_GPI_LOCK_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
|
||||
((0x3 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
|
||||
(ieot << 9) | (ieob << 8) | ch)
|
||||
|
||||
/* Unlock TRE */
|
||||
#define MSM_GPI_UNLOCK_TRE_DWORD0 (0)
|
||||
#define MSM_GPI_UNLOCK_TRE_DWORD1 (0)
|
||||
#define MSM_GPI_UNLOCK_TRE_DWORD2 (0)
|
||||
#define MSM_GPI_UNLOCK_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
|
||||
((0x3 << 20) | (0x1 << 16) | (link_rx << 11) | (bei << 10) | \
|
||||
(ieot << 9) | (ieob << 8) | ch)
|
||||
|
||||
/* DMA w. Buffer TRE */
|
||||
#ifdef CONFIG_ARM64
|
||||
#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) ((u32)ptr)
|
||||
#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) ((u32)(ptr >> 32))
|
||||
#else
|
||||
#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) (ptr)
|
||||
#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) 0
|
||||
#endif
|
||||
|
||||
#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length) (length & 0xFFFFFF)
|
||||
#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
|
||||
((0x1 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
|
||||
(ieot << 9) | (ieob << 8) | ch)
|
||||
#define MSM_GPI_DMA_W_BUFFER_TRE_GET_LEN(tre) (tre->dword[2] & 0xFFFFFF)
|
||||
#define MSM_GPI_DMA_W_BUFFER_TRE_SET_LEN(tre, length) (tre->dword[2] = \
|
||||
MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length))
|
||||
|
||||
/* DMA Immediate TRE */
|
||||
#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD0(d3, d2, d1, d0) ((d3 << 24) | \
|
||||
(d2 << 16) | (d1 << 8) | (d0))
|
||||
#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD1(d4, d5, d6, d7) ((d7 << 24) | \
|
||||
(d6 << 16) | (d5 << 8) | (d4))
|
||||
#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD2(length) (length & 0xF)
|
||||
#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
|
||||
((0x1 << 20) | (0x1 << 16) | (link_rx << 11) | (bei << 10) | \
|
||||
(ieot << 9) | (ieob << 8) | ch)
|
||||
#define MSM_GPI_DMA_IMMEDIATE_TRE_GET_LEN(tre) (tre->dword[2] & 0xF)
|
||||
|
||||
/* DMA w. Scatter/Gather List TRE */
|
||||
#ifdef CONFIG_ARM64
|
||||
#define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) ((u32)ptr)
|
||||
#define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) ((u32)(ptr >> 32))
|
||||
#else
|
||||
#define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) (ptr)
|
||||
#define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) 0
|
||||
#endif
|
||||
#define MSM_GPI_SG_LIST_TRE_DWORD2(length) (length & 0xFFFF)
|
||||
#define MSM_GPI_SG_LIST_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x1 << 20) \
|
||||
| (0x2 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
|
||||
(ieob << 8) | ch)
|
||||
|
||||
/* SG Element */
|
||||
#ifdef CONFIG_ARM64
|
||||
#define MSM_GPI_SG_ELEMENT_DWORD0(ptr) ((u32)ptr)
|
||||
#define MSM_GPI_SG_ELEMENT_DWORD1(ptr) ((u32)(ptr >> 32))
|
||||
#else
|
||||
#define MSM_GPI_SG_ELEMENT_DWORD0(ptr) (ptr)
|
||||
#define MSM_GPI_SG_ELEMENT_DWORD1(ptr) 0
|
||||
#endif
|
||||
#define MSM_GSI_SG_ELEMENT_DWORD2(length) (length & 0xFFFFF)
|
||||
#define MSM_GSI_SG_ELEMENT_DWORD3 (0)
|
||||
|
||||
/* Config2 TRE */
|
||||
#define GPI_CONFIG2_TRE_DWORD0(gr, txp) ((gr << 20) | (txp))
|
||||
#define GPI_CONFIG2_TRE_DWORD1(txp) (txp)
|
||||
#define GPI_CONFIG2_TRE_DWORD2 (0)
|
||||
#define GPI_CONFIG2_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
|
||||
(0x4 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
|
||||
(ieob << 8) | ch)
|
||||
|
||||
/* Config3 TRE */
|
||||
#define GPI_CONFIG3_TRE_DWORD0(rxp) (rxp)
|
||||
#define GPI_CONFIG3_TRE_DWORD1(rxp) (rxp)
|
||||
#define GPI_CONFIG3_TRE_DWORD2 (0)
|
||||
#define GPI_CONFIG3_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) \
|
||||
| (0x5 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
|
||||
(ieob << 8) | ch)
|
||||
|
||||
/* SPI Go TRE */
|
||||
#define MSM_GPI_SPI_GO_TRE_DWORD0(flags, cs, command) ((flags << 24) | \
|
||||
(cs << 8) | command)
|
||||
#define MSM_GPI_SPI_GO_TRE_DWORD1 (0)
|
||||
#define MSM_GPI_SPI_GO_TRE_DWORD2(rx_len) (rx_len)
|
||||
#define MSM_GPI_SPI_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
|
||||
(0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
|
||||
(ieob << 8) | ch)
|
||||
|
||||
/* SPI Config0 TRE */
|
||||
#define MSM_GPI_SPI_CONFIG0_TRE_DWORD0(pack, flags, word_size) ((pack << 24) | \
|
||||
(flags << 8) | word_size)
|
||||
#define MSM_GPI_SPI_CONFIG0_TRE_DWORD1(it_del, cs_clk_del, iw_del) \
|
||||
((it_del << 16) | (cs_clk_del << 8) | iw_del)
|
||||
#define MSM_GPI_SPI_CONFIG0_TRE_DWORD2(clk_src, clk_div) ((clk_src << 16) | \
|
||||
clk_div)
|
||||
#define MSM_GPI_SPI_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
|
||||
((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
|
||||
(ieot << 9) | (ieob << 8) | ch)
|
||||
|
||||
/* UART Go TRE */
|
||||
#define MSM_GPI_UART_GO_TRE_DWORD0(en_hunt, command) ((en_hunt << 8) | command)
|
||||
#define MSM_GPI_UART_GO_TRE_DWORD1 (0)
|
||||
#define MSM_GPI_UART_GO_TRE_DWORD2 (0)
|
||||
#define MSM_GPI_UART_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) \
|
||||
| (0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
|
||||
(ieob << 8) | ch)
|
||||
|
||||
/* UART Config0 TRE */
|
||||
#define MSM_GPI_UART_CONFIG0_TRE_DWORD0(pack, hunt, flags, parity, sbl, size) \
|
||||
((pack << 24) | (hunt << 16) | (flags << 8) | (parity << 5) | \
|
||||
(sbl << 3) | size)
|
||||
#define MSM_GPI_UART_CONFIG0_TRE_DWORD1(rfr_level, rx_stale) \
|
||||
((rfr_level << 24) | rx_stale)
|
||||
#define MSM_GPI_UART_CONFIG0_TRE_DWORD2(clk_source, clk_div) \
|
||||
((clk_source << 16) | clk_div)
|
||||
#define MSM_GPI_UART_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
|
||||
((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
|
||||
(ieot << 9) | (ieob << 8) | ch)
|
||||
|
||||
/* I2C GO TRE */
|
||||
#define MSM_GPI_I2C_GO_TRE_DWORD0(flags, slave, opcode) \
|
||||
((flags << 24) | (slave << 8) | opcode)
|
||||
#define MSM_GPI_I2C_GO_TRE_DWORD1 (0)
|
||||
#define MSM_GPI_I2C_GO_TRE_DWORD2(rx_len) (rx_len)
|
||||
#define MSM_GPI_I2C_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
|
||||
(0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
|
||||
(ieob << 8) | ch)
|
||||
|
||||
/* I2C Config0 TRE */
|
||||
#define MSM_GPI_I2C_CONFIG0_TRE_DWORD0(pack, t_cycle, t_high, t_low) \
|
||||
((pack << 24) | (t_cycle << 16) | (t_high << 8) | t_low)
|
||||
#define MSM_GPI_I2C_CONFIG0_TRE_DWORD1(inter_delay, noise_rej) \
|
||||
((inter_delay << 16) | noise_rej)
|
||||
#define MSM_GPI_I2C_CONFIG0_TRE_DWORD2(clk_src, clk_div) \
|
||||
((clk_src << 16) | clk_div)
|
||||
#define MSM_GPI_I2C_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
|
||||
((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
|
||||
(ieot << 9) | (ieob << 8) | ch)
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
#define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) ((u32)(ptr >> 32))
|
||||
#else
|
||||
#define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) 0
|
||||
#endif
|
||||
|
||||
/* Static GPII here uses bit5 bit4 bit3 bit2 bit1(xxx1 111x) */
|
||||
#define STATIC_GPII_BMSK (0x1e)
|
||||
#define STATIC_GPII_SHFT (0x1)
|
||||
#define GPI_EV_PRIORITY_BMSK (0x1)
|
||||
|
||||
/* cmds to perform by using dmaengine_slave_config() */
|
||||
enum msm_gpi_ctrl_cmd {
|
||||
MSM_GPI_INIT,
|
||||
MSM_GPI_CMD_UART_SW_STALE,
|
||||
MSM_GPI_CMD_UART_RFR_READY,
|
||||
MSM_GPI_CMD_UART_RFR_NOT_READY,
|
||||
};
|
||||
|
||||
enum msm_gpi_cb_event {
|
||||
/* These events are hardware generated events */
|
||||
MSM_GPI_QUP_NOTIFY,
|
||||
MSM_GPI_QUP_ERROR, /* global error */
|
||||
MSM_GPI_QUP_CH_ERROR, /* channel specific error */
|
||||
MSM_GPI_QUP_FW_ERROR, /* unhandled error */
|
||||
/* These events indicate a software bug */
|
||||
MSM_GPI_QUP_PENDING_EVENT,
|
||||
MSM_GPI_QUP_EOT_DESC_MISMATCH,
|
||||
MSM_GPI_QUP_SW_ERROR,
|
||||
MSM_GPI_QUP_MAX_EVENT,
|
||||
};
|
||||
|
||||
struct msm_gpi_error_log {
|
||||
u32 routine;
|
||||
u32 type;
|
||||
u32 error_code;
|
||||
};
|
||||
|
||||
struct msm_gpi_cb {
|
||||
enum msm_gpi_cb_event cb_event;
|
||||
u64 status;
|
||||
u64 timestamp;
|
||||
u64 count;
|
||||
struct msm_gpi_error_log error_log;
|
||||
};
|
||||
|
||||
struct dma_chan;
|
||||
|
||||
struct gpi_client_info {
|
||||
/*
|
||||
* memory for msm_gpi_cb is released after callback, clients shall
|
||||
* save any required data for post processing after returning
|
||||
* from callback
|
||||
*/
|
||||
void (*callback)(struct dma_chan *chan,
|
||||
struct msm_gpi_cb const *msm_gpi_cb,
|
||||
void *cb_param);
|
||||
void *cb_param;
|
||||
};
|
||||
|
||||
/*
|
||||
* control structure to config gpi dma engine via dmaengine_slave_config()
|
||||
* dma_chan.private should point to msm_gpi_ctrl structure
|
||||
*/
|
||||
struct msm_gpi_ctrl {
|
||||
enum msm_gpi_ctrl_cmd cmd;
|
||||
union {
|
||||
struct gpi_client_info init;
|
||||
};
|
||||
};
|
||||
|
||||
enum msm_gpi_tce_code {
|
||||
MSM_GPI_TCE_SUCCESS = 1,
|
||||
MSM_GPI_TCE_EOT = 2,
|
||||
MSM_GPI_TCE_EOB = 4,
|
||||
MSM_GPI_TCE_UNEXP_ERR = 16,
|
||||
};
|
||||
|
||||
/*
|
||||
* gpi specific callback parameters to pass between gpi client and gpi engine.
|
||||
* client shall set async_desc.callback_parm to msm_gpi_dma_async_tx_cb_param
|
||||
*/
|
||||
struct msm_gpi_dma_async_tx_cb_param {
|
||||
u32 length;
|
||||
enum msm_gpi_tce_code completion_code; /* TCE event code */
|
||||
u32 status;
|
||||
struct __packed msm_gpi_tre imed_tre;
|
||||
void *userdata;
|
||||
};
|
||||
|
||||
/* Client drivers of the GPI can call this function to dump the GPI registers
|
||||
* whenever client met some scenario like timeout, error in GPI transfer mode.
|
||||
*/
|
||||
void gpi_dump_for_geni(struct dma_chan *chan);
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user