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Merge changes I95ce33fb,I03723a9f,I4b1cf7f1,I6e17c9b3,I446172f8, ... into android14-6.1

Browse Source 
* changes:
  Merge 6.1.17 into android14-6.1
  ANDROID: update abi definition due to io_uring changes.
  UPSTREAM: Revert "blk-cgroup: dropping parent refcount after pd_free_fn() is done"
  UPSTREAM: Revert "blk-cgroup: synchronize pd_free_fn() from blkg_free_workfn() and blkcg_deactivate_policy()"
  Revert "kobject: modify kobject_get_path() to take a const *"
  Revert "wait: Return number of exclusive waiters awaken"
  Revert "sbitmap: Use single per-bitmap counting to wake up queued tags"
  Revert "sbitmap: correct wake_batch recalculation to avoid potential IO hung"
  Revert "sbitmap: Advance the queue index before waking up a queue"
  Revert "sbitmap: Try each queue to wake up at least one waiter"
  Revert "HID: retain initial quirks set up when creating HID devices"
  Merge 6.1.16 into android14-6.1
This commit is contained in:
Greg Kroah-Hartman 2023-03-14 17:38:04 +00:00
commit 5b483d8a04
835 changed files with 8060 additions and 4645 deletions
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13
Documentation/admin-guide/cgroup-v1/memory.rst
View File

@ -86,6 +86,8 @@ Brief summary of control files.
memory.swappiness set/show swappiness parameter of vmscan
(See sysctl's vm.swappiness)
memory.move_charge_at_immigrate set/show controls of moving charges
This knob is deprecated and shouldn't be
used.
memory.oom_control set/show oom controls.
memory.numa_stat show the number of memory usage per numa
node
@ -716,8 +718,15 @@ NOTE2:
It is recommended to set the soft limit always below the hard limit,
otherwise the hard limit will take precedence.
8. Move charges at task migration
=================================
8. Move charges at task migration (DEPRECATED!)
===============================================
THIS IS DEPRECATED!
It's expensive and unreliable! It's better practice to launch workload
tasks directly from inside their target cgroup. Use dedicated workload
cgroups to allow fine-grained policy adjustments without having to
move physical pages between control domains.
Users can move charges associated with a task along with task migration, that
is, uncharge task's pages from the old cgroup and charge them to the new cgroup.

21
Documentation/admin-guide/hw-vuln/spectre.rst
View File

@ -479,8 +479,16 @@ Spectre variant 2
On Intel Skylake-era systems the mitigation covers most, but not all,
cases. See :ref:`[3] <spec_ref3>` for more details.
On CPUs with hardware mitigation for Spectre variant 2 (e.g. Enhanced
IBRS on x86), retpoline is automatically disabled at run time.
On CPUs with hardware mitigation for Spectre variant 2 (e.g. IBRS
or enhanced IBRS on x86), retpoline is automatically disabled at run time.
Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at
boot, by setting the IBRS bit, and they're automatically protected against
Spectre v2 variant attacks, including cross-thread branch target injections
on SMT systems (STIBP). In other words, eIBRS enables STIBP too.
Legacy IBRS systems clear the IBRS bit on exit to userspace and
therefore explicitly enable STIBP for that
The retpoline mitigation is turned on by default on vulnerable
CPUs. It can be forced on or off by the administrator
@ -504,9 +512,12 @@ Spectre variant 2
For Spectre variant 2 mitigation, individual user programs
can be compiled with return trampolines for indirect branches.
This protects them from consuming poisoned entries in the branch
target buffer left by malicious software. Alternatively, the
programs can disable their indirect branch speculation via prctl()
(See :ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
target buffer left by malicious software.
On legacy IBRS systems, at return to userspace, implicit STIBP is disabled
because the kernel clears the IBRS bit. In this case, the userspace programs
can disable indirect branch speculation via prctl() (See
:ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
On x86, this will turn on STIBP to guard against attacks from the
sibling thread when the user program is running, and use IBPB to
flush the branch target buffer when switching to/from the program.

2
Documentation/admin-guide/kdump/gdbmacros.txt
View File

@ -312,10 +312,10 @@ define dmesg
set var $prev_flags = $info->flags
end
set var $id = ($id + 1) & $id_mask
if ($id == $end_id)
loop_break
end
set var $id = ($id + 1) & $id_mask
end
end
document dmesg

16
Documentation/bpf/instruction-set.rst
View File

@ -99,19 +99,26 @@ code value description
BPF_ADD 0x00 dst += src
BPF_SUB 0x10 dst -= src
BPF_MUL 0x20 dst \*= src
BPF_DIV 0x30 dst /= src
BPF_DIV 0x30 dst = (src != 0) ? (dst / src) : 0
BPF_OR 0x40 dst \|= src
BPF_AND 0x50 dst &= src
BPF_LSH 0x60 dst <<= src
BPF_RSH 0x70 dst >>= src
BPF_NEG 0x80 dst = ~src
BPF_MOD 0x90 dst %= src
BPF_MOD 0x90 dst = (src != 0) ? (dst % src) : dst
BPF_XOR 0xa0 dst ^= src
BPF_MOV 0xb0 dst = src
BPF_ARSH 0xc0 sign extending shift right
BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below)
======== ===== ==========================================================
Underflow and overflow are allowed during arithmetic operations, meaning
the 64-bit or 32-bit value will wrap. If eBPF program execution would
result in division by zero, the destination register is instead set to zero.
If execution would result in modulo by zero, for ``BPF_ALU64`` the value of
the destination register is unchanged whereas for ``BPF_ALU`` the upper
32 bits of the destination register are zeroed.
``BPF_ADD | BPF_X | BPF_ALU`` means::
dst_reg = (u32) dst_reg + (u32) src_reg;
@ -128,6 +135,11 @@ BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below)
src_reg = src_reg ^ imm32
Also note that the division and modulo operations are unsigned. Thus, for
``BPF_ALU``, 'imm' is first interpreted as an unsigned 32-bit value, whereas
for ``BPF_ALU64``, 'imm' is first sign extended to 64 bits and the result
interpreted as an unsigned 64-bit value. There are no instructions for
signed division or modulo.
Byte swap instructions
~~~~~~~~~~~~~~~~~~~~~~

4
Documentation/dev-tools/gdb-kernel-debugging.rst
View File

@ -39,6 +39,10 @@ Setup
this mode. In this case, you should build the kernel with
CONFIG_RANDOMIZE_BASE disabled if the architecture supports KASLR.
- Build the gdb scripts (required on kernels v5.1 and above)::
make scripts_gdb
- Enable the gdb stub of QEMU/KVM, either
- at VM startup time by appending "-s" to the QEMU command line

2
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
View File

@ -32,7 +32,7 @@ properties:
- items:
- enum:
- mediatek,mt8186-disp-ccorr
- const: mediatek,mt8183-disp-ccorr
- const: mediatek,mt8192-disp-ccorr
reg:
maxItems: 1

2
Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml
View File

@ -62,7 +62,7 @@ patternProperties:
description: phandle of the CPU DAI
patternProperties:
"^codec-[0-9]+$":
"^codec(-[0-9]+)?$":
type: object
additionalProperties: false
description: |-

4
Documentation/hwmon/ftsteutates.rst
View File

@ -22,6 +22,10 @@ enhancements. It can monitor up to 4 voltages, 16 temperatures and
8 fans. It also contains an integrated watchdog which is currently
implemented in this driver.
The 4 voltages require a board-specific multiplier, since the BMC can
only measure voltages up to 3.3V and thus relies on voltage dividers.
Consult your motherboard manual for details.
To clear a temperature or fan alarm, execute the following command with the
correct path to the alarm file::

18
Documentation/virt/kvm/api.rst
View File

@ -4483,6 +4483,18 @@ not holding a previously reported uncorrected error).
:Parameters: struct kvm_s390_cmma_log (in, out)
:Returns: 0 on success, a negative value on error
Errors:
====== =============================================================
ENOMEM not enough memory can be allocated to complete the task
ENXIO if CMMA is not enabled
EINVAL if KVM_S390_CMMA_PEEK is not set but migration mode was not enabled
EINVAL if KVM_S390_CMMA_PEEK is not set but dirty tracking has been
disabled (and thus migration mode was automatically disabled)
EFAULT if the userspace address is invalid or if no page table is
present for the addresses (e.g. when using hugepages).
====== =============================================================
This ioctl is used to get the values of the CMMA bits on the s390
architecture. It is meant to be used in two scenarios:
@ -4563,12 +4575,6 @@ mask is unused.
values points to the userspace buffer where the result will be stored.
This ioctl can fail with -ENOMEM if not enough memory can be allocated to
complete the task, with -ENXIO if CMMA is not enabled, with -EINVAL if
KVM_S390_CMMA_PEEK is not set but migration mode was not enabled, with
-EFAULT if the userspace address is invalid or if no page table is
present for the addresses (e.g. when using hugepages).
4.108 KVM_S390_SET_CMMA_BITS
----------------------------

4
Documentation/virt/kvm/devices/vm.rst
View File

@ -302,6 +302,10 @@ Allows userspace to start migration mode, needed for PGSTE migration.
Setting this attribute when migration mode is already active will have
no effects.
Dirty tracking must be enabled on all memslots, else -EINVAL is returned. When
dirty tracking is disabled on any memslot, migration mode is automatically
stopped.
:Parameters: none
:Returns: -ENOMEM if there is not enough free memory to start migration mode;
-EINVAL if the state of the VM is invalid (e.g. no memory defined);

15
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 1
SUBLEVEL = 15
SUBLEVEL = 17
EXTRAVERSION =
NAME = Hurr durr I'ma ninja sloth
@ -93,10 +93,17 @@ endif
# If the user is running make -s (silent mode), suppress echoing of
# commands
# make-4.0 (and later) keep single letter options in the 1st word of MAKEFLAGS.
ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),)
quiet=silent_
KBUILD_VERBOSE = 0
ifeq ($(filter 3.%,$(MAKE_VERSION)),)
silence:=$(findstring s,$(firstword -$(MAKEFLAGS)))
else
silence:=$(findstring s,$(filter-out --%,$(MAKEFLAGS)))
endif
ifeq ($(silence),s)
quiet=silent_
KBUILD_VERBOSE = 0
endif
export quiet Q KBUILD_VERBOSE

29
android/abi_gki_aarch64.stg
View File

@ -36597,6 +36597,10 @@ member {
id: 0x25ab4212
type_id: 0x1983785b
}
member {
id: 0x2612b435
type_id: 0x1764a0c5
}
member {
id: 0x2629d9f4
type_id: 0x178917c0
@ -37383,8 +37387,8 @@ member {
offset: 96
}
member {
id: 0x34b145e5
type_id: 0x5deb6786
id: 0x34be27ed
type_id: 0x5dd6efa4
}
member {
id: 0x34c421be
@ -38795,6 +38799,11 @@ member {
name: "__empty_array"
type_id: 0x186c44db
}
member {
id: 0x3cf3a247
name: "__empty_bufs"
type_id: 0x186c44db
}
member {
id: 0x2cf33eb6
name: "__empty_data"
@ -200464,6 +200473,14 @@ struct_union {
member_id: 0x2df9c4da
}
}
struct_union {
id: 0x1764a0c5
kind: STRUCT
definition {
member_id: 0x3cf3a247
member_id: 0xd0323df9
}
}
struct_union {
id: 0x178917c0
kind: STRUCT
@ -204150,12 +204167,12 @@ struct_union {
}
}
struct_union {
id: 0x5deb6786
id: 0x5dd6efa4
kind: UNION
definition {
bytesize: 16
member_id: 0x2c96db22
member_id: 0xd0323df9
member_id: 0x2612b435
}
}
struct_union {
@ -226261,7 +226278,7 @@ struct_union {
name: "io_uring_buf_ring"
definition {
bytesize: 16
member_id: 0x34b145e5
member_id: 0x34be27ed
}
}
struct_union {
@ -334086,7 +334103,7 @@ elf_symbol {
name: "hid_ignore"
is_defined: true
symbol_type: FUNCTION
crc: 0x6472f954
crc: 0x60a463f6
type_id: 0xfddd6aa8
full_name: "hid_ignore"
}

2
arch/alpha/boot/tools/objstrip.c
View File

@ -148,7 +148,7 @@ main (int argc, char *argv[])
#ifdef __ELF__
elf = (struct elfhdr *) buf;
if (elf->e_ident[0] == 0x7f && str_has_prefix((char *)elf->e_ident + 1, "ELF")) {
if (memcmp(&elf->e_ident[EI_MAG0], ELFMAG, SELFMAG) == 0) {
if (elf->e_type != ET_EXEC) {
fprintf(stderr, "%s: %s is not an ELF executable\n",
prog_name, inname);

30
arch/alpha/kernel/traps.c
View File

@ -233,7 +233,21 @@ do_entIF(unsigned long type, struct pt_regs *regs)
{
int signo, code;
if ((regs->ps & ~IPL_MAX) == 0) {
if (type == 3) { /* FEN fault */
/* Irritating users can call PAL_clrfen to disable the
FPU for the process. The kernel will then trap in
do_switch_stack and undo_switch_stack when we try
to save and restore the FP registers.
Given that GCC by default generates code that uses the
FP registers, PAL_clrfen is not useful except for DoS
attacks. So turn the bleeding FPU back on and be done
with it. */
current_thread_info()->pcb.flags |= 1;
__reload_thread(&current_thread_info()->pcb);
return;
}
if (!user_mode(regs)) {
if (type == 1) {
const unsigned int *data
= (const unsigned int *) regs->pc;
@ -366,20 +380,6 @@ do_entIF(unsigned long type, struct pt_regs *regs)
}
break;
case 3: /* FEN fault */
/* Irritating users can call PAL_clrfen to disable the
FPU for the process. The kernel will then trap in
do_switch_stack and undo_switch_stack when we try
to save and restore the FP registers.
Given that GCC by default generates code that uses the
FP registers, PAL_clrfen is not useful except for DoS
attacks. So turn the bleeding FPU back on and be done
with it. */
current_thread_info()->pcb.flags |= 1;
__reload_thread(&current_thread_info()->pcb);
return;
case 5: /* illoc */
default: /* unexpected instruction-fault type */
;

2
arch/arm/boot/dts/exynos3250-rinato.dts
View File

@ -250,7 +250,7 @@ &fimd {
i80-if-timings {
cs-setup = <0>;
wr-setup = <0>;
wr-act = <1>;
wr-active = <1>;
wr-hold = <0>;
};
};

2
arch/arm/boot/dts/exynos4-cpu-thermal.dtsi
View File

@ -10,7 +10,7 @@
/ {
thermal-zones {
cpu_thermal: cpu-thermal {
thermal-sensors = <&tmu 0>;
thermal-sensors = <&tmu>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {

2
arch/arm/boot/dts/exynos4.dtsi
View File

@ -605,7 +605,7 @@ i2c_8: i2c@138e0000 {
status = "disabled";
hdmi_i2c_phy: hdmiphy@38 {
compatible = "exynos4210-hdmiphy";
compatible = "samsung,exynos4210-hdmiphy";
reg = <0x38>;
};
};

1
arch/arm/boot/dts/exynos4210.dtsi
View File

@ -393,7 +393,6 @@ &cpu_alert2 {
&cpu_thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tmu 0>;
};
&gic {

2
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -1107,7 +1107,7 @@ timer {
&cpu_thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tmu 0>;
thermal-sensors = <&tmu>;
cooling-maps {
map0 {

1
arch/arm/boot/dts/exynos5410-odroidxu.dts
View File

@ -120,7 +120,6 @@ &clock_audss {
};
&cpu0_thermal {
thermal-sensors = <&tmu_cpu0 0>;
polling-delay-passive = <0>;
polling-delay = <0>;

2
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -592,7 +592,7 @@ dp_phy: dp-video-phy {
};
mipi_phy: mipi-video-phy {
compatible = "samsung,s5pv210-mipi-video-phy";
compatible = "samsung,exynos5420-mipi-video-phy";
syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};

10
arch/arm/boot/dts/exynos5422-odroidhc1.dts
View File

@ -31,7 +31,7 @@ led-1 {
thermal-zones {
cpu0_thermal: cpu0-thermal {
thermal-sensors = <&tmu_cpu0 0>;
thermal-sensors = <&tmu_cpu0>;
trips {
cpu0_alert0: cpu-alert-0 {
temperature = <70000>; /* millicelsius */
@ -86,7 +86,7 @@ map1 {
};
};
cpu1_thermal: cpu1-thermal {
thermal-sensors = <&tmu_cpu1 0>;
thermal-sensors = <&tmu_cpu1>;
trips {
cpu1_alert0: cpu-alert-0 {
temperature = <70000>;
@ -130,7 +130,7 @@ map1 {
};
};
cpu2_thermal: cpu2-thermal {
thermal-sensors = <&tmu_cpu2 0>;
thermal-sensors = <&tmu_cpu2>;
trips {
cpu2_alert0: cpu-alert-0 {
temperature = <70000>;
@ -174,7 +174,7 @@ map1 {
};
};
cpu3_thermal: cpu3-thermal {
thermal-sensors = <&tmu_cpu3 0>;
thermal-sensors = <&tmu_cpu3>;
trips {
cpu3_alert0: cpu-alert-0 {
temperature = <70000>;
@ -218,7 +218,7 @@ map1 {
};
};
gpu_thermal: gpu-thermal {
thermal-sensors = <&tmu_gpu 0>;
thermal-sensors = <&tmu_gpu>;
trips {
gpu_alert0: gpu-alert-0 {
temperature = <70000>;

10
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
View File

@ -50,7 +50,7 @@ fan0: pwm-fan {
thermal-zones {
cpu0_thermal: cpu0-thermal {
thermal-sensors = <&tmu_cpu0 0>;
thermal-sensors = <&tmu_cpu0>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@ -139,7 +139,7 @@ cpu0_cooling_map4: map4 {
};
};
cpu1_thermal: cpu1-thermal {
thermal-sensors = <&tmu_cpu1 0>;
thermal-sensors = <&tmu_cpu1>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@ -212,7 +212,7 @@ cpu1_cooling_map4: map4 {
};
};
cpu2_thermal: cpu2-thermal {
thermal-sensors = <&tmu_cpu2 0>;
thermal-sensors = <&tmu_cpu2>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@ -285,7 +285,7 @@ cpu2_cooling_map4: map4 {
};
};
cpu3_thermal: cpu3-thermal {
thermal-sensors = <&tmu_cpu3 0>;
thermal-sensors = <&tmu_cpu3>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
@ -358,7 +358,7 @@ cpu3_cooling_map4: map4 {
};
};
gpu_thermal: gpu-thermal {
thermal-sensors = <&tmu_gpu 0>;
thermal-sensors = <&tmu_gpu>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {

2
arch/arm/boot/dts/imx7s.dtsi
View File

@ -513,7 +513,7 @@ gpr: iomuxc-gpr@30340000 {
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <0>;
#mux-control-cells = <1>;
mux-reg-masks = <0x14 0x00000010>;
};

2
arch/arm/boot/dts/qcom-sdx55.dtsi
View File

@ -577,7 +577,7 @@ pil-reloc@94c {
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x15000000 0x20000>;
#iommu-cells = <2>;
#global-interrupts = <1>;

2
arch/arm/boot/dts/qcom-sdx65.dtsi
View File

@ -455,7 +455,7 @@ pil-reloc@94c {
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x15000000 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;

1
arch/arm/boot/dts/stm32mp131.dtsi
View File

@ -405,6 +405,7 @@ bsec: efuse@5c005000 {
part_number_otp: part_number_otp@4 {
reg = <0x4 0x2>;
bits = <0 12>;
};
ts_cal1: calib@5c {
reg = <0x5c 0x2>;

2
arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
View File

@ -57,7 +57,7 @@ reg_vdd_cpux: vdd-cpux-regulator {
regulator-ramp-delay = <50>; /* 4ms */
enable-active-high;
enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
gpios-states = <0x1>;
states = <1100000 0>, <1300000 1>;

1
arch/arm/configs/bcm2835_defconfig
View File

@ -107,6 +107,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_DRM=y
CONFIG_DRM_V3D=y
CONFIG_DRM_VC4=y
CONFIG_FB=y
CONFIG_FB_SIMPLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_SOUND=y

24
arch/arm/mach-imx/mmdc.c
View File

@ -99,6 +99,7 @@ struct mmdc_pmu {
cpumask_t cpu;
struct hrtimer hrtimer;
unsigned int active_events;
int id;
struct device *dev;
struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
struct hlist_node node;
@ -433,8 +434,6 @@ static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer)
static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
void __iomem *mmdc_base, struct device *dev)
{
int mmdc_num;
*pmu_mmdc = (struct mmdc_pmu) {
.pmu = (struct pmu) {
.task_ctx_nr = perf_invalid_context,
@ -452,15 +451,16 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
.active_events = 0,
};
mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
pmu_mmdc->id = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
return mmdc_num;
return pmu_mmdc->id;
}
static int imx_mmdc_remove(struct platform_device *pdev)
{
struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
perf_pmu_unregister(&pmu_mmdc->pmu);
iounmap(pmu_mmdc->mmdc_base);
@ -474,7 +474,6 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
{
struct mmdc_pmu *pmu_mmdc;
char *name;
int mmdc_num;
int ret;
const struct of_device_id *of_id =
of_match_device(imx_mmdc_dt_ids, &pdev->dev);
@ -497,14 +496,14 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
cpuhp_mmdc_state = ret;
}
mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
if (mmdc_num == 0)
name = "mmdc";
else
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", mmdc_num);
ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
if (ret < 0)
goto pmu_free;
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", ret);
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
@ -525,6 +524,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
pmu_register_err:
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
hrtimer_cancel(&pmu_mmdc->hrtimer);
pmu_free:

2
arch/arm/mach-omap1/timer.c
View File

@ -158,7 +158,7 @@ static int __init omap1_dm_timer_init(void)
kfree(pdata);
err_free_pdev:
platform_device_unregister(pdev);
platform_device_put(pdev);
return ret;
}

1
arch/arm/mach-omap2/omap4-common.c
View File

@ -140,6 +140,7 @@ static int __init omap4_sram_init(void)
__func__);
else
sram_sync = (void __iomem *)gen_pool_alloc(sram_pool, PAGE_SIZE);
of_node_put(np);
return 0;
}

1
arch/arm/mach-omap2/timer.c
View File

@ -76,6 +76,7 @@ static void __init realtime_counter_init(void)
}
rate = clk_get_rate(sys_clk);
clk_put(sys_clk);
if (soc_is_dra7xx()) {
/*

3
arch/arm/mach-s3c/s3c64xx.c
View File

@ -173,7 +173,8 @@ static struct samsung_pwm_variant s3c64xx_pwm_variant = {
.tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
};
void __init s3c64xx_set_timer_source(unsigned int event, unsigned int source)
void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event,
enum s3c64xx_timer_mode source)
{
s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));

1
arch/arm/mach-zynq/slcr.c
View File

@ -213,6 +213,7 @@ int __init zynq_early_slcr_init(void)
zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
if (IS_ERR(zynq_slcr_regmap)) {
pr_err("%s: failed to find zynq-slcr\n", __func__);
of_node_put(np);
return -ENODEV;
}

1
arch/arm64/Kconfig
View File

@ -101,7 +101,6 @@ config ARM64
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
select ARCH_WANT_FRAME_POINTERS
select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
select ARCH_WANT_LD_ORPHAN_WARN
select ARCH_WANTS_NO_INSTR
select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES

10
arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi
View File

@ -168,15 +168,15 @@ sn: sn@32 {
reg = <0x32 0x20>;
};
eth_mac: eth_mac@0 {
eth_mac: eth-mac@0 {
reg = <0x0 0x6>;
};
bt_mac: bt_mac@6 {
bt_mac: bt-mac@6 {
reg = <0x6 0x6>;
};
wifi_mac: wifi_mac@c {
wifi_mac: wifi-mac@c {
reg = <0xc 0x6>;
};
@ -217,7 +217,7 @@ &i2c1 {
pinctrl-names = "default";
/* RTC */
pcf8563: pcf8563@51 {
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
status = "okay";
@ -303,7 +303,7 @@ &uart_AO_B {
&usb {
status = "okay";
phy-supply = <&usb_pwr>;
vbus-supply = <&usb_pwr>;
};
&spicc1 {

4
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

@ -152,7 +152,7 @@ scpi {
scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: clock-controller {
scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>;
@ -161,7 +161,7 @@ scpi_dvfs: clock-controller {
};
scpi_sensors: sensors {
compatible = "amlogic,meson-gxbb-scpi-sensors";
compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};

2
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View File

@ -1694,7 +1694,7 @@ int_mdio: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
internal_ephy: ethernet_phy@8 {
internal_ephy: ethernet-phy@8 {
compatible = "ethernet-phy-id0180.3301",
"ethernet-phy-ieee802.3-c22";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

1
arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
View File

@ -401,5 +401,4 @@ &uart_AO {
&usb {
status = "okay";
dr_mode = "host";
};

20
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
View File

@ -57,26 +57,6 @@ cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <731000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <731000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <731000>;
};
opp-667000000 {
opp-hz = /bits/ 64 <666666666>;
opp-microvolt = <731000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <731000>;

2
arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi
View File

@ -17,7 +17,7 @@ adc-keys {
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
update-button {
button-update {
label = "update";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <1300000>;

6
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@ -232,7 +232,7 @@ sn: sn@14 {
reg = <0x14 0x10>;
};
eth_mac: eth_mac@34 {
eth_mac: eth-mac@34 {
reg = <0x34 0x10>;
};
@ -249,7 +249,7 @@ scpi {
scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>;
@ -531,7 +531,7 @@ periphs: bus@c8834000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
hwrng: rng {
hwrng: rng@0 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};

2
arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts
View File

@ -16,7 +16,7 @@ / {
leds {
compatible = "gpio-leds";
status {
led {
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
default-state = "off";
color = <LED_COLOR_ID_RED>;

2
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
View File

@ -18,7 +18,7 @@ cvbs-connector {
leds {
compatible = "gpio-leds";
status {
led {
label = "n1:white:status";
gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
default-state = "on";

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts
View File

@ -79,6 +79,5 @@ bluetooth {
enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;
clock-names = "lpo";
};
};

6
arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts
View File

@ -86,11 +86,11 @@ sdio_pwrseq: sdio-pwrseq {
};
&efuse {
bt_mac: bt_mac@6 {
bt_mac: bt-mac@6 {
reg = <0x6 0x6>;
};
wifi_mac: wifi_mac@C {
wifi_mac: wifi-mac@c {
reg = <0xc 0x6>;
};
};
@ -239,7 +239,7 @@ &i2c_B {
pinctrl-names = "default";
pinctrl-0 = <&i2c_b_pins>;
pcf8563: pcf8563@51 {
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
status = "okay";

2
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -759,7 +759,7 @@ mux {
};
};
eth-phy-mux {
eth-phy-mux@55c {
compatible = "mdio-mux-mmioreg", "mdio-mux";
#address-cells = <1>;
#size-cells = <0>;

6
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts
View File

@ -17,13 +17,13 @@ / {
compatible = "bananapi,bpi-m5", "amlogic,sm1";
model = "Banana Pi BPI-M5";
adc_keys {
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 2>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
key {
button-sw3 {
label = "SW3";
linux,code = <BTN_3>;
press-threshold-microvolt = <1700000>;
@ -123,7 +123,7 @@ vddio_c: regulator-vddio_c {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
enable-gpio = <&gpio_ao GPIOE_2 GPIO_ACTIVE_HIGH>;
enable-gpio = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-always-on;

10
arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
View File

@ -76,9 +76,17 @@ sound {
};
&cpu_thermal {
trips {
cpu_active: cpu-active {
temperature = <60000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "active";
};
};
cooling-maps {
map {
trip = <&cpu_passive>;
trip = <&cpu_active>;
cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -562,7 +562,7 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
imx8mm_uid: unique-id@410 {
imx8mm_uid: unique-id@4 {
reg = <0x4 0x8>;
};

2
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -563,7 +563,7 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
imx8mn_uid: unique-id@410 {
imx8mn_uid: unique-id@4 {
reg = <0x4 0x8>;
};

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -424,7 +424,7 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
imx8mp_uid: unique-id@420 {
imx8mp_uid: unique-id@8 {
reg = <0x8 0x8>;
};

2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -592,7 +592,7 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
imx8mq_uid: soc-uid@410 {
imx8mq_uid: soc-uid@4 {
reg = <0x4 0x8>;
};

1
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@ -435,6 +435,7 @@ uart3: serial@11005000 {
pwm: pwm@11006000 {
compatible = "mediatek,mt7622-pwm";
reg = <0 0x11006000 0 0x1000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_PWM_SEL>,
<&pericfg CLK_PERI_PWM_PD>,

3
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@ -125,8 +125,7 @@ topckgen: topckgen@1001b000 {
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt",
"mediatek,mt6589-wdt";
compatible = "mediatek,mt7986-wdt";
reg = <0 0x1001c000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;

12
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -585,6 +585,15 @@ psci {
method = "smc";
};
clk13m: fixed-factor-clock-13m {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clk26m>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "clk13m";
};
clk26m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -968,8 +977,7 @@ systimer: timer@10017000 {
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CLK13M>;
clock-names = "clk13m";
clocks = <&clk13m>;
};
iommu: iommu@10205000 {

17
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View File

@ -47,14 +47,12 @@ core4 {
core5 {
cpu = <&cpu5>;
};
};
cluster1 {
core0 {
core6 {
cpu = <&cpu6>;
};
core1 {
core7 {
cpu = <&cpu7>;
};
};
@ -211,10 +209,12 @@ l3_0: l3-cache {
};
};
clk13m: oscillator-13m {
compatible = "fixed-clock";
clk13m: fixed-factor-clock-13m {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-frequency = <13000000>;
clocks = <&clk26m>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "clk13m";
};
@ -330,8 +330,7 @@ pio: pinctrl@10005000 {
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8186-wdt",
"mediatek,mt6589-wdt";
compatible = "mediatek,mt8186-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x1000>;
#reset-cells = <1>;

25
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@ -29,6 +29,15 @@ aliases {
rdma4 = &rdma4;
};
clk13m: fixed-factor-clock-13m {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clk26m>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "clk13m";
};
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -149,19 +158,16 @@ core2 {
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
core4 {
cpu = <&cpu4>;
};
core1 {
core5 {
cpu = <&cpu5>;
};
core2 {
core6 {
cpu = <&cpu6>;
};
core3 {
core7 {
cpu = <&cpu7>;
};
};
@ -531,8 +537,7 @@ systimer: timer@10017000 {
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
clock-names = "clk13m";
clocks = <&clk13m>;
};
pwrap: pwrap@10026000 {
@ -575,6 +580,8 @@ scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
#clock-cells = <1>;
/* power domain dependency not upstreamed */
status = "fail";
};
uart0: serial@11002000 {

25
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -150,22 +150,20 @@ core2 {
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
core4 {
cpu = <&cpu4>;
};
core1 {
core5 {
cpu = <&cpu5>;
};
core2 {
core6 {
cpu = <&cpu6>;
};
core3 {
core7 {
cpu = <&cpu7>;
};
};
@ -244,6 +242,15 @@ sound: mt8195-sound {
status = "disabled";
};
clk13m: fixed-factor-clock-13m {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clk26m>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "clk13m";
};
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -683,8 +690,7 @@ power-domain@MT8195_POWER_DOMAIN_AUDIO {
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
compatible = "mediatek,mt8195-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
#reset-cells = <1>;
@ -701,7 +707,7 @@ systimer: timer@10017000 {
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_CLK26M_D2>;
clocks = <&clk13m>;
};
pwrap: pwrap@10024000 {
@ -1410,6 +1416,7 @@ u3phy1: t-phy@11e30000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11e30000 0xe00>;
power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
status = "disabled";
u2port1: usb-phy@0 {

2
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
View File

@ -1666,7 +1666,7 @@ vdd_hdmi: regulator-vdd-hdmi {
vin-supply = <&vdd_5v0_sys>;
};
vdd_cam_1v2: regulator-vdd-cam-1v8 {
vdd_cam_1v2: regulator-vdd-cam-1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd-cam-1v2";
regulator-min-microvolt = <1200000>;

63
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -137,7 +137,7 @@ usb1_ssphy: phy@58200 {
#clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb1_pipe_clk_src";
clock-output-names = "usb3phy_1_cc_pipe_clk";
};
};
@ -180,7 +180,7 @@ usb0_ssphy: phy@78200 {
#clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";
clock-output-names = "usb3phy_0_cc_pipe_clk";
};
};
@ -197,9 +197,9 @@ qusb_phy_0: phy@79000 {
status = "disabled";
};
pcie_qmp0: phy@86000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x00086000 0x1c4>;
pcie_qmp0: phy@84000 {
compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
reg = <0x00084000 0x1bc>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -213,15 +213,16 @@ pcie_qmp0: phy@86000 {
"common";
status = "disabled";
pcie_phy0: phy@86200 {
reg = <0x86200 0x16c>,
<0x86400 0x200>,
<0x86800 0x4f4>;
pcie_phy0: phy@84200 {
reg = <0x84200 0x16c>,
<0x84400 0x200>,
<0x84800 0x1f0>,
<0x84c00 0xf4>;
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "pcie_0_pipe_clk";
clock-output-names = "pcie20_phy0_pipe_clk";
};
};
@ -242,14 +243,14 @@ pcie_qmp1: phy@8e000 {
status = "disabled";
pcie_phy1: phy@8e200 {
reg = <0x8e200 0x16c>,
reg = <0x8e200 0x130>,
<0x8e400 0x200>,
<0x8e800 0x4f4>;
<0x8e800 0x1f8>;
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "pcie_1_pipe_clk";
clock-output-names = "pcie20_phy1_pipe_clk";
};
};
@ -750,9 +751,9 @@ pcie1: pci@10000000 {
phy-names = "pciephy";
ranges = <0x81000000 0 0x10200000 0x10200000
0 0x100000 /* downstream I/O */
0x82000000 0 0x10300000 0x10300000
0 0xd00000>; /* non-prefetchable memory */
0 0x10000>, /* downstream I/O */
<0x82000000 0 0x10220000 0x10220000
0 0xfde0000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@ -795,16 +796,18 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
};
pcie0: pci@20000000 {
compatible = "qcom,pcie-ipq8074";
compatible = "qcom,pcie-ipq8074-gen3";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
<0x00080000 0x2000>,
<0x20001000 0x1000>,
<0x00080000 0x4000>,
<0x20100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
reg-names = "dbi", "elbi", "atu", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
max-link-speed = <3>;
#address-cells = <3>;
#size-cells = <2>;
@ -812,9 +815,9 @@ pcie0: pci@20000000 {
phy-names = "pciephy";
ranges = <0x81000000 0 0x20200000 0x20200000
0 0x100000 /* downstream I/O */
0x82000000 0 0x20300000 0x20300000
0 0xd00000>; /* non-prefetchable memory */
0 0x10000>, /* downstream I/O */
<0x82000000 0 0x20220000 0x20220000
0 0xfde0000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@ -832,28 +835,30 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,
<&gcc GCC_PCIE0_AXI_S_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>,
<&gcc GCC_PCIE0_AUX_CLK>;
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE0_RCHNG_CLK>;
clock-names = "iface",
"axi_m",
"axi_s",
"ahb",
"aux";
"axi_bridge",
"rchng";
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
<&gcc GCC_PCIE0_SLEEP_ARES>,
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
<&gcc GCC_PCIE0_AHB_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
reset-names = "pipe",
"sleep",
"sticky",
"axi_m",
"axi_s",
"ahb",
"axi_m_sticky";
"axi_m_sticky",
"axi_s_sticky";
status = "disabled";
};
};

2
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -455,7 +455,7 @@ tlmm: pinctrl@1000000 {
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 155>;
gpio-ranges = <&tlmm 0 0 142>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;

3
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts
View File

@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) Jean Thomas <virgule@jeanthomas.me>
/*
* Copyright (c) Jean Thomas <virgule@jeanthomas.me>
*/
/dts-v1/;

3
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts
View File

@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) Jean Thomas <virgule@jeanthomas.me>
/*
* Copyright (c) Jean Thomas <virgule@jeanthomas.me>
*/
/dts-v1/;

37
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
View File

@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015, LGE Inc. All rights reserved.
/*
* Copyright (c) 2015, LGE Inc. All rights reserved.
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com>
* Copyright (c) 2021-2022, Petr Vorel <petr.vorel@gmail.com>
* Copyright (c) 2022, Dominik Kobinski <dominikkobinski314@gmail.com>
*/
/dts-v1/;
@ -13,6 +15,9 @@
/* cont_splash_mem has different memory mapping */
/delete-node/ &cont_splash_mem;
/* disabled on downstream, conflicts with cont_splash_mem */
/delete-node/ &dfps_data_mem;
/ {
model = "LG Nexus 5X";
compatible = "lg,bullhead", "qcom,msm8992";
@ -47,7 +52,17 @@ ramoops@1ff00000 {
};
cont_splash_mem: memory@3400000 {
reg = <0 0x03400000 0 0x1200000>;
reg = <0 0x03400000 0 0xc00000>;
no-map;
};
reserved@5000000 {
reg = <0x0 0x05000000 0x0 0x1a00000>;
no-map;
};
reserved@6c00000 {
reg = <0x0 0x06c00000 0x0 0x400000>;
no-map;
};
};
@ -79,8 +94,8 @@ pm8994_regulators: pm8994-regulators {
/* S1, S2, S6 and S12 are managed by RPMPD */
pm8994_s1: s1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-min-microvolt = <1025000>;
regulator-max-microvolt = <1025000>;
};
pm8994_s2: s2 {
@ -236,9 +251,8 @@ pm8994_l25: l25 {
};
pm8994_l26: l26 {
/* TODO: value from downstream
regulator-min-microvolt = <987500>;
fails to apply */
regulator-max-microvolt = <987500>;
};
pm8994_l27: l27 {
@ -252,19 +266,13 @@ pm8994_l28: l28 {
};
pm8994_l29: l29 {
/* TODO: Unsupported voltage range.
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,init-voltage = <2800000>;
*/
};
pm8994_l30: l30 {
/* TODO: get this verified
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
*/
};
pm8994_l31: l31 {
@ -273,11 +281,8 @@ pm8994_l31: l31 {
};
pm8994_l32: l32 {
/* TODO: get this verified
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
*/
};
};

3
arch/arm64/boot/dts/qcom/msm8992.dtsi
View File

@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
/*
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
#include "msm8994.dtsi"

5
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
View File

@ -944,10 +944,6 @@ touch_int_sleep: touch-int-sleep {
};
};
/*
* For reasons that are currently unknown (but probably related to fusb301), USB takes about
* 6 minutes to wake up (nothing interesting in kernel logs), but then it works as it should.
*/
&usb3 {
status = "okay";
qcom,select-utmi-as-pipe-clk;
@ -956,6 +952,7 @@ &usb3 {
&usb3_dwc3 {
extcon = <&usb3_id>;
dr_mode = "peripheral";
maximum-speed = "high-speed";
phys = <&hsusb_phy1>;
phy-names = "usb2-phy";
snps,hird-threshold = /bits/ 8 <0>;

22
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -712,7 +712,7 @@ gcc: clock-controller@300000 {
#power-domain-cells = <1>;
reg = <0x00300000 0x90000>;
clocks = <&rpmcc RPM_SMD_BB_CLK1>,
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_LN_BB_CLK>,
<&sleep_clk>,
<&pciephy_0>,
@ -829,9 +829,11 @@ a2noc: interconnect@583000 {
compatible = "qcom,msm8996-a2noc";
reg = <0x00583000 0x7000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_UFS_AXI_CLK>;
};
mnoc: interconnect@5a4000 {
@ -1050,7 +1052,7 @@ dsi0_phy: dsi-phy@994400 {
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
@ -1118,7 +1120,7 @@ dsi1_phy: dsi-phy@996400 {
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
@ -2932,8 +2934,8 @@ kryocc: clock-controller@6400000 {
compatible = "qcom,msm8996-apcc";
reg = <0x06400000 0x90000>;
clock-names = "xo";
clocks = <&rpmcc RPM_SMD_BB_CLK1>;
clock-names = "xo", "sys_apcs_aux";
clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
#clock-cells = <1>;
};
@ -3052,7 +3054,7 @@ sdhc1: mmc@7464900 {
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmcc RPM_SMD_BB_CLK1>;
<&rpmcc RPM_SMD_XO_CLK_SRC>;
resets = <&gcc GCC_SDCC1_BCR>;
pinctrl-names = "default", "sleep";
@ -3076,7 +3078,7 @@ sdhc2: mmc@74a4900 {
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmcc RPM_SMD_BB_CLK1>;
<&rpmcc RPM_SMD_XO_CLK_SRC>;
resets = <&gcc GCC_SDCC2_BCR>;
pinctrl-names = "default", "sleep";
@ -3383,7 +3385,7 @@ adsp_pil: remoteproc@9300000 {
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmcc RPM_SMD_BB_CLK1>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
memory-region = <&adsp_mem>;

5
arch/arm64/boot/dts/qcom/pmk8350.dtsi
View File

@ -16,8 +16,9 @@ pmk8350: pmic@0 {
#size-cells = <0>;
pmk8350_pon: pon@1300 {
compatible = "qcom,pm8998-pon";
reg = <0x1300>;
compatible = "qcom,pmk8350-pon";
reg = <0x1300>, <0x800>;
reg-names = "hlos", "pbs";
pon_pwrkey: pwrkey {
compatible = "qcom,pmk8350-pwrkey";

12
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -792,7 +792,7 @@ pcie_phy: phy@7786000 {
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
<&gcc 21>;
<&gcc GCC_PCIE_0_PIPE_ARES>;
reset-names = "phy", "pipe";
clock-output-names = "pcie_0_pipe_clk";
@ -1322,12 +1322,12 @@ pcie: pci@10000000 {
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
clock-names = "iface", "aux", "master_bus", "slave_bus";
resets = <&gcc 18>,
<&gcc 17>,
<&gcc 15>,
<&gcc 19>,
resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
<&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
<&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
<&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE_0_BCR>,
<&gcc 16>;
<&gcc GCC_PCIE_0_AHB_ARES>;
reset-names = "axi_m",
"axi_s",
"axi_m_sticky",

4
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -3238,8 +3238,8 @@ spmi_bus: spmi@c440000 {
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;

4
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -4242,8 +4242,8 @@ spmi_bus: spmi@c440000 {
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};

6
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -1287,6 +1287,7 @@ usb_0: usb@a6f8800 {
"ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
@ -1341,6 +1342,7 @@ usb_1: usb@a8f8800 {
"ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_SEC_BCR>;
@ -1470,8 +1472,8 @@ spmi_bus: spmi@c440000 {
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};

2
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@ -969,7 +969,7 @@ sdc2_card_det_n: sd-card-det-n {
};
wcd_intr_default: wcd_intr_default {
pins = <54>;
pins = "gpio54";
function = "gpio";
input-enable;

19
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
View File

@ -40,17 +40,18 @@ extcon_usb: extcon-usb {
};
gpio-keys {
status = "okay";
compatible = "gpio-keys";
autorepeat;
key-vol-dn {
pinctrl-0 = <&vol_down_n>;
pinctrl-names = "default";
key-volume-down {
label = "Volume Down";
gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEDOWN>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
@ -108,6 +109,14 @@ &sdhc_1 {
&tlmm {
gpio-reserved-ranges = <22 2>, <28 6>;
vol_down_n: vol-down-n-state {
pins = "gpio47";
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
};
&usb3 {

6
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@ -442,9 +442,9 @@ hsusb_phy1: phy@1613000 {
reg = <0x01613000 0x180>;
#phy-cells = <0>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_AHB2PHY_USB_CLK>;
clock-names = "ref", "cfg_ahb";
clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
status = "disabled";

7
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -342,13 +342,12 @@ last_log_region: memory@ffbc0000 {
};
ramoops: ramoops@ffc00000 {
compatible = "removed-dma-pool", "ramoops";
reg = <0 0xffc00000 0 0x00100000>;
compatible = "ramoops";
reg = <0 0xffc00000 0 0x100000>;
record-size = <0x1000>;
console-size = <0x40000>;
ftrace-size = <0x0>;
msg-size = <0x20000 0x20000>;
cc-size = <0x0>;
ecc-size = <16>;
no-map;
};

7
arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi
View File

@ -33,9 +33,10 @@ chosen {
framebuffer: framebuffer@9c000000 {
compatible = "simple-framebuffer";
reg = <0 0x9c000000 0 0x2300000>;
width = <1644>;
height = <3840>;
stride = <(1644 * 4)>;
/* Griffin BL initializes in 2.5k mode, not 4k */
width = <1096>;
height = <2560>;
stride = <(1096 * 4)>;
format = "a8r8g8b8";
/*
* That's (going to be) a lot of clocks, but it's necessary due

2
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -1043,8 +1043,6 @@ uart2: serial@98c000 {
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

4
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -991,8 +991,6 @@ uart20: serial@894000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart20_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -1387,8 +1385,6 @@ uart7: serial@99c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};

24
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
View File

@ -437,20 +437,6 @@ wm8962_endpoint: endpoint {
};
};
/* 0 - lcd_reset */
/* 1 - lcd_pwr */
/* 2 - lcd_select */
/* 3 - backlight-enable */
/* 4 - Touch_shdwn */
/* 5 - LCD_H_pol */
/* 6 - lcd_V_pol */
gpio_exp1: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
touchscreen@26 {
compatible = "ilitek,ili2117";
reg = <0x26>;
@ -482,6 +468,16 @@ hd3ss3220_out_ep: endpoint {
};
};
};
gpio_exp1: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select",
"backlight-enable", "Touch_shdwn",
"LCD_H_pol", "lcd_V_pol";
};
};
&lvds0 {

9
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
View File

@ -306,7 +306,8 @@ main_spi0: spi@20100000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 172 0>;
clocks = <&k3_clks 141 0>;
status = "disabled";
};
main_spi1: spi@20110000 {
@ -316,7 +317,8 @@ main_spi1: spi@20110000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 173 0>;
clocks = <&k3_clks 142 0>;
status = "disabled";
};
main_spi2: spi@20120000 {
@ -326,7 +328,8 @@ main_spi2: spi@20120000 {
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 174 0>;
clocks = <&k3_clks 143 0>;
status = "disabled";
};
main_gpio_intr: interrupt-controller@a00000 {

2
arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
View File

@ -42,6 +42,7 @@ mcu_spi0: spi@4b00000 {
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
status = "disabled";
};
mcu_spi1: spi@4b10000 {
@ -52,6 +53,7 @@ mcu_spi1: spi@4b10000 {
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
status = "disabled";
};
mcu_gpio_intr: interrupt-controller@4210000 {

2
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View File

@ -80,7 +80,7 @@ vdd_sd_dv: gpio-regulator-TLV71033 {
};
};
&wkup_pmx0 {
&wkup_pmx2 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */

29
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
View File

@ -56,7 +56,34 @@ chipid@43000014 {
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
reg = <0x00 0x4301c000 0x00 0x34>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx1: pinctrl@0x4301c038 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c038 0x00 0x8>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx2: pinctrl@0x4301c068 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c068 0x00 0xec>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx3: pinctrl@0x4301c174 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c174 0x00 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;

2
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View File

@ -825,6 +825,7 @@ dwc3_0: usb@fe200000 {
clock-names = "bus_early", "ref";
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,resume-hs-terminations;
/* dma-coherent; */
};
};
@ -851,6 +852,7 @@ dwc3_1: usb@fe300000 {
clock-names = "bus_early", "ref";
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,resume-hs-terminations;
/* dma-coherent; */
};
};

2
arch/arm64/kernel/cpufeature.c
View File

@ -2757,7 +2757,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_DIT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),

2
arch/loongarch/net/bpf_jit.c
View File

@ -782,7 +782,7 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, bool ext
if (ret < 0)
return ret;
move_imm(ctx, t1, func_addr, is32);
move_addr(ctx, t1, func_addr);
emit_insn(ctx, jirl, t1, LOONGARCH_GPR_RA, 0);
move_reg(ctx, regmap[BPF_REG_0], LOONGARCH_GPR_A0);
break;

21
arch/loongarch/net/bpf_jit.h
View File

@ -80,6 +80,27 @@ static inline void emit_sext_32(struct jit_ctx *ctx, enum loongarch_gpr reg, boo
emit_insn(ctx, addiw, reg, reg, 0);
}
static inline void move_addr(struct jit_ctx *ctx, enum loongarch_gpr rd, u64 addr)
{
u64 imm_11_0, imm_31_12, imm_51_32, imm_63_52;
/* lu12iw rd, imm_31_12 */
imm_31_12 = (addr >> 12) & 0xfffff;
emit_insn(ctx, lu12iw, rd, imm_31_12);
/* ori rd, rd, imm_11_0 */
imm_11_0 = addr & 0xfff;
emit_insn(ctx, ori, rd, rd, imm_11_0);
/* lu32id rd, imm_51_32 */
imm_51_32 = (addr >> 32) & 0xfffff;
emit_insn(ctx, lu32id, rd, imm_51_32);
/* lu52id rd, rd, imm_63_52 */
imm_63_52 = (addr >> 52) & 0xfff;
emit_insn(ctx, lu52id, rd, rd, imm_63_52);
}
static inline void move_imm(struct jit_ctx *ctx, enum loongarch_gpr rd, long imm, bool is32)
{
long imm_11_0, imm_31_12, imm_51_32, imm_63_52, imm_51_0, imm_51_31;

2
arch/m68k/68000/entry.S
View File

@ -45,6 +45,8 @@ do_trace:
jbsr syscall_trace_enter
RESTORE_SWITCH_STACK
addql #4,%sp
addql #1,%d0
jeq ret_from_exception
movel %sp@(PT_OFF_ORIG_D0),%d1
movel #-ENOSYS,%d0
cmpl #NR_syscalls,%d1

1
arch/m68k/Kconfig.devices
View File

@ -19,6 +19,7 @@ config HEARTBEAT
# We have a dedicated heartbeat LED. :-)
config PROC_HARDWARE
bool "/proc/hardware support"
depends on PROC_FS
help
Say Y here to support the /proc/hardware file, which gives you
access to information about the machine you're running on,

2
arch/m68k/coldfire/entry.S
View File

@ -90,6 +90,8 @@ ENTRY(system_call)
jbsr syscall_trace_enter
RESTORE_SWITCH_STACK
addql #4,%sp
addql #1,%d0
jeq ret_from_exception
movel %d3,%a0
jbsr %a0@
movel %d0,%sp@(PT_OFF_D0) /* save the return value */

3
arch/m68k/kernel/entry.S
View File

@ -184,9 +184,12 @@ do_trace_entry:
jbsr syscall_trace_enter
RESTORE_SWITCH_STACK
addql #4,%sp
addql #1,%d0 | optimization for cmpil #-1,%d0
jeq ret_from_syscall
movel %sp@(PT_OFF_ORIG_D0),%d0
cmpl #NR_syscalls,%d0
jcs syscall
jra ret_from_syscall
badsys:
movel #-ENOSYS,%sp@(PT_OFF_D0)
jra ret_from_syscall

2
arch/mips/boot/dts/ingenic/ci20.dts
View File

@ -113,7 +113,7 @@ otg_power: fixedregulator@2 {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpf 14 GPIO_ACTIVE_LOW>;
gpio = <&gpf 15 GPIO_ACTIVE_LOW>;
enable-active-high;
};
};

2
arch/mips/include/asm/syscall.h
View File

@ -38,7 +38,7 @@ static inline bool mips_syscall_is_indirect(struct task_struct *task,
static inline long syscall_get_nr(struct task_struct *task,
struct pt_regs *regs)
{
return current_thread_info()->syscall;
return task_thread_info(task)->syscall;
}
static inline void mips_syscall_update_nr(struct task_struct *task,

2
arch/powerpc/Makefile
View File

@ -90,7 +90,7 @@ aflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -mlittle-endian
ifeq ($(HAS_BIARCH),y)
KBUILD_CFLAGS += -m$(BITS)
KBUILD_AFLAGS += -m$(BITS) -Wl,-a$(BITS)
KBUILD_AFLAGS += -m$(BITS)
KBUILD_LDFLAGS += -m elf$(BITS)$(LDEMULATION)
endif

11
arch/powerpc/mm/book3s64/radix_tlb.c
View File

@ -1179,15 +1179,12 @@ static inline void __radix__flush_tlb_range(struct mm_struct *mm,
}
}
} else {
bool hflush = false;
bool hflush;
unsigned long hstart, hend;
if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
hstart = (start + PMD_SIZE - 1) & PMD_MASK;
hend = end & PMD_MASK;
if (hstart < hend)
hflush = true;
}
hstart = (start + PMD_SIZE - 1) & PMD_MASK;
hend = end & PMD_MASK;
hflush = IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && hstart < hend;
if (type == FLUSH_TYPE_LOCAL) {
asm volatile("ptesync": : :"memory");

6
arch/riscv/Makefile
View File

@ -11,7 +11,11 @@ LDFLAGS_vmlinux :=
ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
LDFLAGS_vmlinux := --no-relax
KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
CC_FLAGS_FTRACE := -fpatchable-function-entry=8
ifeq ($(CONFIG_RISCV_ISA_C),y)
CC_FLAGS_FTRACE := -fpatchable-function-entry=4
else
CC_FLAGS_FTRACE := -fpatchable-function-entry=2
endif
endif
ifeq ($(CONFIG_CMODEL_MEDLOW),y)

50
arch/riscv/include/asm/ftrace.h
View File

@ -42,6 +42,14 @@ struct dyn_arch_ftrace {
* 2) jalr: setting low-12 offset to ra, jump to ra, and set ra to
* return address (original pc + 4)
*
*<ftrace enable>:
* 0: auipc t0/ra, 0x?
* 4: jalr t0/ra, ?(t0/ra)
*
*<ftrace disable>:
* 0: nop
* 4: nop
*
* Dynamic ftrace generates probes to call sites, so we must deal with
* both auipc and jalr at the same time.
*/
@ -52,25 +60,43 @@ struct dyn_arch_ftrace {
#define AUIPC_OFFSET_MASK (0xfffff000)
#define AUIPC_PAD (0x00001000)
#define JALR_SHIFT 20
#define JALR_BASIC (0x000080e7)
#define AUIPC_BASIC (0x00000097)
#define JALR_RA (0x000080e7)
#define AUIPC_RA (0x00000097)
#define JALR_T0 (0x000282e7)
#define AUIPC_T0 (0x00000297)
#define NOP4 (0x00000013)
#define make_call(caller, callee, call) \
#define to_jalr_t0(offset) \
(((offset & JALR_OFFSET_MASK) << JALR_SHIFT) | JALR_T0)
#define to_auipc_t0(offset) \
((offset & JALR_SIGN_MASK) ? \
(((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) | AUIPC_T0) : \
((offset & AUIPC_OFFSET_MASK) | AUIPC_T0))
#define make_call_t0(caller, callee, call) \
do { \
call[0] = to_auipc_insn((unsigned int)((unsigned long)callee - \
(unsigned long)caller)); \
call[1] = to_jalr_insn((unsigned int)((unsigned long)callee - \
(unsigned long)caller)); \
unsigned int offset = \
(unsigned long) callee - (unsigned long) caller; \
call[0] = to_auipc_t0(offset); \
call[1] = to_jalr_t0(offset); \
} while (0)
#define to_jalr_insn(offset) \
(((offset & JALR_OFFSET_MASK) << JALR_SHIFT) | JALR_BASIC)
#define to_jalr_ra(offset) \
(((offset & JALR_OFFSET_MASK) << JALR_SHIFT) | JALR_RA)
#define to_auipc_insn(offset) \
#define to_auipc_ra(offset) \
((offset & JALR_SIGN_MASK) ? \
(((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) | AUIPC_BASIC) : \
((offset & AUIPC_OFFSET_MASK) | AUIPC_BASIC))
(((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) | AUIPC_RA) : \
((offset & AUIPC_OFFSET_MASK) | AUIPC_RA))
#define make_call_ra(caller, callee, call) \
do { \
unsigned int offset = \
(unsigned long) callee - (unsigned long) caller; \
call[0] = to_auipc_ra(offset); \
call[1] = to_jalr_ra(offset); \
} while (0)
/*
* Let auipc+jalr be the basic *mcount unit*, so we make it 8 bytes here.

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