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mmc: rtsx: fix tuning fail on gen3 PCI-Express

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On gen3 PCI-Express we should send command one by one.
If sending many commands in one packet will lead to a failure.

Signed-off-by: rui_feng <rui_feng@realsil.com.cn>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
rui_feng
2017-09-22 16:07:35 +08:00
committed by Ulf Hansson
parent c8b5fd031a
commit 563be8b603
2 changed files with 19 additions and 20 deletions
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38
drivers/mmc/host/rtsx_pci_sdmmc.c
View File

@ -618,29 +618,22 @@ static int sd_change_phase(struct realtek_pci_sdmmc *host,
u8 sample_point, bool rx) u8 sample_point, bool rx)
{ {
struct rtsx_pcr *pcr = host->pcr; struct rtsx_pcr *pcr = host->pcr;
int err;
dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
__func__, rx ? "RX" : "TX", sample_point); __func__, rx ? "RX" : "TX", sample_point);
rtsx_pci_init_cmd(pcr); rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
if (rx) if (rx)
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, rtsx_pci_write_register(pcr, SD_VPRX_CTL,
SD_VPRX_CTL, 0x1F, sample_point); PHASE_SELECT_MASK, sample_point);
else else
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, rtsx_pci_write_register(pcr, SD_VPTX_CTL,
SD_VPTX_CTL, 0x1F, sample_point); PHASE_SELECT_MASK, sample_point);
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET,
PHASE_NOT_RESET, PHASE_NOT_RESET); PHASE_NOT_RESET);
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
err = rtsx_pci_send_cmd(pcr, 100);
if (err < 0)
return err;
return 0; return 0;
} }
@ -708,10 +701,12 @@ static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
{ {
int err; int err;
struct mmc_command cmd = {}; struct mmc_command cmd = {};
struct rtsx_pcr *pcr = host->pcr;
err = sd_change_phase(host, sample_point, true); sd_change_phase(host, sample_point, true);
if (err < 0)
return err; rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
SD_RSP_80CLK_TIMEOUT_EN);
cmd.opcode = opcode; cmd.opcode = opcode;
err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
@ -719,9 +714,12 @@ static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
/* Wait till SD DATA IDLE */ /* Wait till SD DATA IDLE */
sd_wait_data_idle(host); sd_wait_data_idle(host);
sd_clear_error(host); sd_clear_error(host);
rtsx_pci_write_register(pcr, SD_CFG3,
SD_RSP_80CLK_TIMEOUT_EN, 0);
return err; return err;
} }
rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
return 0; return 0;
} }

1
include/linux/mfd/rtsx_pci.h
View File

@ -334,6 +334,7 @@
#define DCM_DRP_RD_DATA_H 0xFC29 #define DCM_DRP_RD_DATA_H 0xFC29
#define SD_VPCLK0_CTL 0xFC2A #define SD_VPCLK0_CTL 0xFC2A
#define SD_VPCLK1_CTL 0xFC2B #define SD_VPCLK1_CTL 0xFC2B
#define PHASE_SELECT_MASK 0x1F
#define SD_DCMPS0_CTL 0xFC2C #define SD_DCMPS0_CTL 0xFC2C
#define SD_DCMPS1_CTL 0xFC2D #define SD_DCMPS1_CTL 0xFC2D
#define SD_VPTX_CTL SD_VPCLK0_CTL #define SD_VPTX_CTL SD_VPCLK0_CTL