SPEAr: clk: Add VCO-PLL Synthesizer clock
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Viresh Kumar
Arnd Bergmann
parent
e12ff34402
commit
55b8fd4f42
@ -2,3 +2,6 @@
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obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
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clk-mux.o clk-divider.o clk-fixed-factor.o
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# SoCs specific
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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5
drivers/clk/spear/Makefile
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5
drivers/clk/spear/Makefile
Normal file
@ -0,0 +1,5 @@
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#
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# SPEAr Clock specific Makefile
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#
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obj-y += clk.o clk-vco-pll.o
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363
drivers/clk/spear/clk-vco-pll.c
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363
drivers/clk/spear/clk-vco-pll.c
Normal file
@ -0,0 +1,363 @@
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/*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* VCO-PLL clock implementation
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*/
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#define pr_fmt(fmt) "clk-vco-pll: " fmt
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include "clk.h"
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/*
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* DOC: VCO-PLL clock
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*
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* VCO and PLL rate are derived from following equations:
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*
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* In normal mode
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* vco = (2 * M[15:8] * Fin)/N
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*
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* In Dithered mode
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* vco = (2 * M[15:0] * Fin)/(256 * N)
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*
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* pll_rate = pll/2^p
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*
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* vco and pll are very closely bound to each other, "vco needs to program:
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* mode, m & n" and "pll needs to program p", both share common enable/disable
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* logic.
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*
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* clk_register_vco_pll() registers instances of both vco & pll.
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* CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its
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* set_rate to vco. A single rate table exists for both the clocks, which
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* configures m, n and p.
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*/
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/* PLL_CTR register masks */
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#define PLL_MODE_NORMAL 0
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#define PLL_MODE_FRACTION 1
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#define PLL_MODE_DITH_DSM 2
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#define PLL_MODE_DITH_SSM 3
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#define PLL_MODE_MASK 3
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#define PLL_MODE_SHIFT 3
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#define PLL_ENABLE 2
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#define PLL_LOCK_SHIFT 0
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#define PLL_LOCK_MASK 1
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/* PLL FRQ register masks */
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#define PLL_NORM_FDBK_M_MASK 0xFF
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#define PLL_NORM_FDBK_M_SHIFT 24
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#define PLL_DITH_FDBK_M_MASK 0xFFFF
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#define PLL_DITH_FDBK_M_SHIFT 16
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#define PLL_DIV_P_MASK 0x7
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#define PLL_DIV_P_SHIFT 8
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#define PLL_DIV_N_MASK 0xFF
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#define PLL_DIV_N_SHIFT 0
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#define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw)
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#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
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/* Calculates pll clk rate for specific value of mode, m, n and p */
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static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
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unsigned long prate, int index, unsigned long *pll_rate)
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{
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unsigned long rate = prate;
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unsigned int mode;
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mode = rtbl[index].mode ? 256 : 1;
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rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));
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if (pll_rate)
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*pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
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return rate * 10000;
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}
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static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
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unsigned long *prate, int *index)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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unsigned long prev_rate, vco_prev_rate, rate = 0;
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unsigned long vco_parent_rate =
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__clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
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if (!prate) {
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pr_err("%s: prate is must for pll clk\n", __func__);
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return -EINVAL;
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}
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for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) {
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prev_rate = rate;
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vco_prev_rate = *prate;
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*prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
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&rate);
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if (drate < rate) {
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/* previous clock was best */
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if (*index) {
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rate = prev_rate;
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*prate = vco_prev_rate;
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(*index)--;
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}
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break;
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}
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}
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return rate;
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}
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static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long *prate)
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{
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int unused;
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return clk_pll_round_rate_index(hw, drate, prate, &unused);
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}
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long
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parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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unsigned int p;
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if (pll->vco->lock)
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spin_lock_irqsave(pll->vco->lock, flags);
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p = readl_relaxed(pll->vco->cfg_reg);
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if (pll->vco->lock)
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spin_unlock_irqrestore(pll->vco->lock, flags);
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p = (p >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
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return parent_rate / (1 << p);
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}
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static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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struct pll_rate_tbl *rtbl = pll->vco->rtbl;
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unsigned long flags = 0, val;
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int i;
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clk_pll_round_rate_index(hw, drate, NULL, &i);
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if (pll->vco->lock)
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spin_lock_irqsave(pll->vco->lock, flags);
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val = readl_relaxed(pll->vco->cfg_reg);
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val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT);
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val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
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writel_relaxed(val, pll->vco->cfg_reg);
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if (pll->vco->lock)
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spin_unlock_irqrestore(pll->vco->lock, flags);
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return 0;
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}
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static struct clk_ops clk_pll_ops = {
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.recalc_rate = clk_pll_recalc_rate,
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.round_rate = clk_pll_round_rate,
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.set_rate = clk_pll_set_rate,
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};
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static inline unsigned long vco_calc_rate(struct clk_hw *hw,
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unsigned long prate, int index)
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{
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struct clk_vco *vco = to_clk_vco(hw);
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return pll_calc_rate(vco->rtbl, prate, index, NULL);
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}
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static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long *prate)
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{
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struct clk_vco *vco = to_clk_vco(hw);
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int unused;
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return clk_round_rate_index(hw, drate, *prate, vco_calc_rate,
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vco->rtbl_cnt, &unused);
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}
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static unsigned long clk_vco_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_vco *vco = to_clk_vco(hw);
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unsigned long flags = 0;
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unsigned int num = 2, den = 0, val, mode = 0;
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if (vco->lock)
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spin_lock_irqsave(vco->lock, flags);
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mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
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val = readl_relaxed(vco->cfg_reg);
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if (vco->lock)
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spin_unlock_irqrestore(vco->lock, flags);
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den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
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/* calculate numerator & denominator */
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if (!mode) {
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/* Normal mode */
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num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
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} else {
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/* Dithered mode */
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num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
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den *= 256;
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}
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if (!den) {
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WARN(1, "%s: denominator can't be zero\n", __func__);
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return 0;
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}
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return (((parent_rate / 10000) * num) / den) * 10000;
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}
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/* Configures new clock rate of vco */
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static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct clk_vco *vco = to_clk_vco(hw);
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struct pll_rate_tbl *rtbl = vco->rtbl;
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unsigned long flags = 0, val;
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int i;
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clk_round_rate_index(hw, drate, prate, vco_calc_rate, vco->rtbl_cnt,
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&i);
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if (vco->lock)
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spin_lock_irqsave(vco->lock, flags);
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val = readl_relaxed(vco->mode_reg);
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val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
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val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
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writel_relaxed(val, vco->mode_reg);
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val = readl_relaxed(vco->cfg_reg);
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val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT);
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val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
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val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT);
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if (rtbl[i].mode)
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val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
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PLL_DITH_FDBK_M_SHIFT;
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else
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val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
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PLL_NORM_FDBK_M_SHIFT;
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writel_relaxed(val, vco->cfg_reg);
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if (vco->lock)
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spin_unlock_irqrestore(vco->lock, flags);
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return 0;
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}
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static struct clk_ops clk_vco_ops = {
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.recalc_rate = clk_vco_recalc_rate,
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.round_rate = clk_vco_round_rate,
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.set_rate = clk_vco_set_rate,
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};
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struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
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const char *vco_gate_name, const char *parent_name,
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unsigned long flags, void __iomem *mode_reg, void __iomem
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*cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
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spinlock_t *lock, struct clk **pll_clk,
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struct clk **vco_gate_clk)
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{
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struct clk_vco *vco;
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struct clk_pll *pll;
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struct clk *vco_clk, *tpll_clk, *tvco_gate_clk;
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struct clk_init_data vco_init, pll_init;
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const char **vco_parent_name;
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if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg ||
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!rtbl || !rtbl_cnt) {
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pr_err("Invalid arguments passed");
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return ERR_PTR(-EINVAL);
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}
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vco = kzalloc(sizeof(*vco), GFP_KERNEL);
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if (!vco) {
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pr_err("could not allocate vco clk\n");
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return ERR_PTR(-ENOMEM);
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}
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll) {
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pr_err("could not allocate pll clk\n");
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goto free_vco;
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}
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/* struct clk_vco assignments */
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vco->mode_reg = mode_reg;
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vco->cfg_reg = cfg_reg;
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vco->rtbl = rtbl;
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vco->rtbl_cnt = rtbl_cnt;
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vco->lock = lock;
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vco->hw.init = &vco_init;
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pll->vco = vco;
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pll->hw.init = &pll_init;
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if (vco_gate_name) {
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tvco_gate_clk = clk_register_gate(NULL, vco_gate_name,
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parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
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if (IS_ERR_OR_NULL(tvco_gate_clk))
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goto free_pll;
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if (vco_gate_clk)
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*vco_gate_clk = tvco_gate_clk;
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vco_parent_name = &vco_gate_name;
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} else {
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vco_parent_name = &parent_name;
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}
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vco_init.name = vco_name;
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vco_init.ops = &clk_vco_ops;
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vco_init.flags = flags;
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vco_init.parent_names = vco_parent_name;
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vco_init.num_parents = 1;
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pll_init.name = pll_name;
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pll_init.ops = &clk_pll_ops;
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pll_init.flags = CLK_SET_RATE_PARENT;
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pll_init.parent_names = &vco_name;
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pll_init.num_parents = 1;
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vco_clk = clk_register(NULL, &vco->hw);
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if (IS_ERR_OR_NULL(vco_clk))
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goto free_pll;
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tpll_clk = clk_register(NULL, &pll->hw);
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if (IS_ERR_OR_NULL(tpll_clk))
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goto free_pll;
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if (pll_clk)
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*pll_clk = tpll_clk;
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return vco_clk;
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free_pll:
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kfree(pll);
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free_vco:
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kfree(vco);
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pr_err("Failed to register vco pll clock\n");
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return ERR_PTR(-ENOMEM);
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}
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36
drivers/clk/spear/clk.c
Normal file
36
drivers/clk/spear/clk.c
Normal file
@ -0,0 +1,36 @@
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/*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* SPEAr clk - Common routines
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*/
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#include <linux/clk-provider.h>
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#include <linux/types.h>
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#include "clk.h"
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long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
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unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
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int *index)
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{
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unsigned long prev_rate, rate = 0;
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for (*index = 0; *index < rtbl_cnt; (*index)++) {
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prev_rate = rate;
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rate = calc_rate(hw, parent_rate, *index);
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if (drate < rate) {
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/* previous clock was best */
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if (*index) {
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rate = prev_rate;
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(*index)--;
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}
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break;
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}
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}
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return rate;
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}
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58
drivers/clk/spear/clk.h
Normal file
58
drivers/clk/spear/clk.h
Normal file
@ -0,0 +1,58 @@
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/*
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* Clock framework definitions for SPEAr platform
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*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
|
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __SPEAR_CLK_H
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#define __SPEAR_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/spinlock_types.h>
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#include <linux/types.h>
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/* VCO-PLL clk */
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struct pll_rate_tbl {
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u8 mode;
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u16 m;
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u8 n;
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u8 p;
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};
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struct clk_vco {
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struct clk_hw hw;
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void __iomem *mode_reg;
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void __iomem *cfg_reg;
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struct pll_rate_tbl *rtbl;
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u8 rtbl_cnt;
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spinlock_t *lock;
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};
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struct clk_pll {
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struct clk_hw hw;
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struct clk_vco *vco;
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const char *parent[1];
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
|
||||
int index);
|
||||
|
||||
/* clk register routines */
|
||||
struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
|
||||
const char *vco_gate_name, const char *parent_name,
|
||||
unsigned long flags, void __iomem *mode_reg, void __iomem
|
||||
*cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
|
||||
spinlock_t *lock, struct clk **pll_clk,
|
||||
struct clk **vco_gate_clk);
|
||||
|
||||
long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
|
||||
unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
|
||||
int *index);
|
||||
|
||||
#endif /* __SPEAR_CLK_H */
|
||||
Loading…
Reference in New Issue
Block a user