arm-smmu: add smmu testbus dump support for gen3auto

Add gen3auto based values for ARM_SMMU_STATS_SYNC_INV_TBU_ACK,
ARM_SMMU_TESTBUS_SEL & ARM_SMMU_TESTBUS registers.

Modify TESTBUS tcu base offset
ARM_SMMU_TCU_TESTBUS_HLOS1_NS -> ARM_SMMU_TESTBUS_SEL_HLOS1_NS
and sync invalid TBU acknowledgment as
ARM_SMMU_IMPL_DEF0 instead ARM_SMMU_IMPL_DEF5.

Change-Id: I4040932104e6630690e1c6bfa54f889b9432b9bb
Signed-off-by: Madhu Ananthula <quic_mananthu@quicinc.com>
This commit is contained in:
Madhu Ananthula 2024-04-25 12:40:25 +05:30
parent 5b40ea9ae2
commit 544da6541b
3 changed files with 27 additions and 3 deletions

View File

@ -537,6 +537,16 @@ config ARM_SMMU_TESTBUS_DUMP
If unsure, say N here.
config ARM_SMMU_TESTBUS_DUMP_GEN3AUTO
bool "ARM SMMU testbus dump for gen3auto"
depends on ARM_SMMU && ARM_SMMU_TESTBUS && ARM_SMMU_TESTBUS_DUMP
help
Enables testbus dump collection on arm smmu right after TLB
sync timeout failure on gen3auto.
Note to use this only on debug builds.
If unsure, say N here.
config QCOM_LAZY_MAPPING
tristate "Reference counted iommu-mapping support"
depends on QCOM_DMABUF_HEAPS

View File

@ -1,13 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifdef CONFIG_ARM_SMMU_TESTBUS_DUMP_GEN3AUTO
#define ARM_SMMU_TESTBUS_SEL 0x2524
#define ARM_SMMU_TESTBUS 0x2528
#define ARM_SMMU_TCU_TESTBUS_HLOS1_NS ARM_SMMU_TESTBUS_SEL_HLOS1_NS
#else
#define ARM_SMMU_TESTBUS_SEL 0x25E4
#define ARM_SMMU_TESTBUS 0x25E8
#define ARM_SMMU_TESTBUS_SEL_HLOS1_NS 0x8
#define ARM_SMMU_TCU_TESTBUS_HLOS1_NS 0x28
#endif
#define ARM_SMMU_TESTBUS_SEL_HLOS1_NS 0x8
#define DEBUG_TESTBUS_SEL_TBU 0x50
#define DEBUG_TESTBUS_TBU 0x58

View File

@ -6,7 +6,7 @@
*
* Author: Will Deacon <will.deacon@arm.com>
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _ARM_SMMU_H
@ -266,7 +266,11 @@ enum arm_smmu_cbar_type {
/* Implementation Defined Register Space 5 registers*/
/* Relative to IMPL_DEF5 page */
#ifdef CONFIG_ARM_SMMU_TESTBUS_DUMP_GEN3AUTO
#define ARM_SMMU_STATS_SYNC_INV_TBU_ACK 0x51c
#else
#define ARM_SMMU_STATS_SYNC_INV_TBU_ACK 0x5dc
#endif
#define TBU_SYNC_ACK GENMASK(31, 17)
#define TBU_SYNC_REQ BIT(16)
#define TBU_INV_ACK GENMASK(15, 1)
@ -689,7 +693,11 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
*/
#define ARM_SMMU_IMPL_DEF0 2
#define ARM_SMMU_IMPL_DEF4 6
#ifdef CONFIG_ARM_SMMU_TESTBUS_DUMP_GEN3AUTO
#define ARM_SMMU_IMPL_DEF5 ARM_SMMU_IMPL_DEF0
#else
#define ARM_SMMU_IMPL_DEF5 7
#endif
#define ARM_SMMU_CB(s, n) ((s)->numpage + (n))