arm-smmu: add smmu testbus dump support for gen3auto
Add gen3auto based values for ARM_SMMU_STATS_SYNC_INV_TBU_ACK, ARM_SMMU_TESTBUS_SEL & ARM_SMMU_TESTBUS registers. Modify TESTBUS tcu base offset ARM_SMMU_TCU_TESTBUS_HLOS1_NS -> ARM_SMMU_TESTBUS_SEL_HLOS1_NS and sync invalid TBU acknowledgment as ARM_SMMU_IMPL_DEF0 instead ARM_SMMU_IMPL_DEF5. Change-Id: I4040932104e6630690e1c6bfa54f889b9432b9bb Signed-off-by: Madhu Ananthula <quic_mananthu@quicinc.com>
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@ -537,6 +537,16 @@ config ARM_SMMU_TESTBUS_DUMP
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If unsure, say N here.
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config ARM_SMMU_TESTBUS_DUMP_GEN3AUTO
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bool "ARM SMMU testbus dump for gen3auto"
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depends on ARM_SMMU && ARM_SMMU_TESTBUS && ARM_SMMU_TESTBUS_DUMP
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help
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Enables testbus dump collection on arm smmu right after TLB
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sync timeout failure on gen3auto.
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Note to use this only on debug builds.
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If unsure, say N here.
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config QCOM_LAZY_MAPPING
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tristate "Reference counted iommu-mapping support"
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depends on QCOM_DMABUF_HEAPS
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@ -1,13 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifdef CONFIG_ARM_SMMU_TESTBUS_DUMP_GEN3AUTO
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#define ARM_SMMU_TESTBUS_SEL 0x2524
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#define ARM_SMMU_TESTBUS 0x2528
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#define ARM_SMMU_TCU_TESTBUS_HLOS1_NS ARM_SMMU_TESTBUS_SEL_HLOS1_NS
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#else
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#define ARM_SMMU_TESTBUS_SEL 0x25E4
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#define ARM_SMMU_TESTBUS 0x25E8
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#define ARM_SMMU_TESTBUS_SEL_HLOS1_NS 0x8
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#define ARM_SMMU_TCU_TESTBUS_HLOS1_NS 0x28
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#endif
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#define ARM_SMMU_TESTBUS_SEL_HLOS1_NS 0x8
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#define DEBUG_TESTBUS_SEL_TBU 0x50
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#define DEBUG_TESTBUS_TBU 0x58
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@ -6,7 +6,7 @@
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _ARM_SMMU_H
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@ -266,7 +266,11 @@ enum arm_smmu_cbar_type {
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/* Implementation Defined Register Space 5 registers*/
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/* Relative to IMPL_DEF5 page */
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#ifdef CONFIG_ARM_SMMU_TESTBUS_DUMP_GEN3AUTO
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#define ARM_SMMU_STATS_SYNC_INV_TBU_ACK 0x51c
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#else
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#define ARM_SMMU_STATS_SYNC_INV_TBU_ACK 0x5dc
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#endif
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#define TBU_SYNC_ACK GENMASK(31, 17)
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#define TBU_SYNC_REQ BIT(16)
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#define TBU_INV_ACK GENMASK(15, 1)
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@ -689,7 +693,11 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
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*/
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#define ARM_SMMU_IMPL_DEF0 2
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#define ARM_SMMU_IMPL_DEF4 6
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#ifdef CONFIG_ARM_SMMU_TESTBUS_DUMP_GEN3AUTO
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#define ARM_SMMU_IMPL_DEF5 ARM_SMMU_IMPL_DEF0
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#else
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#define ARM_SMMU_IMPL_DEF5 7
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#endif
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#define ARM_SMMU_CB(s, n) ((s)->numpage + (n))
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