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Merge "clk: qcom: cliffs: Add support for GCC and GPUCC on cliffs"

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qctecmdr 2023-07-16 19:21:17 -07:00 committed by Gerrit - the friendly Code Review server
commit 50a530fb96
4 changed files with 3889 additions and 0 deletions
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18
drivers/clk/qcom/Kconfig
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@ -1229,6 +1229,24 @@ config SM_DEBUGCC_6150
Say Y if you want to support the debug clocks such as
clock measurement functionality.
config SM_GCC_CLIFFS
tristate "Cliffs Global Clock Controller"
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on Qualcomm Technologies, Inc
Cliffs devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GPUCC_CLIFFS
tristate "CLIFFS Graphics Clock Controller"
select SM_GCC_CLIFFS
help
Support for the graphics clock controller on Qualcomm Technologies, Inc
Cliffs devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
endif
config VIRTIO_CLK

2
drivers/clk/qcom/Makefile
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@ -136,6 +136,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
obj-$(CONFIG_SM_GCC_BLAIR) += gcc-blair.o
obj-$(CONFIG_SM_GCC_CLIFFS) += gcc-cliffs.o
obj-$(CONFIG_SM_GCC_HOLI) += gcc-holi.o
obj-$(CONFIG_SM_GCC_PINEAPPLE) += gcc-pineapple.o
obj-$(CONFIG_SM_GPUCC_6150) += gpucc-sm6150.o
@ -155,6 +156,7 @@ obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
obj-$(CONFIG_SM_GPUCC_BLAIR) += gpucc-blair.o
obj-$(CONFIG_SM_GPUCC_CLIFFS) += gpucc-cliffs.o
obj-$(CONFIG_SM_GPUCC_HOLI) += gpucc-holi.o
obj-$(CONFIG_SM_GPUCC_PINEAPPLE) += gpucc-pineapple.o
obj-$(CONFIG_SM_VIDEOCC_6150) += videocc-sm6150.o

3199
drivers/clk/qcom/gcc-cliffs.c Normal file
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File diff suppressed because it is too large Load Diff

670
drivers/clk/qcom/gpucc-cliffs.c Normal file
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@ -0,0 +1,670 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-cliffs.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "vdd-level.h"
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_LOW + 1, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mx, VDD_LOW + 1, 1, vdd_corner);
static DEFINE_VDD_REGULATORS(vdd_mxc, VDD_NOMINAL + 1, 1, vdd_corner);
static struct clk_vdd_class *gpu_cc_cliffs_regulators[] = {
&vdd_cx,
&vdd_mx,
&vdd_mxc,
};
static struct clk_vdd_class *gpu_cc_cliffs_regulators_1[] = {
&vdd_cx,
&vdd_mx,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
/* 520MHz Configuration */
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x1b,
.cal_l = 0x44,
.cal_l_ringosc = 0x44,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ole_ops,
},
.vdd_data = {
.vdd_class = &vdd_mxc,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 615000000,
[VDD_LOW] = 1100000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000,
[VDD_HIGH_L1] = 2300000000},
},
},
};
/* 440MHz Configuration */
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x16,
.cal_l = 0x44,
.cal_l_ringosc = 0x44,
.alpha = 0xeaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ole_ops,
},
.vdd_data = {
.vdd_class = &vdd_mx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 615000000,
[VDD_LOW] = 1100000000,
[VDD_LOW_L1] = 1600000000,
[VDD_NOMINAL] = 2000000000,
[VDD_HIGH_L1] = 2300000000},
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "gpll0_out_main" },
{ .fw_name = "gpll0_out_main_div" },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gpll0_out_main" },
{ .fw_name = "gpll0_out_main_div" },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gpll0_out_main" },
{ .fw_name = "gpll0_out_main_div" },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_3_ao[] = {
{ .fw_name = "bi_tcxo_ao" },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x91b8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.enable_safe_config = true,
.flags = HW_CLK_CTRL_MODE,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 200000000},
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9168,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.enable_safe_config = true,
.flags = HW_CLK_CTRL_MODE,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_classes = gpu_cc_cliffs_regulators_1,
.num_vdd_classes = ARRAY_SIZE(gpu_cc_cliffs_regulators_1),
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 220000000,
[VDD_LOW] = 550000000},
},
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x919c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.enable_safe_config = true,
.flags = HW_CLK_CTRL_MODE,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
.clkr.vdd_data = {
.vdd_class = &vdd_cx,
.num_rate_max = VDD_NUM,
.rate_max = (unsigned long[VDD_NUM]) {
[VDD_LOWER_D1] = 200000000},
},
};
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
.enable_safe_config = true,
.flags = HW_CLK_CTRL_MODE,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3_ao,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x902c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
.reg = 0x9028,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x90c8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x90c8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x90cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_accu_shift_clk = {
.halt_reg = 0x9108,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9108,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_accu_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x90f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90f8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x90e4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90e4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x90f0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90f0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_freq_measure_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x9198,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9198,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x90f4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90f4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x90fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90fc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x9158,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9158,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
.halt_reg = 0x915c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x915c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x90dc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gpu_cc_cliffs_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
};
static const struct qcom_reset_map gpu_cc_cliffs_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x9180 },
[GPUCC_GPU_CC_CB_BCR] = { 0x918c },
[GPUCC_GPU_CC_CX_BCR] = { 0x9088 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x9194 },
[GPUCC_GPU_CC_FF_BCR] = { 0x91b4 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x910c },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9164 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9030 },
[GPUCC_GPU_CC_RBCPR_BCR] = { 0x9118 },
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
};
static const struct regmap_config gpu_cc_cliffs_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9988,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_cliffs_desc = {
.config = &gpu_cc_cliffs_regmap_config,
.clks = gpu_cc_cliffs_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_cliffs_clocks),
.resets = gpu_cc_cliffs_resets,
.num_resets = ARRAY_SIZE(gpu_cc_cliffs_resets),
.clk_regulators = gpu_cc_cliffs_regulators,
.num_clk_regulators = ARRAY_SIZE(gpu_cc_cliffs_regulators),
};
static const struct of_device_id gpu_cc_cliffs_match_table[] = {
{ .compatible = "qcom,cliffs-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_cliffs_match_table);
static int gpu_cc_cliffs_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gpu_cc_cliffs_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep clocks always enabled:
* gpu_cc_cxo_aon_clk
* gpu_cc_demet_clk
*/
regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &gpu_cc_cliffs_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
return ret;
}
dev_info(&pdev->dev, "Registered GPU CC clocks\n");
return ret;
}
static void gpu_cc_cliffs_sync_state(struct device *dev)
{
qcom_cc_sync_state(dev, &gpu_cc_cliffs_desc);
}
static struct platform_driver gpu_cc_cliffs_driver = {
.probe = gpu_cc_cliffs_probe,
.driver = {
.name = "gpu_cc-cliffs",
.of_match_table = gpu_cc_cliffs_match_table,
.sync_state = gpu_cc_cliffs_sync_state,
},
};
static int __init gpu_cc_cliffs_init(void)
{
return platform_driver_register(&gpu_cc_cliffs_driver);
}
subsys_initcall(gpu_cc_cliffs_init);
static void __exit gpu_cc_cliffs_exit(void)
{
platform_driver_unregister(&gpu_cc_cliffs_driver);
}
module_exit(gpu_cc_cliffs_exit);
MODULE_DESCRIPTION("QTI GPU_CC CLIFFS Driver");
MODULE_LICENSE("GPL");