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V_01-00-41

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1. DMA channel status cleared only for SW path allocated DMA channels. IPA path DMA channel status clearing is skipped.
2. Ethtool statistics added to print doorbell SRAM area for all the channels.
This commit is contained in:
TC956X 2022-02-04 17:11:24 +09:00 committed by jianzhou
parent b7b5fb6a60
commit 4d94d05dd1
6 changed files with 82 additions and 5 deletions
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9
Readme.md
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@ -1,7 +1,7 @@
# Toshiba Electronic Devices & Storage Corporation TC956X PCIe Ethernet Host Driver
Release Date: 02 Feb 2022
Release Date: 04 Feb 2022
Release Version: V_01-00-40 : Limited-tested version
Release Version: V_01-00-41 : Limited-tested version
TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
@ -454,3 +454,8 @@ TC956X PCIe EMAC driver is based on "Fedora 30, kernel-5.4.19".
## TC956X_Host_Driver_20220202_V_01-00-40:
1. Tx Queue flushed and checked for status after Tx DMA stop.
## TC956X_Host_Driver_20220204_V_01-00-41:
1. DMA channel status cleared only for SW path allocated DMA channels. IPA path DMA channel status clearing is skipped.
2. Ethtool statistics added to print doorbell SRAM area for all the channels.

6
common.h
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@ -75,6 +75,8 @@
* VERSION : 01-00-38
* 31 Jan 2022 : 1. Additional macros defined for debug dump API usage.
* VERSION : 01-00-39
* 04 Feb 2021 : 1. Ethtool statistics added to print doorbell SRAM area for all the channels.
* VERSION : 01-00-41
*/
#ifndef __COMMON_H__
@ -1379,6 +1381,10 @@ struct tc956xmac_extra_stats {
u64 m3_tx_timeout_port0;
u64 m3_tx_timeout_port1;
u64 m3_debug_cnt19;
u64 m3_tx_pcie_addr_loc_port0[TC956XMAC_CH_MAX];
u64 m3_tx_pcie_addr_loc_port1[TC956XMAC_CH_MAX];
u64 m3_rx_pcie_addr_loc_port0[TC956XMAC_CH_MAX];
u64 m3_rx_pcie_addr_loc_port1[TC956XMAC_CH_MAX];
};

4
tc956x_pci.c
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@ -138,6 +138,8 @@
* VERSION : 01-00-39
* 02 Feb 2022 : 1. Version update
* VERSION : 01-00-40
* 04 Feb 2022 : 1. Version update
* VERSION : 01-00-41
*/
#include <linux/clk-provider.h>
@ -202,7 +204,7 @@ static unsigned int mac1_txq1_size = TX_QUEUE1_SIZE;
unsigned int mac0_en_lp_pause_frame_cnt = DISABLE;
unsigned int mac1_en_lp_pause_frame_cnt = DISABLE;
static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 4, 0};
static const struct tc956x_version tc956x_drv_version = {0, 1, 0, 0, 4, 1};
static int tc956xmac_pm_usage_counter; /* Device Usage Counter */
struct mutex tc956x_pm_suspend_lock; /* This mutex is shared between all available EMAC ports. */

4
tc956xmac.h
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@ -127,6 +127,8 @@
* VERSION : 01-00-39
* 02 Feb 2022 : 1. Version update
* VERSION : 01-00-40
* 04 Feb 2022 : 1. Version update
* VERSION : 01-00-41
*/
#ifndef __TC956XMAC_H__
@ -182,7 +184,7 @@
#define IRQ_DEV_NAME(x) (((x) == RM_PF0_ID) ? ("eth0") : ("eth1"))
#define WOL_IRQ_DEV_NAME(x) (((x) == RM_PF0_ID) ? ("eth0_wol") : ("eth1_wol"))
#define DRV_MODULE_VERSION "V_01-00-40"
#define DRV_MODULE_VERSION "V_01-00-41"
#define TC956X_FW_MAX_SIZE (64*1024)
#define ATR_AXI4_SLV_BASE 0x0800

51
tc956xmac_ethtool.c
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@ -48,6 +48,8 @@
* VERSION : 01-00-24
* 10 Dec 2021 : 1. Added link partner pause frame count debug counters to ethtool statistics.
* VERSION : 01-00-31
* 04 Feb 2021 : 1. Ethtool statistics added to print doorbell SRAM area for all the channels.
* VERSION : 01-00-41
*/
#include <linux/etherdevice.h>
@ -669,6 +671,39 @@ static const struct tc956xmac_stats tc956xmac_gstrings_stats[] = {
TC956XMAC_STAT(m3_tx_timeout_port0),
TC956XMAC_STAT(m3_tx_timeout_port1),
TC956XMAC_STAT(m3_debug_cnt19),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port0[0]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port0[1]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port0[2]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port0[3]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port0[4]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port0[5]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port0[6]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port0[7]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port1[0]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port1[1]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port1[2]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port1[3]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port1[4]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port1[5]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port1[6]),
TC956XMAC_STAT(m3_tx_pcie_addr_loc_port1[7]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port0[0]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port0[1]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port0[2]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port0[3]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port0[4]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port0[5]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port0[6]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port0[7]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port1[0]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port1[1]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port1[2]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port1[3]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port1[4]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port1[5]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port1[6]),
TC956XMAC_STAT(m3_rx_pcie_addr_loc_port1[7]),
};
#define TC956XMAC_STATS_LEN ARRAY_SIZE(tc956xmac_gstrings_stats)
@ -1120,6 +1155,22 @@ static void tc956xmac_m3fw_stats_read(struct tc956xmac_priv *priv)
(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT18 )));
priv->xstats.m3_debug_cnt19 = readl(priv->tc956x_SRAM_pci_base_addr +
(TC956X_M3_SRAM_DEBUG_CNTS_OFFSET + (DB_CNT_LEN * DB_CNT19 )));
for (chno = 0; chno < tx_queues_count; chno++) {
priv->xstats.m3_tx_pcie_addr_loc_port0[chno] = readl(priv->tc956x_SRAM_pci_base_addr +
(SRAM_TX_PCIE_ADDR_LOC + (chno * 4 )));
}
for (chno = 0; chno < tx_queues_count; chno++) {
priv->xstats.m3_tx_pcie_addr_loc_port1[chno] = readl(priv->tc956x_SRAM_pci_base_addr +
(SRAM_TX_PCIE_ADDR_LOC + (TC956XMAC_CH_MAX * 4) + (chno * 4 )));
}
for (chno = 0; chno < rx_queues_count; chno++) {
priv->xstats.m3_rx_pcie_addr_loc_port0[chno] = readl(priv->tc956x_SRAM_pci_base_addr +
(SRAM_RX_PCIE_ADDR_LOC + (chno * 4 )));
}
for (chno = 0; chno < rx_queues_count; chno++) {
priv->xstats.m3_rx_pcie_addr_loc_port1[chno] = readl(priv->tc956x_SRAM_pci_base_addr +
(SRAM_RX_PCIE_ADDR_LOC + (TC956XMAC_CH_MAX * 4) + (chno * 4 )));
}
}

13
tc956xmac_main.c
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@ -103,6 +103,8 @@
* VERSION : 01-00-37
* 31 Jan 2022 : 1. Debug dump API supported to dump registers during crash.
* VERSION : 01-00-39
* 04 Feb 2022 : 1. DMA channel status cleared only for SW path allocated DMA channels. IPA path DMA channel status clearing is skipped.
* VERSION : 01-00-41
*/
#include <linux/clk.h>
@ -4120,10 +4122,19 @@ static void tc956xmac_dma_interrupt(struct tc956xmac_priv *priv)
if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
channels_to_check = ARRAY_SIZE(status);
for (chan = 0; chan < channels_to_check; chan++)
for (chan = 0; chan < channels_to_check; chan++) {
/* Assuming DMA Tx and Rx channels are used as pairs */
if ((priv->plat->tx_dma_ch_owner[chan] != USE_IN_TC956X_SW) ||
(priv->plat->rx_dma_ch_owner[chan] != USE_IN_TC956X_SW))
continue;
status[chan] = tc956xmac_napi_check(priv, chan);
}
for (chan = 0; chan < tx_channel_count; chan++) {
if (priv->plat->tx_dma_ch_owner[chan] != USE_IN_TC956X_SW)
continue;
if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
/* Try to bump up the dma threshold on this failure */
if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&